hochschule fu r angewandte wissenschaften hamburg Prof. Dr. B. Schwarz FB Elektrotechnik/Informatik

Transcription

1 8 Shift Registers A Johnson counter contains the basic structure of a shift register which is made up by a chain of D- FFs. Beginning with the LSB of a register (a number of D-FFs) each D-FF output can be connected to the data input of the D-FF with next higher weight. This chain of D-FFs includes the ability to shift the bits of the register to the left (LSB to MSB) or to the right (MSB to LSB). For example, a sequence of bits can be converted into a word by shifting the bits into a register and moving the bits along at each clock edge. After a sufficient number of clock edges, namely the number n of D-FFs, the n bits of a word are available as a single word. This is known as a serial-in and parallel-out register. Applications of shift registers will be found in serial communication interfaces. The receiver input device will clock in a data stream of sequenced bits and a parallel word will be accessed by internal processes. A sender will clock out a parallel stored word over a serial register output. Simple multiply and division operations can be performed by a shift register. A multiplication by two will be done with a shift left by one bit. Digital Circuits I 8-

2 Direction of shift is described by the weight of bits: Shift right: from MSB to LSB Shift left: from LSB to MSB The direct chaining of flip-flops is allowed because each time the clock gates of all flip-flops are opened the inputs are connected to stable output signal levels. If the output transition occurs after a certain propagation delay the clock gates are deactivated. Device example: 8-bit shift register SN74xx9 (8 stages). Serial shift input (LSB) is an AND gate. Shift right result Q is available in uncomplemented and complemented form. serial serial Input 5 stages output. clock edge 2. clock edge 3. clock edge 4. clock edge Digital Circuits I 8-2

3 8. 3-bit Serial-to-Parallel Converter In serial communications, such a shift register is used to receive a serial bit stream and support connected components with a parallel data word: bitfi n-bit. Serial data is read in at the shift input SE which appears at the REG register outputs. Control signal X distinguishes operational modes: X = : shift right, register outputs deactivated. X = : no shift, register outputs enabled Remember: Never delay clock lines with combinational logic! This example is just a symbolic schematic. Give suggestions for a professional solution! Digital Circuits I 8-3

4 VHDL description of an n-bit serial-to-parallel converter Parameterised register width with generic-statement. 2 processes: - clock edge gated internal shift register INTREG, - combinational output logic controlled by signal X and register state. Shift operation done with a for-loop. Loop subscript I does not need to be declared explicitly. Shift right: INTREG(I) <= INTREG(I-) entity SRG_NBIT is generic(n : natural :=3); -- number of bits equal to 3 port( CLK, SE, RESET, X: in bit; REG: out bit_vector(n- downto )); -- register with N flip-flops end SRG_NBIT; Digital Circuits I 8-4

5 architecture BEHAVE of SRG_NBIT is signal INTREG: bit_vector(n- downto ); begin P: process(clk, RESET) -- shift register begin if RESET='' then INTREG <= (others => '') after ns; elsif (CLK='' and CLK'event) then -- positive edge if X='' then -- professional synchronous enable!!!!! for I in N- downto loop -- shift to MSB (left) INTREG(I) <= INTREG(I-) after ns; end loop; INTREG() <= SE after ns; -- shift input copied into LSB end if; end if; end process P; P2: process(x, INTREG) -- output enable, combinational logic begin if X='' then REG <= INTREG after ns; else REG <= (others=>'') after ns; end if; end process P2; end BEHAVE; Digital Circuits I 8-5

6 All flip-flops are clocked at the same time. Shift is enabled if X =. Output is enabled if X = ''. Reliable shift functionality because of: Propagation delay t plh is larger than hold time t H. Simulation waveform of a 3-bit serial-to-parallel converter Digital Circuits I 8-6

7 8.2 Parallel-to-Serial Converter Shift registers are used as parallel-to-serial converters in transmitter components of transceiver devices: n-bitfi -bit A parallel load input E[2:] and a shift output SA = Q(2) is needed. Control of operation mode by signal X: X='' : shift left, inputs disabled, LSB will always be loaded with X='' : inputs are enabled, parallel data are stored with the next clock. All stages are identical therefore only one stage has to be designed fi Consider stage Q E X Combinational Logic D X Q E D D : 2 X E 4 6 X 5 7 E 3 X Q Q Digital Circuits I 8-7

8 Synthesized schematic of a 3-bit parallel-to-serial converter Next state forming logic interfaces between adjacent stages are identical. The LSB stage is driven by (Pulldown Resistor) The MSB will be first seen at the SA output. Digital Circuits I 8-8

9 VHDL code for a 3-bit parallel-to-serial converter entity PAR_SER is generic(n : natural :=3); -- number of bits, initialised with 3 port( CLK, RESET, X: in bit; E: in bit_vector(n- downto ); -- parallel data input SA: out bit); -- shift output end PAR_SER; architecture VERHALTEN of PAR_SER is signal INTREG: bit_vector(n- downto ); begin P: process(clk, RESET) -- shift register begin if RESET='' then INTREG <= (others => '') after ns; elsif (CLK='' and CLK'event) then -- rising edge if X='' then INTREG <= INTREG(N-2 downto ) & after ns; -- shift left else end if; end if; end process P; SA <= INTREG(N-); end VERHALTEN; INTREG <= E after ns; -- parallel data load -- MSB: shift output Digital Circuits I 8-9

10 Simulation waveforms of the parallel-to-serial converter Digital Circuits I 8-

11 8.3 Linear Feedback Shift Register (LFSR) A shift register with a feedback path via XOR gates to the LSB input generates pseudorandom test patterns that are useful in testing both combinational and sequential machines. A 4-bit LFSR which has an XOR feedback of bit numbers 2 and 3, will be initialised with 䀡 and it sequences through 5 of the 6 states. It is not allowed to enter the 䀡 state since that is a hang state because XOR will not generate a which is the start of the pseudorandom sequence. Register width XOR- feedback register output subscripts 2,3 4,5 3,6 2,4 6,7 4,8 6,9 8, 5,7, 4-bit pseudorandom counting pattern Q 3 Q 2 Q Q Q/h Y D A 5 B 7 F E C 8 Digital Circuits I 8-

12 Schematic and simulation waveform of a 4-bit LFSR Digital Circuits I 8-2