Electrically Erasable Programmable Logic Devices as an Aid for Teaching Digital Electronics

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1 Iowa State University From the SelectedWorks of Stuart J. Birrell 988 Electrically Erasable Programmable Logic Devices as an Aid for Teaching Digital Electronics Nelson L. Buck, University of Illinois at Urbana-Champaign Kenneth A. Sudduth, United States Department of Agriculture Stuart J. Birrell, University of Illinois at Urbana-Champaign Available at:

2 Electrically Erasable Programmable Logic Devices as an Aid for Teaching Digital Electronics Nelson L. Buck, Kenneth A. Sudduth, Stuart J. Birrell ASSOC. MEMBER ASSOC. MEMBER STUDENT MEMBER ASAE ASAE ASAE ABSTRACT ELECTRICALLY erasable programmable logic devices (PLDs) are digital circuit components which can be programmed to perform complex logic functions. Agricultural engineering students designed circuits using PLDs and programmed and tested them as part of a class exercise in logic circuit design. The devices were erased at the end of the semester for use by the next class. Because the lab assignment required the students to master several new concepts at once, they experienced some initial difficulties; however, they enjoyed the assignment and learned the material well. INTRODUCTION As the use of electronics increases in the agriculture industry, agricultural engineers are being called on to develop electronic circuitry. Among the functions of electronic devices are feeding animals, controlling tractors and implements, and controlling the environment in buildings. In recognition of the growing importance of electronics, the American Society of Agricultural Engineers recently created an Electrical and Electronic Systems Division. The teaching of digital electronics has become an important job of the agricultural engineering educator. A Programmable Logic Device (PLD) is a digital integrated circuit which can make a circuit designer's job easier in several ways:. One PLD can replace two to four conventional TTL chips, so the use of PLDs allows a logic circuit to be shrunk onto a smaller printed circuit board. If the circuit occupies several boards in its TTL version, the use of PLDs allows fewer boards to be used. The cost of the additional or larger boards is avoided, the time required to lay out additional boards is saved, fewer slots are occupied on the system bus, and the problems of interconnecting circuit boards are reduced. 2. The function of one pin on a PLD may be easily interchanged with that of another pin. If there is a problem routing a circuit board conductor to one of the pins, it is possible to simply route it to another pin instead and reprogram the chip. This capability can greatly simplify board layout. Article was submitted for publication in August, 987; reviewed and approved for publication by the Electrical and Electronic Systems Division of ASAE in March, 988. Presented as ASAE Paper No The authors are: NELSON L. BUCK, Assistant Professor, Agricultural Engineering Dept, University of Illinois, Urbana; KENNETH A. SUDDUTH, Agricultural Engineer, USDA-ARS, Urbana; and STUART J. BIRRELL, Graduate Research Assistant, Agricultural Engineering Dept., University of Illinois, Urbana. 3. The signals in a circuit made with PLDs often travel through fewer gates than in a circuit using conventional logic chips, allowing faster operation. 4. It is actually easier to design a circuit using PLDs instead of conventional chips. The applications of PLDs have little overlap with those of microprocessors and programmable read-only memories (PROMs). A PLD is an alternative to hardwired digital logic. It cannot execute a complex program or perform arithmetic like a microprocessor, and it cannot store data or a set of instructions like a PROM. It can, however, perform logical operations on a set of binary input signals and generate binary outputs to control other devices. The control functions can be altered by re-programming the chip instead of re-wiring the circuit. A PLD with internal flip-flops can also execute a short sequence of logic operations, which might be considered a simple program. PLDs are well suited to applications where speed and space are important and the functions to be performed are simple. PRINCIPLE OF OPERATION A PLD contains many interconnected gates and the circuitry to break selected connections. By breaking connections, a circuit designer programs the device to perform complex logic functions. Before the connections are broken, the circuit is nonfunctional. The devices which program PLDs are similar to those used to program PROMs. A high voltage applied to a specific pin enables the addressing circuitry on the chip, so individual AND gate inputs can be addressed. In the earlier PLDs these inputs contained fuses, and applying a high current to the appropriate pin melted the desired fuse. Of course, such a chip could not be reprogrammed, so any changes to the circuit required throwing away the chip. The circuit diagram of such a PLD was called a "fuse map". Newer PLDs use floating-gate field effect transistors (FETs) instead of fuses; however, due to long-standing tradition, their circuit diagrams are still called "fuse maps". Depending upon the type of FET used, the broken connections can be re-established either by exposing the chip to ultraviolet light (a UV-erasable PLD) or by applying an electrical signal (an electrically erasable PLD). This process erases the chip's program. After erasing, the chip can be re-used. Typical PLD Internal Circuit A typical PLD might contain the very general circuit shown in Fig.. The inputs and their complements are connected to multiple-input AND gates, the outputs of which are connected to a multiple-input OR gate, which produces an output. The Boolean equation which American Society of Agricultural Engineers /88/42-8$2. APPLIED ENGINEERING in AGRICULTURE

3 A B C D B B I I \ I M II D- OUTPUT Fig. 2 An 8-input AND gate, as represented in a PLD circuit diagram. Fig. A simple Programmable Logic Device (unprogrammed). describes Fig. is: Y = A*A*B*B*C*C*D*D + A*A*B*B*C*C*D*D + A*A*B*B*C*C*D*D + A*A*B*B*C*C*D*D Where an AND operation is represented by "*" and an OR is represented by " + ". Because it looks like an algebraic sum of product terms, this equation is called a "sum of products" equation. Before programming, the value of each product term in this equation, and therefore the output Y, is always zero, because each input is ANDed with its inverse. The connections which are selectively broken to make the device useful are at the inputs to the AND gates, and are shown in Fig. as black dots. The inputs of the AND gates are designed to float high (logic "") when the connections are broken, so breaking the connection to any input effectively removes it from the equation ( AND == ). Breaking all of the inputs to any AND gate forces the corresponding product term, and therefore the output Y, to be a "". If none of the connections to an AND gate are broken, the corresponding product term remains at "" and can be ignored ( OR = ). The representation of a multiple-input AND gate used in Fig. becomes clumsy when the number of inputs becomes large, so circuit diagrams of real PLDs use the symbol shown in Fig. 2 instead. This can be thought of as the symbol used in Fig. turned on its side, so the input wires line up behind one another. Each dot in Fig. 2 represents a connection to an input (a fuse or a FET). If a wire crosses the input line without a dot, there is no connection from that wire to an input. Configuring a PLD to Match a Truth Table The usefulness of the type of circuit shown in Fig. lies in the fact that any arbitrary truth table can be converted directly to a sum of products equation. This is done in the following way: Each line of the truth table that gives an output of "" corresponds to a product term. On that line, wherever an input has a value of "", one inserts that input into the product term. Wherever an input has a value of "", one inserts its complement. Wherever an "" appears, meaning that the value of that input does not matter, one ignores that input. As an example, suppose one needs to multiplex inputs C and D onto output Y (Fig. ) according to the following rules: When inputs A and B are both, Y = D When A and B are both, Y = C When A = and B =, Y = When A = and B =, Y = The truth table that satisfies these rules follows. Next to each line with an output of is the corresponding term of the sum-of-products equation: A ] B nputs C D Output Y Product term A*B*D A*B A*B*C The sum-of-products equation is: Y = A*B*'D + A*B + A*B*C. Fig. 3 shows the PLD programmed to implement this equation. A real PLD is considerably more complicated, but it contains an array of AND and OR gates like the one just described. The real chip will have multiple ouputs, each one fed from an AND-OR array. It will probably have more inputs. The output of any AND-OR array may go directly to an output pin of the PLD, or it may be fed back into the chip as another input, or it may be fed to the "D" input of a flip-flop, or it may go to any ft ft r^ iv A-B-D A- B Y ABC O o- Y «A-B-D fa-b + ABC Fig. 3 A simple PLD, programmed for Y = A*B*C by the sum-ofproducts method. The lines of the truth table which end in "" are superimposed on the fuse map.

4 combination of these locations, depending upon the particular PLD used. Because of the simple, logical way in which a circuit can be constructed on a PLD, and because the chips can be re-programmed, erasable PLDs have tremendous potential for reducing the design time for logic circuits and for teaching the digital design process to students. EQUIPMENT AND PROCEDURE Electrically erasable PLDs (EEPLDs) were used as teaching aids in a senior/graduate level course on instrumentation. The course was taught in the fall of 986 and the fall of 987. The two classes included five graduate students, twelve seniors in Agricultural Engineering, and two seniors in Mechanical Engineering. The students first received lectures on digital logic and performed a lab experiment which introduced them to TTL chips. Next they covered the techniques of developing a sum of products equation from a truth table and implementing it as a circuit. The students were then given a laboratory assignment to design a digital circuit, once using TTL chips and once using a PLD. The students built their circuits in the lab, verified that they worked, and documented their circuits in a report. They were asked to give their reactions to the lab and to the PLD in their report. The assignment took two lab periods of 2 h each, not including preparation time. The assigned circuit was a demultiplexer which routed a digital input signal to one of four different output lines. Each output line ended at a light-emitting diode (LED) connected to +5 V through a Q resistor. The LED's were connected to 5 V rather than ground because the TTL-compatible PLD outputs could carry more current to ground than to +5 V. When the input was grounded, the LED on the selected output line lit up. All others remained dark. When the input was at 5 V, none of the LEDs lit up. A two bit binary counter selected the output line, so the active output line changed on each rising edge of a clock input. If the circuit was constructed properly, the LEDs flashed in the sequence with the input grounded and the clock running. Fig. 4 shows a block diagram of the circuit and compares the parts needed for the TTL and PLD versions. The materials cost of the lab was low. The TTL chips cost about $ each and the PLDs cost $6.7 each. The PLD programmer cost $479, but only one programmer was needed for the entire class. The students and the lab instructor needed access to IBM-compatible* personal computers, but these were already available in the department. The clock signals were supplied by function generators, but square wave oscillators made in the lab could have been used instead. Description of the PLDs The PLDs used in the class were GAL6V8s made by Lattice Semiconductor of Beaverton, OR. These were Trade names are used in this publication solely for the purpose of providing specific information. Mention of a trade name, proprietary product, or specific equipment does not constitute a guarantee or warranty by the University of Illinois or the U.S. Department of Agriculture and does not imply the approval of the named product to the exclusion of other products that may be suitable. LED'S H-5v TTL PARTS LIST 2 -BIT COUNTER THE CIRCUIT DESIGN PROJECT ASSIGNED TO THE CLASS 74LS74 (DUAL FLIP-FLOP) 2 74LS2 (QUAD OR GATES) I 74LS86 (QUAD OR GATE) 4 RESISTORS 4 LED'S PLD PARTS LIST I PLD 4 RESISTORS 4 LED'S 2 OUTPUTS ON THE PLD WERE LEFT V UNUSED. Fig. 4 Diagram and parts lists for the circuit design project assi to the class. 2-pin integrated circuits which could be configured to bahave like any of the popular 2-pin PLDs on the market. Eight of the pins were inputs, and eight were outputs which could be individually placed in a high impedance state and used as inputs. The outputs of the AND/OR networks were routed to the "D" inputs of eight flip-flops, and the outputs of the flip-flops were connected to the eight output pins. The other pins were a clock input, an output enable, VCC (+5 V) and ground. Fig. 5 shows the internal logic of the AND/OR array. The device labeled "OLMC" (for Output Logic Macro Cell) in Fig. 5 included the OR gate, the flip-flop, and some programmable logic switches. The OLMC merits further discussion. However, it was not necessary to understand its internal workings completely to use the chip, as the software supplied with the programmer automatically set the switches. Logic Diagram of the Output Logic Macrocell Fig. 6 shows a logic diagram of the Output Logic Macro Cell for the nth output pin. Each OLMC had a polarity bit called OR(n) which determined whether the output was inverted (OR(n)=) or not (OR(n)=l) between the output of the OR gate and the output pin. Each OLMC also had an "architecture control bit" called ACl(n). In addition, there was a global architecture control bit called ACO which affected all of the OLMCs and a control bit called SYN which replaced ACO for the two OLMCs at the ends of the chip (pins 2 and 9). SYN is not shown in Fig. 6, as it did not affect most of the OLMCs. All of these bits were programmed along with the chip. The software supplied with the PLD programmer automatically set the architecture control bits to their correct values; there was no need to set them explicitly, although it was possible to do so if the need ever arose. The effect of the architecture control bits was 82 APPLIED ENGINEERING in AGRICULTURE

5 Clock (Pin I! I ACO To Adjacent Stage ACQ Afcl(n) From Adjacent Stage Fig. 6 The Ouput Logic Macro Cell. L -<- Fig. 5 GAL6V8 AND/OR array logic diagram (from Lattice Semiconductor, 986). to throw the switches in Fig. 6 in the manner shown: up for, down for. If ACO was set to and SYN set to, then each output pin could be selected individually to be a flip-flop output with feedback to the AND/OR array (ACl(n)=) or a bidirectional I/O pin (ACl(n)=l). Pin was the common clock, and pin was the common output enable for the flip-flops. On each bidirectional I/O pin, one of the eight product terms feeding the OR gate was diverted to be the output enable. In contrast, if ACO was set to and SYN to, all of the flip-flops were bypassed. In this condition, if ACl(n) was set to, pin n became a dedicated output (not tri-state). If ACl(n) was set to, pin n became a dedicated input, routing its input through the feedback buffer of an adjacent stage. Because of the construction of the chip, pins 5 and 6 could not be made into inputs. However, pins and (the flip-flop clock and output enable) automatically became inputs. In only one case was SYN permitted to be set equal to ACO: when ACO=l and all the outputs were selected to be bidirectional I/O pins. In this case, setting SYN= disabled the input function at pins 2 and 9 and converted pins and to inputs. The PLD Programmer The PLD programmer used was the Logic Lab, made specifically for the Lattice chips by Programmable Logic Technologies of Longmont, CO. It was connected to the serial port of an IBM PC/AT and programmed one PLD at a time, automatically erasing the PLD before programming it. Included with the PLD programmer was the software needed to operate it. The circuit to be programmed onto the chip was defined by a source file written on the IBM by any DOScompatible editor. EDLIN (supplied with PC-DOS) worked, but a full-screen editor was much easier to use. The source file followed a specific format: the first line specified the type of PLD being used, and the next three lines formed a title block. Next came a list of names for the 2 pins of the chip, which included GND for the chip ground and VCC for the positive power supply. After the pin list, the circuit itself was specified by a set of equations, of the three forms:. Output : = (Sum-of-Products expression of pin names) 2. Output = (Sum-of-Products expression of pin names) 3. Output.OE= (AND expression of pin names) Form () indicates that the output is taken from a flipflop, and that the output will become equal to the expression on the rising edge of the clock. The expression is limited to eight product terms. The output is enabled by the common "Output Enable" pin. For example, if the outputs of the counter in the lab assignment are Ql (most significant bit) and QO, the counter can be specified by: QO:= /QO Ql := Ql*/QO + /Ql*QO Form (2) indicates that the output is taken directly from the AND-OR array, bypassing the flip-flop. The expression is limited to seven product terms, as one term is used to enable the output by an expression of form (3). For example, if IP is the input of the demultiplexer in the lab assignment, the outputs OPO OP3 can be specified by: OPO = IP + Ql + QO OP = IP + Ql + /QO OP2 = IP + /Ql + QO OP3 = IP + /Ql + /QO Form (3) specifies when an output fed directly from the AND-OR array is to be enabled. The expression is limited to one product term. If this equation is omitted for any of these outputs, that output will be stuck in the high impedance state. An output fed from a flip-flop does not need an equation of form (3), as it is already enabled by a common pin. The demultiplexer outputs in the lab assignment can be enabled at all times by the Vol. 4(2):June,

6 following equations: OPO.OE=VCC OP.OE=VCC OP2.OE^VCC OP3.OE=VCC If all of the output pins are used as dedicated inputs or dedicated combinational outputs (no flip-flops and no tri-stating), then the program will set architecture control bits ACO = and SYN = on the chip. In this case equations of form (2) can have eight product terms, and equations of form (3) are not required (or allowed). The AND function was represented by an asterisk (*), and the OR function was represented by a plus sign ( + ). The output or any of the inputs in an equation could be inverted by placing a slash (/) in front of the pin name. The end of the equation list was identified by the word "DESCRIPTION". Anything written after "DESCRIPTION" was considered a comment and ignored by the program (Programmable Logic Technologies, 986). RESULTS The students decided to build the TTL circuit first, because they felt more comfortable with chips they had already used in a previous lab. After some difficulty, all of the students' circuits worked. When they then tried to program the PLDs, several of the students, misunderstanding the capabilities of the chip, tried to program impossible equations (for instance, trying to enable an output with a sum of two product terms). The software did not detect the errors, and the chips behaved strangely. Again, however, after some difficulty all of the circuits worked. One PLD chip was burned out in the process. The cause of the damage was not known. This lab was the students' first exposure to a tri-state device. Some of the 986 students did not realize that the outputs of the PLD had to be enabled. Some also had difficulty understanding that the output of a flip-flop could be used as an input to determine the next state of the same flip-flop. This concept was necessary for constructing a synchronous counter. In 987 these two concepts were emphasized before the students attempted the lab. The students were also enouraged to try to design the circuit a second way: set all the outputs equal to the input, and use the logic to enable the one selected by the counter. This time the students had no problem enabling the outputs continuously. However, some had problems understanding that the tristate output enables could also function as logic elements. Again, some did not fully understand the concept of using a flip-flop output as an input. Reactions of the Class The consensus of the students was that this lab was very instructive and enjoyable. They liked starting with a problem, taking it through the steps of generating a truth table, a set of logic equations, and a schematic, then finally connecting actual TTL chips into an actual circuit with flashing lights. In the process, they said that anything they did not know at the beginning, they learned quickly. The 987 class felt that more design problems should have been included at the expense of other material. When the students were tested a month after the lab experiment, all of them were able to derive a logic circuit (on paper) from a truth table without difficulty. A problem reported by all of the 986 students was that they did not have a good enough understanding of the PLD, the programming software, or the editor program needed to create the source file. Consequently, when the PLD circuits failed to function properly, the students were unable to locate the problems without help. In 987 the handouts were revised and the class spent more time covering these topics. These measures solved the problem. All of the students realized that the ability to perform complex logic functions on a single chip would greatly reduce the problems they might encounter in wiring a circuit. Most of the students reported being impressed with the potential of the PLDs for creating complex circuits with low chip counts, and one of them suggested that a more complex design problem be assigned with the PLDs. CONCLUSIONS The primary advantage of this lab appears to have been the exercise of letting the students carry out their own design problem according to an orderly technique, rather than the use of the PLD. There were some benefits to including the PLD, however:. The students were exposed to a logic design process different from the one they had become familiar with. They were forced to think in terms of truth tables and Boolean equations rather than circuit schematics. In the process, any concepts that they did not understand became apparent. 2. The students gained some experience in the use of a personal computer as an engineering design tool. 3. The students were given some experience with a device at the cutting edge of technology. More complex erasable PLDs are coming onto the market, and they are finding use in an increasing number of applications (Collett, 987). Any experience the students receive with these devices is likely to benefit them later on in their careers. The lectures prior to the lab and the literature passed out in class in 986 did not adequately prepare the students to use the PLDs. The fact that the students were all able to program working circuits into the PLDs after receiving help hi troubleshooting indicated that the devices were basically easy to use. The lectures and handouts were revised to include more material about the sum-of-products method, the concept of a programmable logic device, and the use of the editor and programmer software. These measures corrected the problem in the fall of 987. References. Collett, R Reports from the PLD front. ESD: the Electronic System Design Magazine (formerly Digital Design) 7(2): * 2. Lattice Semiconductor Corporation Data catalog. 54 N. W. Greenbrier Parkway, Beaverton, OR Programmable Logic Technologies PLD syntax (instructions for Logic Lab PLD programmer). P. O. Box 567, Longmont, CO APPLIED ENGINEERING in AGRICULTURE