Super-Doubler Device for Improved Classic Videogame Console Output

Transcription

1 Super-Doubler Device for Improved Classic Videogame Console Output Initial Project Documentation EEL4914 Dr. Samuel Richie and Dr. Lei Wei September 15, 2015 Group 31 Stephen Williams BSEE Kenneth Richardson BSCpE John Shepherd BSEE Gilson Rodrigues BSEE

2 Project Narrative With the move from analog video signals and CRT television sets to an all-digital world of flat panel LCD, plasma, and other technologies, many older entertainment peripherals yield inadequate results when displayed on these new sets. The reasons for this are numerous. Television manufacturers ultimately make the decision which additional conversion and scaling techniques they would like to implement into the set itself. With the television industry as competitive as ever, the additional cost of considering specific devices and edge cases for a consumer base, overwhelmingly using newer digital devices, could make a large impact on units sold. For many manufacturers, the solution is to provide the bare minimum in analog device support and connector compatibility. Often the only analog connector provided is composite. Even when the connectors themselves are present, the methods used in processing and displaying them are typically applied in a broad and insufficient way. The result is an image which lacks clarity as seen in Figure 1. Figure 1: 240p signal. TV default processing mode (left), XRGB-mini device output (right). This project is focused specifically on providing an intermediary device between classic 8-bit/16-bit videogame consoles and modern television sets similar to Micomsoft s XRGB-mini, but at a lower cost and with a more focused feature set. These videogame systems typically output a 240p (320x240) signal over one of the aforementioned analog connections. Modern televisions often handle such 240p signals poorly, interpreting the signals as 480i (640x480 interlaced) and inappropriately applying de-interlacing techniques to a progressive scan signal. We plan to solve several of these issues with a single device. Our device exists between the videogame console and the modern television. With a 240p analog input, our device will properly scale the signal to 480p through a process known as line-doubling using an FPGA and accompanying filter and conversion circuitry. Line-doubling scales the resolution by a factor of two while requiring very little processing time. While modern televisions often have trouble with

3 240p signals, the majority today handle 480p signals well enough for the average user. Our goal is to bridge this gap between troublesome 240p and well-handled 480p for any television set. If desired, the console stereo audio output may also be provided as input and carried over HDMI to the display for a single, convenient connection point. Figure 2: 240p signal displayed on a CRT television with darkened scanlines (left), emulated scanlines via XRGB-mini. In addition to scaling and converting the image, our device provides darkened scanline emulation. A darkened scanline, in the context of 240p displayed on a CRT television, refers to the darkening of every odd line due to only one of the image fields being transmitted as shown in Figure 2. These darkened scanlines are absent when a 240p signal is displayed on a digital television. This device will allow the user to darken every other picture line, providing a classic visual effect. An on-screen overlay will allow the user to simply and quickly check the device status and operating mode for making desired adjustments. This overlay will be interfaced with via remote control, allowing the user to adjust various image properties in addition to scanline control. On the strict hardware interface side, our device will support a variety of analog video inputs. It will support component-ypbpr video, 15-pin VGA-RGBHV, and SCART-RGBS. For output, the device will support digital output via HDMI. This collection of input connections covers nearly all common connections seen on the videogame consoles targeted for use with this device.

4 Specifications and Requirements Physical Weight < 2lbs Volume < 25 in 3 Complete standalone device in single enclosure Power Total device power usage < 20 watts Input/Output Support Support component-ypbpr, VGA-RGBHV, and SCART-RGBS input Support LR stereo audio input Support HDMI output Display and Technical Processing time < 30ms Full 4:4:4 RGB Processing, (no chroma-subsampling) Resolution Scale Factor >= 2 240p <-> 480i switch time < 2 Frames Time Support overlay for inspecting device status Support for scanline emulation Cost and Miscellaneous Bill of materials for one device < $100 Support for configuration using remote control Support for FPGA reconfiguration via SD card

5 Project Block Diagrams Stereo Audio Stereo Audio ADC Digital Audio Control: I2C Analog Input: NTSC 15Khz (240p) LPF Filtered Video Signal SDTV Video Decoder Digitized Component Video FPGA Encoded Video HDMI Transmitter HDMI Out FPGA/MCU Comm Path VGA DAC VGA Out Power SD Card Reader FPGA Config Bit File MCU Status LEDs Receiver Digitized Component Video Encoded Video Remote Control Control Unit MCU Interface I2C FPGA/MCU Comm Path

6 Table 1: Block diagram key Acronym Expansion Brief Description LPF Low Pass Filter network Filter for cleaning up analog signals before conversion and processing DAC Digital-Analog Converter Signal processor and circuitry for conversion of digital to analog signals ADC Analog-Digital Converter Signal processor and circuitry for conversion of analog to digital signals FPGA Field-Programmable Gate Array Programmable digital logic chip for implementing image processing logic I2C Inter-Integrated Circuit Serial communications protocol NTSC National Television Systems Committee Standards governing analog video signals in North America 240p 320x240 progressive scan video Analog video frame format output by most devices in our target class MCU Microcontroller Microcontroller for external control interfacing

7 Budget Estimate Initial budget estimate for project development. Includes costs of known prototyping and development/early testing tools as well as estimates for final device assembly components. As of now the project is self-funded. Table 2: Initial project budget estimate. Part Name Unit Cost Quantity Total Multi-regulator IC $1 5 $5 LPF Filter IC $4 5 $20 ADC IC $7 5 $35 HDMI TX IC $9 4 $36 FPGA IC $25 2 $50 Miscellaneous IC - Varies $50 Barrel Jacks (RCA, Power, etc) $1 10+ $10 Miscellaneous Jacks (HDMI, VGA, - Varies $20 etc) Miscellaneous Components - Varies $50 FPGA Dev board $50 2 $100 PCB for ADC Dev board $20 1 $20 PCB for system prototype $40 1 $40 Enclosure $10 1 $10 Microcontroller $10 1 $10 Remote/Receiver Components $10 1 $10 SD Card $10 1 $10 Total $476

8 Initial Milestones Table 3: Initial project milestones. Task Duration Start Date End Date Research 7 weeks 9/14/ /31/ Video Protocols/Standards 2 weeks 9/14/2015 9/30/ Communication Standards 2 weeks 9/14/2015 9/30/ Audio Conversion 2 weeks 9/21/ /7/ FPGA 7 weeks 9/14/ /31/ Selection 2 weeks 9/14/2015 9/28/ Logic and Interfacing 6 weeks 9/21/ /31/ MCU 6 weeks 9/21/ /31/ Selection 2 weeks 9/21/ /7/ Logic and Interfacing 4 weeks 10/1/ /31/ Analog/Video Filtering 3 weeks 9/21/ /14/ Analog-Digital Conversion 3 weeks 9/21/ /14/ Overlay Generation 2 weeks 10/7/ /21/ HDMI Transmitter 2 weeks 10/7/ /21/ Power Requirements 2 weeks 10/14/ /31/ PCB Considerations 2 weeks 10/14/ /31/ Enclosure (Late) 2 weeks 2/7/2016 2/21/2016 Design 9 weeks 10/21/ /21/ Filtering 4 weeks 10/21/ /21/ Analog-Digital Conversion (AV) 4 weeks 10/21/ /21/ Frame Manip. Logic (FPGA) 9 weeks 10/21/ /21/ Control Logic (FPGA) 9 weeks 10/21/ /21/ MCU Logic 9 weeks 10/21/ /21/ Overlay Generation 3 weeks 11/7/ /28/ Combined PCB 5 weeks 10/21/ /28/ Power System 3 weeks 10/28/ /21/ HDMI/Output Stage 4 weeks 10/28/ /28/ Enclosure (Late) 2 weeks 2/14/2016 2/28/2016 Prototype 5 weeks 2/7/2016 3/14/ ADC Breakout (Early) 3 weeks 9/21/ /14/ Output Stage Breakout (Early) 3 weeks 9/21/ /14/ Combined PCB 3 weeks 2/7/2016 2/28/ Component Mounting 2 weeks 2/28/2016 3/14/ Enclosure 1 weeks 3/7/2016 3/14/2016 Testing 7 weeks 3/14/2016 5/4/ ADC Breakout (Early) 4 weeks 10/14/ /14/ Output Stage Breakout (Early) 4 weeks 10/14/ /14/ Finished Prototype 7 weeks 3/14/2016 5/4/2016

9 Documentation 34 weeks 9/8/2015 5/4/ Initial Proposal 1 weeks 9/8/2015 9/15/ SD1 Document 8 weeks 10/21/ /15/ Conference Paper 5 weeks 3/7/2016 4/14/2016