Design of Efficient Programmable Test-per-Scan Logic BIST Modules

Transcription

1 Design of Efficient Programmable Test-per-Scan Logic BIST Modules Devika K N 1 and Ramesh Bhakthavatchalu 2 Electronics and Communication Engineering Amrita School of Engineering, Amritapuri Amrita Vishwa Vidyapeetham, Kerala Amrita University, India devikanandalal@gmail.com 1, rameshb@am.amrita.edu 2 Abstract This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology day by day have made chip testing more complicated. This has paved way for the increased popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows self testing of chips with the help of an additional built-in hardware structure inside the circuit. Test-per-scan Logic BIST structure includes Test pattern generator, Response Analyzer, ROM, and Comparator. LFSR does the role of test pattern generator in Logic BIST since it is more efficient than binary counters. MISR is commonly used as an output response analyzer which acts as an alternative to n-parallel LFSRs. Comparator compares the responses stored in ROM and MISR output. Reconfigurability is added to every structural element in BIST to improve the fault coverage of IC testing. The proposed structural architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 48) programmable structures in Logic BIST were synthesized in Xilinx Spartan 3E and Spartan 6 for implementing them on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete form were implemented for PRPG and MISR design. All the designs were synthesized in ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable PRPG and MISR designs were analyzed for speed, power and area with the equivalent modules generated by third party sign-off tool. Keywords FPGA, PRPG, MISR, Reconfigurability, primitive polynomial, ASIC, SOC. I. INTRODUCTION This modern era of VLSI technology has witnessed a tremendous increase in the design complexity as well as higher density in System-on-chip (SOC) designs shooting at a faster rate. The Integrated circuits manufactured for critical applications are diagnosed with latent faults which may not be evident at the time of manufacturing testing but appears fatal in the later life span of the chip due to environmental variation. To ensure safety and durability, infield testing should be implemented within SOC s for detecting stuck at faults and bridging faults arising due to manufacturing defects. This lead to an innovative methodology called Logic BIST where circuit can be tested at-speed using built-in circuitry. Rapid testing and reduction in costs are the attractive features of Logic BIST structures compared to ATPG based testing [1]. While the former uses a random number generator to generate test patterns, the latter uses Automatic Test Equipment to provide stored deterministic patterns to the circuit under test. Since the patterns are generated at real time of circuit testing, it significantly reduces the memory usage adding to its features at the expense of small area overhead. Pseudo Random Pattern Generator (PRPG) and Multiple Input Shift Register (MISR) forms the critical components in Logic BIST. Pseudo Random Pattern Generator is implemented using an LFSR which generates random test patterns [2], [3]. Same LFSR structure is modified to work as MISR. Many research works have been done and is still under progress for implementing high performance LBIST circuits. One of the work utilizes a new adaptive low shift power random test pattern generator (ALP-RTPG) for generating test patterns in LBIST to reduce the power consumed [4]. But it results in significant test coverage loss with increase in the number of primary inputs. Another approach incorporates reconfigurable interconnects so as to reduce the correlation between test patterns [5]. It allows the requirement of fewer control bits compared to other BIST methods but can cause bus contention inside scan chains for those test vectors that is not desired. Paper [6] makes use of ATPG to provide deterministic patterns to deterministic BIST. But it converts failure diagnosis to a complex process. In this paper an n-bit reconfigurable LBIST structure that would be able to test any circuit has been designed and implemented. The proposed approach makes the design flexible by adding reconfigurability to each components of LBIST. It is simulated and synthesized using verilog on the Xilinx Spartan 3E for implementation in FPGA and in Encounter RTL compiler for implementation in ASIC [7]. The structures are designed and compared to verify its performance, area overhead and to maximize efficiency. The structure of the paper proceeds as follows: Section II describes the typical architecture of Logic BIST and its structural components. Section III discusses how programmable LBIST is implemented. Section IV shows the simulation and synthesis results of LBIST components in Xilinx and RTL compiler. Section V concludes the paper and discusses the future scope in this field. II. TYPICAL LOGIC BIST ARCHITECTURE Logic BIST is an extra testing circuitry embedded in the chip that perform structural based test after manufacturing /17/$ IEEE

2 Fig. 2. N-bit Modular LFSR architecture Fig. 1. Typical Logic BIST architecture Logic BIST design includes on-chip/board circuitry to provide test patterns and to analyze output responses. Fig. 1. shows the typical Logic BIST architecture. Test pattern Generator, Multiple Input Signature Register, Comparator, ROM, and BIST controller forms the basic elements of the structure. This circuitry tests the chip infield thus avoiding the need for an ATE. It ensures high fault coverage with minimum vectors at the expense of 15% area overhead of the chip. In Logic BIST architecture PRPG plays the role of test pattern generator and MISR does the output response analysis. BIST components are detailed below: A. Pseudo Random Pattern Generator PRPG generates the required test vectors which are fed into the circuit to be tested. LFSR is the basic structure that generates pseudo random patterns based on the feedback polynomial provided [8],[9],[10],[11]. It is a kind of shift register where selected bits called taps are XORed to construct the feedback polynomial which is fed to LSB flip-flop of LFSR. Characteristic polynomial of degree n over GF (2) defines the internal structure of an n-bit LFSR where coefficients denote the existence of feedback path [12], [13]. Only primitive polynomials are considered as candidates for feedback loop in LBIST applications since they generate maximum length sequences. Such polynomials can be determined by checking whether the latter could completely divide x t + 1, where t = 2 n 1. Basic theory behind LFSR is Galois field. Every arithmetic operation in LFSR is based on modulo 2 where multiplication is equivalent to AND operation and addition is considered as XOR operation. PRPG can be implemented in four different forms: Standard, Modular, Complete and Hybrid. Fig. 2. shows N-bit Modular PRPG architecture. This configuration is better among all the four in terms of speed of execution, area, and power consumption. While standard form has higher critical path with increasing number of taps in the feedback polynomial. Complete PRPG demands more area due to additional gates used in circuit for generating 2 n patterns. Hybrid PRPG could be used only if the feedback polynomial satisfies a particular condition thus limiting its usage but has comparable features as that of standard form. Fig. 3. N-bit Modular MISR architecture B. Multiple Input Signature Register Multiple Input Signature Register is a modified form of LFSR that compresses long output sequence of bits from CUT into compressed data stream. It reduces the area overhead by acting as an alternative to multiple LFSR in parallel which is determined by the primary outputs of CUT. MISR compresses all outputs into a single LFSR and the resulting output value is known as signature [14]. It can be constructed from a LFSR structure since LFSR has linear properties and conforms to superposition principles. Signature is thus obtained as a result of performing modulo operation of each primary output with feedback polynomial and then XOR sum of the resultant. MISR produces compressed output that is compared with the expected outputs (Golden signature) using a comparator to check for faulty or fault-free circuit [15],[16]. Fig. 3. shows N-bit modular MISR architecture. C. Comparator Comparator performs data comparison where inputs are in the form of binary numbers. It checks whether a given number is equal, greater or less than the other one in terms of magnitude. In this context comparator does the comparison between golden signature stored in ROM and the resultant signature obtained from MISR and checks whether they are equal. The equality between the values indicates a fault-free circuit. If the values are not the same, it confirms that the circuit is faulty. Golden signature is the output from same identical circuit as that under test when it is in a fault-free condition. It is obtained through simulations under similar operations. D. Read Only Memory(ROM) Read only Memory (ROM) is a storage element that can retain data even when the power is off. In Logic BIST, stores Golden signature values of fault-free circuit. These values are pre-calculated through simulations. No amount of memory is used by this self-testing circuitry for storing test vectors thus saving large memory space.

3 E. Circuit Under Test Circuit Under Test could be combinational or sequential circuits. ISCAS-89 and ISCAS-99 circuits can be considered as the circuit to be tested to verify the working of Logic BIST architecture. These designs are the benchmark circuits which are designed using gate level modeling. The number of primary inputs and outputs of the circuit to be tested determines the size of PRPG and MISR to be used in LBIST structure. to replace third party generated equivalent structures to study the performance characteristics. This paper presents an idea of designing every basic component in a Logic BIST reconfigurable to accept any number of inputs of any bit size. Modular form of PRPG and MISR is efficient in terms of performance and speed compared with other configurations like standard, Complete and Hybrid. The proposed reconfigurable designs were found to be efficient in terms of speed, area, and power on comparison with equivalent third party tool generated modules as shown in table VII. IV. SIMULATION AND SYNTHESIS RESULTS Different components of Logic BIST structure is designed in verilog HDL, simulated in Modelsim 6.5 RTL simulator and Xilinx ISE is the software tool used for FPGA synthesis. Encounter RTL compiler is the EDA tool used for the synthesis of the design in ASIC. Fig. 4. Fig. 5. N-bit Modular LFSR architecture N-bit Modular MISR architecture III. PROPOSED ARCHITECTURE OF LOGIC BIST This paper focuses on the design of a Programmable Logic BIST structure. Every element inside the structure is made reconfigurable so that any circuit with different inputs could be tested by the same built-in testing circuitry. Reconfigurable PRPG is designed by adding multiplexers into the basic design of LFSR having XOR gates and flipflops as the core components. Feedback polynomial decides the position of XOR gates in LFSR. Multiplexers enable the designer to feed any initial value called seed with the help of select signal called load. In the other case pseudo random patterns starting from the initial value are generated through shift operation. The size of PRPG can also be varied to meet the circuit features adding to its flexibility. Fig. 4. Shows the proposed architecture for reconfigurable PRPG. MISR can also be made programmable by modifying the LFSR structure by adding XOR gates at the input of every flip-flop depending on the primary outputs of CUT. Fig. 5. shows the proposed architecture for MISR. The signature value obtained is provided as one of the input to a reconfigurable comparator whose other input is the golden signature stored in programmable ROM. Comparator is designed to accept any bit size input, provided the two inputs are of the same number of bits. ROM is also made programmable to store required number of signature values based on the number of signature a fault-free version of the circuit under test could actually produce. PRPG and MISR modules thus designed were used A. Synthesis result in Xilinx ISE tool Synthesis of 48 bit PRPG and MISR in its various configurations were done are their results were analyzed in both Spartan 6 and spartan 3E FPGA. Analysis shows that modular form of PRPG and MISR have maximum operational frequency compared to standard, complete or hybrid structure for any bit configuration. ASIC synthesis of 16bit PRPG is shown in fig. 6. Fig. 7. and fig. 8. displays FPGA synthesis of 48 bit modular PRPG and programmable 16 bit ROM respectively. Table I. and Table II. highlights the parametric analysis results of 48 bit PRPG and MISR in Spartan 6 and Spartan3E respectively. Complete PRPG/MISR has least speed of execution due to more number of gates involved in its critical path. Hybrid form has comparable properties to that of Standard one. Comparator and ROM were designed for 16 and 32 bit. B. Synthesis results in RTL compiler ASIC synthesis of every design also proved that modular structure had maximum speed of execution of about 1.37 GHz and less switching power. Standard PRPG/MISR had less speed and greater area overhead compared to hybrid form. Complete structure due to more number of gates used for its implementation showed up highest area overhead. Hybrid form utilized lesser number of XOR gates owing to its structural property and thus had efficient gate utilization. Table III. and table IV. shows the synthesis results of 48 bit PRPG and MISR in RTL compiler respectively. Fig. 9. displays the synthesis results of 16 bit comparator in RTL compiler while fig. 10. shows the synthesis of 48 bit modular MISR in Spartan 3E FPGA. TABLE I. PARAMETER ANALYSIS FOR 48 BIT PRPG IN XILINX FPGA Parameters Spartan-3E Spartan-6 S M C H S M C H FF s LUTs Slices/LUT-FF Bonded IOBs GCLK/BUFGs Speed(GHz)

4 TABLE II. PARAMETER ANALYSIS FOR 48 BIT MISR IN XILINX FPGA Parameters Spartan-3E Spartan-6 S M C H S M C H FF LUTs Slices/LUT-FF Bonded IOBs BUFG/GCLKs Speed(GHz) S-Standard, M-Modular, C-Complete, H-Hybrid TABLE III. SYNTHESIS RESULTS OF 48 BIT PRPG IN RTL COMPILER Type of LFSR Size Area(nm 2 ) Mapped gates Power(nW) Speed(GHz) Standard Modular Complete Hybrid Fig. 8. FPGA Synthesis design of 16bit ROM TABLE IV. SYNTHESIS RESULTS OF 48 BIT MISR IN RTL COMPILER Type of LFSR Size Area(nm 2 ) Mapped gates Power(nW) Speed(GHz) Standard Modular Complete Hybrid Fig. 6. Schematic diagram of 16bit Modular PRPG in ASIC Synthesis Fig. 9. ASIC Synthesis design of 16bit Comparator Fig. 7. Technology Schematic of 48bit Modular PRPG in FPGA Fig. 10. Technology Schematic of 48bit Modular MISR in FPGA Logic BIST synthesis were done for the entire set of ISCAS-89 benchmark circuits for comparison of results and performance analysis. Table V explains the LBIST synthesis details while table VI highlights about the test and scan information s for these 27 circuits. V. CONCLUSION AND FUTURE SCOPE This paper presents a reconfigurable Logic BIST architecture where every component was designed to be programmable.

5 TABLE V. LOGIC BIST SYNTHESIS DETAILS OF DIFFERENT ISCAS-89 DESIGNS ISCAS PI PO Flip No of Scan Total Tested Test Design Flops scan chain Faults Faults coverage chains length S S S S S S S S S S S S S S S S S S S S S S S S S S S TABLE VI. TEST AND SCAN DETAILS IN LBIST FOR DIFFERENT ISCAS-89 DESIGNS ISCAS Test Scan Test Test Design Cycles Cycles Sequences coverage S S S S S S S S S S S S S S S S S S S S S S S S S S S This design thus ensures self-testing of any kind of circuitry with varying configurations. PRPG and MISR structures were made reconfigurable by adding multiplexers into its designs and providing flexibility in the position of tap insertions which determines the feedback polynomials and the patterns generated. For MISR, XOR gates were added to every flipflop inputs depending on the number of primary outputs of the CUT. Comparator and ROM were also designed to compare and store any number of inputs with varying size. TABLE VII. COMPARISON OF PERFORMANCE PARAMETERS BETWEEN THIRD PARTY GENERATED AND RECONFIGURABLE LOGIC BIST MODULES Design Area(nm 2 ) Power(nW) Speed(GHz) Original New Original New Original New Netlist Netlist Netlist Netlist Netlist Netlist s s s s s s s s s s s s s s s s s s s s s s s s s s s The analysis of this work shows that modular structure is efficient in terms of speed of execution and in gate utilization compared to other forms of Reconfigurable PRPG or MISR. The proposed PRPG and MISR design modules displayed better performance in terms of speed, area and power on comparison with the same structures generated by a third party tool. As future scope, ROM and Comparator modules of Logic BIST structure can also be reconfigured and replaced to analyze the performance variations in analogy with tool generated design equivalent. REFERENCES [1] Nagaraj s vannal, saroja v siddamal, shruti v bidaralli, mahalaxmi s bhille, Design and testing of combinational Logic circuits using built in self Test scheme for fpgas, 2015 fifth international conference on communication systems and network technologies, [2] Ramesh Bhakthavatchalu and M. Nirmala Devi, Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture, International Journal of Engineering and Technology, vol. 7, no. 3, pp , [3] Ramesh Bhakthavatchalu, Deepthy G R, Sreenivasa Mallia S, HariKrishnan R, ArunKrishnan, Sruthi.B, 32-bit Reconfigurable Logic-BIST Design Using Verilog for ASIC Chips, Recent Advances in Intelligent Computational Systems (RAICS), pp , [4] Xijiang Lin and Janusz Rajski, Adaptive Low Shift Power Test Pattern Generator for Logic BIST, 19th IEEE Asian Test Symposium, [5] Lei Li and Krishnendu Chakrabarty, Test Set Embedding for Deterministic BIST Using a Reconfigurable Interconnection Network, IEEE Transactions on computer-aided design of Integrated Circuits and Systems, vol. 23, no. 9, pp , [6] Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew, Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST, 23rd IEEE VLSI Test Symposium (VTS 05), 2005.

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