CPE 628 Chapter 5 Logic Built-In Self-Test. Dr. Rhonda Kay Gaede UAH. UAH Chapter Introduction

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1 Chapter 5 Logic Built-In Self-Test Dr. Rhonda Kay Gaede UAH Introduction Introduce the basic concepts of BIST BIST Rules Test pattern generation and output techniques Fault Coverage Various BIST diagrams A Design Practice Page 2 1

2 4.1 Introduction Logic BIST Techniques Why do we need built-in self-test (BIST)? For applications Detect faults Provide diagnosis BIST Concurrent online BIST Non Concurrent online BIST BIST Functional offline BIST Structural offline BIST Page Introduction Typical ATPG System Test Pattern Generator (TPG) Logic BIST Controller Circuit Under Test (CUT) Output Response Analyzer (ORA) Structural off-line BIST Page 4 2

3 5.2 BIST Design Rules Logic BIST requires much more design restrictions when compared to conventional scan. Therefore, when designing a logic BIST system, it is essential that the circuit under test meet all rules and design rules, called design rules. One of the biggest problems is values. Depending on the nature of each, several methods can be appropriate for use. Common problems: (1). (2). Page BIST Design Rules Typical Unknown Sources Adding bypass logic. Adding control-only scan point Bypass logic Initialization Scan points Page 6 3

4 5.2 BIST Design Rules Unknown Source Blocking Page BIST Design Rules Asynchronous Set/Reset Signals Asynchronous Set/Reset Signals using the existing scan enable (SE) signal to protect each shift operation and adding a set/reset clock point (SRCK) on each set/reset signal to test the set/reset circuitry. SRCK SE Set/Reset Circuitry Functional Logic 0 1 R D Q Scan-In CK Shift Window Capture Window Shift Window Capture Window Shift Window CK C1 C2 SRCK SE Page 8 4

5 5.2 BIST Design Rules Tri-State Buses Tri-State Buses Re-synthesize each bus with. decoder A for testing a tri-state bus with 2 drivers Page BIST Design Rules Paths 0-control point 1-control point Paths Adding an extra to a selected combinational gate on the path Page 10 5

6 5.2 BIST Design Rules I/O Ports Fix the of each bi-directional I/O port to either input or output mode. EN SE BIST_mode D Z IO Forcing a bi-directional port to mode Page BIST Design Rules and caused by clock may occur between the TPG and the (scan chain) inputs of the CUT as well as between the (scan chain) outputs of the CUT and the ORA. To avoid these potential problems and ease physical implementation, we recommend adding logic between the TPG and the CUT and between the CUT and the ORA. T P G D CK Q D CK Q CUT D CK Q D CK Q O R A CK1 CK2 CK3 logic among the TPG, CUT, and ORA Page 12 6

7 5.3 Test Pattern Generation Test pattern generators (TPGs) constructed from shift registers (LFSRs) TPG testing ( set of tests) Pseudo- testing ( of tests plus simulation) Pseudo- testing ( set of tests for of each output) Page Test Pattern Generation Standard LFSR(External XOR) Consists of n and a number of exclusive-or (XOR) gates h n-1 h n-2 h 2 h 1 S i0 S i1 S in-2 S in-1 Page 14 7

8 5.3 Test Pattern Generation Standard LFSR(Internal XOR) Each XOR gate placed between two D flip-flops At most, one of delay h 1 h 2 hn-2 hn-1 Si0 Si1 Sin-2 Sin-1 Page Test Pattern Generation Standard LFSR(Characteristic Polynomial) The internal of the n-stage LFSR can be described by a polynomial of degree n, f(x) = 1 + h 1 x + h 2 x h n-1 x n-1 + x n, where h represents a in the circuit. Let S i represent the of the n-stage LFSR after i of the contents,s 0,of the LFSR, and S i (x) be the polynomial representation of S i S i (x) = S i0 + S i1 x + S i2 x S in-2 x n-2 + S in-1 x n-1 If T is the integer such that f(x) divides 1 + x T,then the integer T is called the of the LFSR. If T = 2 n 1, then the n-stage LFSR generates a -length sequence. Page 16 8

5.3 Test Pattern Generation Standard LFSR(Maximal Length LFSR) a.f(x) = 1 + x 2 + x 4 b.f(x) = 1 + x + x 4 S 0 = x 3 Page 17 5.

9 5.3 Test Pattern Generation Standard LFSR(Maximal Length LFSR) a.f(x) = 1 + x 2 + x 4 b.f(x) = 1 + x + x 4 S 0 = x 3 Page Test Pattern Generation Standard LFSR(Primitive Polynomials) A maximal length LFSR is constructed using polynomials. A polynomial is a polynomial that divides but not, for any integer i < T, where T = 2 n -1. Maximal length LFSRs leave out one pattern,. Page 18 9

10 5.3 Test Pattern Generation Standard LFSRs(Complete LFSRs) (a) 4-stage standard CFSR (b) 4-stage modular CFSR (c) A minimized version of (a) (d) A minimized version of (b) Page Test Pattern Generation Pseudo-Random Testing Exhaustive Testing works well for. Pseudo-Random generates a subset using a maximum-length LFSR. Each maximum-length LFSR produces a sequence with probability of generating at every output. For faults, you can use logic to the patterns X 1 X 2 X 3 X 4 Page 20 10

11 5.3 Test Pattern Generation Pseudo-Random Testing (Cellular Automata) Provide test patterns Provide coverage in a random-pattern resistant (RP-resistant) circuit Implementation advantage General structure of an n-stage cellular automata Rule 90: x i (t+1) = x i-1 (t) + x i+1 (t) Rule 150: x i (t+1) = x i-1 (t) + x i (t) + x i+1 (t) 0 Cell 0 Cell 1 Cell n-2 Cell n-1 0 Page Test Pattern Generation Pseudo- Random Testing (Cellular Automata Example) 0 X 0 X 1 X 2 X Page 22 11

12 5.3 Test Pattern Generation Pseudo-Exhaustive Testing Reduce while retaining many advantages of testing Guarantee 100% single-stuck fault coverage test technique test technique Page Test Pattern Generation Pseudo-Exhaustive Testing (Verification Testing) the CUT into m cones, from each output to determine the inputs that drive the output. Each cone will receive test patterns and are tested. Pseudo-exhaustive pattern generation techniques Page 24 12

13 5.3 Test Pattern Generation Syndrome Driver Counter Use SDC to generate test patterns. Check whether some inputs can the same test signal. If n-p Inputs can share test inputs with other p inputs, then the circuit can be tested exhaustively with these p inputs. In this case, and can share a test signal. x 1 x 2 x 3 x An (n, w)=(4, 2) CUT X 1 X 2 X 3 y 1 y 2 y 3 y 4 X 4 Page Test Pattern Generation Constant-Weight Counter Use CWCs to generate test patterns. Constant-Weight counters are constructed using constant-weight code or code. The constant-weight test set is a -length test set for many circuits. X 1 X 2 X X 4 Page 26 13

14 5.3 Test Pattern Generation Combined LFSR/SR Use a combination of an LFSR and a shift register (SR) for pattern generation. The method is most effective when is much less than. In general, this technique requires tests than other schemes when is greater than. However, it usually requires at least seeds. This sequence can test the (4,2) circuit because the patterns occur on all of outputs. X 1 X 2 X 3 X Page Test Pattern Generation Combined LFSR/Phase Shifter A combined LFSR/PS approach using a combination of an LFSR and a linear phase shifter which includes a of gates to generate test pattern. Similar to combined LFSR/SR, this technique requires more tests than other schemes when w is greater than n/2. Again, any two outputs contain all four combinations. The number of seeds required is two. X 1 X 2 X 3 X 1 X 2 X 4 X Page 28 14

15 5.3 Test Pattern Generation Condensed LFSR Condensed LFSRs are constructed based on codes. Define g(x) and p(x) as the polynomial and polynomial over GF(2), respectively. An (n, k) condensed LFSR can be realized using where f(x) = g(x)p(x) = (1 + x + x x n-k )p(x) w < k/(n k _ 1) + k/(n k + 1) (4,3) with S 0 (x) = g(x) = 1 + x for testing (n,w) = (4, 2) CUT X 1 X 2 X 3 X 4 Page Test Pattern Generation Cyclic LFSR Use cyclic LFSRs to reduce the test length when. A cyclic code always exists when n =, To exhaustively test any (n,w) CUT -find a generator polynomial g(x) of degree (or degree ), for generating an (n,k ) = (n,n -k) cyclic code, that divides and has a design distance ; construct an (n,k) cyclic LFSR using f(x) = h(x)p(x) = (1+x n )p(x)/g(x), where h(x) = (1+x n )/g(x); -shorten this (n,k) cyclic LFSR to an (n,k) cyclic LFSR by deleting the,, or n -n stages from the (n,k) cyclic LFSR. To test a CUT, no cyclic code for 8, use n = and k = Page 30 15

16 5.3 Test Pattern Generation Cyclic LFSR (Example) To test a CUT, no cyclic code for 8, use n = and k = A (8,5) cyclic LFSR, picking the first stages and the last stages of the (15,5) cyclic LFSR, has a period of Page Test Pattern Generation Compatible LFSR The combined LFSR of an l-stage LFSR and an l-to-n logic, called l-stage compatible LFSR, can further the test length, when only stuck faults are considered. X 1 X 2 Y X 3 X 4 X 5 Y 2 X 1 X 2 X 3 X 4 X 5 (a) An (n,w) = (5,4) CUT (b) A 2-stage compatible LFSR Page 32 16

17 5.3 Test Pattern Generation Segmentation Testing Used when Test using previous techniques is too or Output depends on inputs. Divide the circuit into segments partitioning partitioning Page Test Pattern Generation Delay Fault Testing Need patterns to test delay fault exhaustively Test set could cause test when more than input changes. Use maximal LFSR plus counter to generate 2n(2 n 1) patterns TESTTYPE h n-1 h n-2 h 2 h X 1 X 2 X n-1 X n Page 34 17

18 5.4 Output Response Analysis Output responses are into a signature is different from, is lossy. Compaction techniques testing testing Page Output Response Analysis Ones Count Testing Assume the CUT has output and the output contains a stream of L bits. Let the fault-free output response be {r 0, r 1, r 2,,r L-1 } Ones count testing will need a counter to count in the bit stream. The probability P OC (m) = (C(L,m)-1)/(2 L 1) where m is the number of and C(L, m) is the combination of taken at a time and L is the of the sequence. T CUT Counter Signature CLK Page 36 18

19 5.4 Output Response Analysis - Transition Count Testing Transition count testing is similar to that for ones count testing, except the is defined as the number of 1-to-0 and 0-to-1. The aliasing probabilty is P TC (m) = (2C(L-1,m)-1)/(2 L -1) where m is the fault-free number of and C(L-1, m) is the combination of L-1 taken m at a time and L is the length of the sequence. T CUT D Q ri-1 r i Counter Signature CLK Page Output Response Analysis Signature Analysis Signature analysis is the compaction technique used today, based on checking. Two signature analysis schemes signature analysis ( ) signature analysis ( ) Page 38 19

20 5.4 Output Response Analysis Signature Analysis (Serial Example) M Page Output Response Analysis Signature Analysis (Serial) An n-stage single-input signature register h 1 h 2 h n-2 h n-1 M r 0 r 1 r n-2 r n-1 Define L-bit output sequence M Aliasing Probability M ( x) = m 0 + m1 x + m2x m L x L 1 1 Let the polynomial of the modular LFSR be f(x) IF M(x) = q(x) f(x) + r(x) Signature is the polynomial remainder, r(x) Page 40 20

21 5.4 Output Response Analysis Signature Analysis (Parallel) Multiple-input signature register ( ) h 1 h 2 h n-2 h n-1 r 0 r 1 r n-2 r n-1 M 0 M 1 M 2 M n-2 M n-1 An n-input MISR can be remodeled as a single-input SISR with sequence M(x) and E(x) n 2 n 1 M ( x) = M 0( x) + xm1( x) x M n 2( x) + x M n 1( x) n 2 n 1 E( x) = E0( x) + xe1 ( x) x En 2( x) + x En 1( x) Page Output Response Analysis Signature Analysis (Parallel Example) M 0 M 1 M 2 M 3 M 0 M 1 M 2 M 3 M A 4-stage MISR An equivalent M sequence Aliasing probability P PSA ( n) = (2 ( ml n) 1) /(2 ml 1) Page 42 21

22 5.5 Logic BIST Architectures Four Types of BIST Architectures: No structure to the CUT Make use of in the CUT the scan chains for test pattern and output response Use concurrent circuitry of the design Page Logic BIST Architectures BIST Architectures for Non-scan Circuits Two LFSRs and two multiplexers are added to the circuit. The first LFSR acts as a, the second serves as a. The first multiplexer selects the inputs, another routes the PO to the SISR. PIs n M U X n CUT (C or S) m PRPG 1 MUX k 1 SISR TEST k = [log 2 m] CSBL Architecture Page 44 22

23 5.5 Logic BIST Architectures BIST Architectures for Non-scan Circuits Use a PRPG and a MISR. Pseudo-random patterns are applied in parallel from the PRPG to the chip primary inputs (PIs) and a MISR is used to compact the chip output responses. PIs P R P G CUT (C or S) M I S R BEST Architecture Page Logic BIST Architectures BIST Architectures for Scan Circuits In addition to the internal scan chain, an external scan chain comprising all and is required. The external scan-chain input is connected to the the internal scan chain. S in PRPG SISR S out R 1 R 2 PIs SRL CUT (C) S i S o POs SRL LOCST Architecture Page 46 23

24 5.5 Logic BIST Architectures BIST Architectures for Scan Circuits Contains a PRPG (SRSG) and a MISR. The are loaded in parallel from the PRPG. The clocks are then pulsed and the are scanned out to the MISR for compaction. New test patterns are scanned in at the as the test responses are being scanned out. PRPG PRPG Linear Phase Shifter CUT (C or S) CUT (C or S) MISR STUMPS Linear Phase Compactor MISR Page Logic BIST Architectures BIST Architectures w/ Register Reconfiguration The architecture applies to circuits that can be partitioned into (logic blocks). Each module is assumed to have its own input and output ( elements), or such are added to the circuit where necessary. The registers are so that for test purposes they act as PRPGs or MISRs. B 2 Y 0 Y 1 Y 2 B D Q D Q D Q Scan-In SCK X 0 X Scan-Out/X 2 1 BILBO Page 48 24

25 5.5 Logic BIST Architectures BIST Architectures w/ Register Reconfiguration Y 0 Y 1 Y 2 B 1 Scan-Out D Q 1D 2D Q SEL D Q 1D 2D Q SEL D Q 1D 2D Q SEL CBILBO Scan-In B 2 SCK X 0 X 1 X 2 Page Logic BIST Architectures BIST Architectures w/ Register Reconfiguration All primary inputs and primary outputs are reconfigured as scan cells. They are connected to the internal scan cells to form a path. During, all primary inputs (PIs) are connected as a shift register (SR), whereas all internal scan cells and primary outputs (POs) are reconfigured as a MISR. Fault coverage is. CIRCULATE S in 0 1 PIs SR MISR S out MISR CUT (C) MISR Y i X i CLK D Q Xi (a) The CSTP architecture POs (b) Self-Test cell Page 50 25

26 5.5 Logic BIST Architectures BIST Architectures w/ Concurrent Checking PRPG n Functional Circuitry m Duplicate Circuitry m Checking Circuitry two-rail checker CSV Architecture Page Fault Coverage Enhancement Three approaches to enhance the fault coverage Test point insertion Mixed-mode BIST Hybrid BIST Page 52 26

27 5.6 Fault Coverage Enhancement Test Point Insertion Page Fault Coverage Enhancement Test Point Insertion (Placement) Where to place the test points in the circuit to maximize the coverage and minimize the number of test points required. guided techniques guided techniques test point insertion technique During normal operation control points must be Random Deterministic Page 54 27

28 5.6 Fault Coverage Enhancement Mixed-Mode BIST (No Modification to CUT) patterns are generated to detect the RP-testable faults, and then some additional patterns are generated to detect the RP-resistant faults. Approaches.. ROM Compression LFSR Reseeding also LFSR Embedding Deterministic Patterns Decoding Logic Poly. Id Seeds LFSR Scan Chain Bit-Flipping Function Bit-flipping BIST Reseeding with multiplepolynomial LFSR Page Fault Coverage Enhancement Hybrid BIST (Load from Tester) For fault coverage enhancement where a tester is present, deterministic data from the tester can be used to improve the fault coverage. Top-up ATPG Store the deterministic patterns on the tester Page 56 28

29 5.7 BIST Timing Control To test -clock-domain circuits To detect -clock-domain faults and -clock-domain faults Capture-clocking schemes Single-capture Skewed-load Double-capture Page BIST Timing Control One-Hot Single Capture A capture pulse is applied to, while holding test clocks inactive, during each capture window. Benefit: a single and slow scan mode signal Drawback: long test time Shift Window Capture Window Shift Window Capture Window Shift Window CK1 CK2 d1 C1 d2 C2 GSE Page 58 29

30 5.7 BIST Timing Control Staggered Single Capture Benefits: short test time; a and global scan mode signal Drawback: some fault coverage loss if the ordered sequence of capture clocks is for all capture cycles Shift Window Capture Window Shift Window CK1 C1 d1 d2 d3 CK2 C2 GSE Page BIST Timing Control Skewed-Load An at-speed test technique Address -clock-domain faults Three approaches One-hot skewed-load Aligned skewed-load Staggered skewed-load Page 60 30

31 5.7 BIST Timing Control One-Hot Skewed-Load Tests all clock domains one by one by applying -followed by- pulses to detect intra-clock-domain delay faults. Drawbacks: (1) Cannot detect -clock-domain delay faults (2) Test time is long (3) Single and global scan enable (GSE) signal can no longer be used Shift Window Capture Window Shift Window Capture Window Shift Window CK1 SE1 CK2 SE2 S1 C1 d1 S2 C2 d2 Page BIST Timing Control Aligned Skewed-Load S1 S2 S3 C S C1 Capture Window S1 CK1 SE1 CK1 SE1 C2 CK2 SE2 CK2 SE2 C3 CK3 SE3 CK3 SE3 Capture aligned skewed-load Launch aligned skewed-load Benefits: Solve the long test time problem, Test all -clockdomain and -clock-domain faults Drawbacks: Need timing-control Page 62 31

32 5.7 BIST Timing Control Staggered Skewed-Load When two test clocks cannot be precisely, we can simply insert a proper to eliminate the clock skew. The last pulse is used to create a transition and the output responses are caught by the next pulse for each clock domain. This works for clock domains. Drawback: Need at-speed signal for each clock domain CK1 SE1 CK2 SE2 Shift Window Capture Window Shift Window S1 C1 d1 d3 S2 C2 d2 Page BIST Timing Control Double Capture Solve the difficulty using skewed-load True at-speed test Double-capture benefits Detect intra-clock-domain faults and inter-clock-domain faults or faults at-speed Facilitate physical implementation Ease with ATPG Page 64 32

33 5.7 BIST Timing Control One-Hot Double Capture Test all clock domains one by one by applying capture pulses at their respective domains to test intra-clock-domain delay faults. Benefit: true at-speed testing of -clock-domain faults Drawbacks: (1) Cannot detect -clock-domain delay faults (2) Test time is long Shift Window Capture Window Shift Window Capture Window Shift Window C1 C2 CK1 CK2 d1 C3 C4 GSE d2 Page BIST Timing Control Aligned Double-Capture C1 C2 C3 C C Capture Window CK1 CK1 C1 C4 C2 CK2 CK2 C3 CK3 GSE CK3 GSE Aligned double-capture - I Aligned double-capture - II Page 66 33

34 5.7 BIST Timing Control Staggered Double-Capture In the capture window, two capture pulses are generated for each clock domain. The first two capture pulses are used to create at the of scan cells, and the output responses to the transitions are by the next two capture pulses, respectively. Shift Window Capture Window Shift Window CK1 C1 C2 d1 d2 d3 d4 d5 CK2 C3 C4 GSE Page Fault Detection Note: A hybrid double-capture scheme using double-capture and double-capture seems to be the scheme for true at-speed testing Page 68 34

35 5.8 A Design Practice An example of designing a logic BIST system for testing a (core) comprising two clock domains using s38417 and s The two clock domains are taken from the benchmark circuits. Design statistics Page A Design Practice Design Flow BIST Rule and Violation Logic BIST System Design RTL Design Verification and Enhancement Page 70 35

36 5.8 A Design Practice BIST Rule Checking and Violation Repair All DFT rule violations of the design rules and design rules must be repaired. In addition, we should be aware of the following design parameters: The number of test clocks present in the design The number of set/reset clocks present in the design Page A Design Practice Logic BIST System Design The second step is to design the logic BIST system at the RTL, including: The type of logic BIST architecture to adopt The number of (or ) pairs to use The of each (or ) pair The faults to be tested and BIST diagrams to be used The types of to be added Page 72 36

37 5.8 A Design Practice Logic BIST Architecture We choose to implement a -based architecture, since it is easy to integrate with scan/atpg and is used in industry. Logic BIST Controller TPG SCK1 SCK2 PLL CK2 CK1 PRPG1 PS1/SpE1 PRPG2 PS2/SpE2 Data/ Control Input Selector PIs/ SIs Start Finish Result Test Controller CCK1 CCK2 Clock Gating Block TCK1 TCK2 Clock Domain CD1 C Clock Domain CD2 BIST-Ready Core POs/ SOs SpC1 SpC2 MISR1 ORA MISR2 A logic BIST system for testing a design with 2 cores Page A Design Practice TPG and ORA Next, we need to determine the of each PRPG- MISR pair. Using a PRPG-MISR pair for each clock domain allows us to the of each PRPG and MISR. PRPG-MISR Choices Page 74 37

38 5.8 A Design Practice Test Controller The test controller plays a central role in the overall BIST operation. Often, external signals are controlled through an IEEE Standard based test access port (TAP) controller. In order to test faults in the BISTready core, we choose the staggered single-capture approach. TCK1 Shift Window Capture Window Shift Window C1 TCK2 C2 GSE Slow-speed timing control using staggered single-capture Page A Design Practice Asynchronous Clocks In order to test faults in the BIST-ready core, we choose the staggered doublecapture approach if CD1 and CD2 are asynchronous TCK1 TCK2 GSE Shift Window Capture Window Shift Window C1 C2 d C3 C4 Staggered double-capture SE1 BIST mode SE1 Generator CK1 SE2 Generator 2-Pulse Controller SE2 CK2 CK1 TCK1 2-Pulse Controller A daisy-chain clock-triggering circuit CK2 TCK2 Page 76 38

39 5.8 A Design Practice Synchronous Clocks In order to test delay faults in the BIST-ready core, we choose the launch-aligned double-capture approach if CD1 and CD2 are synchronous TCK1 TCK2 GSE Shift Window Capture Window Shift Window C1 C2 C3 C4 Launch aligned double-capture 0 CK TCK1 BIST mode GSE Generator GSE 0 CK CK1 CK2 TCK2 A clock suppression circuit Page A Design Practice Re-Timing Logic We recommend adding two pipelining registers between each and the BIST-ready core, and two additional pipelining registers between the BISTready core and each. In this case, the maximum scan chain length for each clock domain, CD1 or CD2, is effectively increased by, not. Page 78 39

5.8 A Design Practice Fault Coverage Enhancing Logic and Diagnostic Logic In order to improve the circuit s fault coverage, we recommend adding and additional logic for top-up ATPG support at the RTL.

40 5.8 A Design Practice Fault Coverage Enhancing Logic and Diagnostic Logic In order to improve the circuit s fault coverage, we recommend adding and additional logic for top-up ATPG support at the RTL. We also recommend including in the RTL BIST code to facilitate and. Example test modes to be supported by the logic BIST system Page A Design Practice RTL BIST Synthesis At this stage, it is possible to either the logic BIST system or generate the RTL code using a (commercially available) RTL logic BIST tool. In either case, the number of for each clock domain should be specified along with the of their associated scan inputs (SIs) and scan outputs (SOs) without the actual scan chains into the circuit. Page 80 40

41 5.8 A Design Practice Design Verification and Fault Coverage Enhancement Finally, the synthesized netlist needs to be verified with and/or verification. Next, needs to be performed on the pseudo-random patterns generated by the TPG in order to determine the circuit s. Gate-Level Test Point Insertion Test Point Selection at RTL Design No Logic/Scan Synthesis Fault Simulation Coverage Acceptable? Yes Done Fault simulation and test point insertion flow Page 81 41

Chapter 5. Logic Built-In Self-Test. VLSI EE141 Test Principles and Architectures Ch. 5 - Logic BIST - P. 1

Chapter 5. Logic Built-In Self-Test. VLSI EE141 Test Principles and Architectures Ch. 5 - Logic BIST - P. 1 Chapter 5 Logic Built-In Self-Test VLSI EE141 Test Principles and Architectures Ch. 5 - Logic BIST - P. 1 1 What is this chapter about? Introduce the basic concepts of logic BIST BIST Design Rules Test