SA4NCCP 4-BIT FULL SERIAL ADDER

Transcription

1 SA4NCCP 4-BIT FULL SERIAL ADDER CLAUZEL Nicolas PRUVOST Côme

2 SA4NCCP 4-bit serial full adder Table of contents Deeper inside the SA4NCCP architecture...3 SA4NCCP characterization...9 SA4NCCP capabilities...12 Trademarks This document is the report of a study made during the course of Physic and Electronic Component Modeling at the Institut National des Sciences Appliquées of Toulouse. It was made using the Microwind software which is copyrighted by its owner. SA4NCCP is a fictive product and is not available anywhere. Pruvozel Semiconductors is not a registered trademark but it's logo was made by Côme PRUVOST and is licensed as creative common nc-by-sa 2.0.

3 SA4NCCP 4-bit serial full adder The SA4NCCP is a 4-bit adder designed to be easy to use, implement and extend. It perfectly fits into a complex calculus MOS component. The design of the SA4NCCP follows five main guidelines: minimize space to increase working frequency and lower needed silicon, modular conception to ease implementation, rectangular modules to fit one in another and gain in space lost, reduce needed layers to increase the number of layers available to wiring, take a carry as input to allow SA4NCCP chaining and deal with larger binary words. Deeper inside the SA4NCCP architecture A 4-bit adder take 2 4-bit-coded numbers as input and a carry bit and realizes the addition operation of this two numbers and the carry. It outputs the result as a 4-bit-coded number and an out carry bit. (See Figure 3 page 5). The SA4NCCP is designed element by element to optimize as much as possible each step of conception and fit to the guidelines. In its final design, all the inputs are placed left while outputs are placed left. Power supplies, required by the MOS transistors, are both connectible at the top of the structure and as they are propagated inside the adder, there is no need to wire them elsewhere. These two features make the SA4NCCP easily wired and integrable in a more complex circuit. The exception is made for the out carry bit which is placed bottom left. The reason is that such a placement allows SA4NCCP chaining by simply piling them up in column. As you might see, power supplies are also propagated to the bottom so you can stack up SA4NCCPs without the need to wire power supplies to each adder. Dealing with more than 4-bit operation is then as simple as Ctrl-C Ctrl-V. The SA4NCCP only uses the first and second metal layer to wire its elements. As such, you have all the place you need to link the SA4NCCP with other components and route a more complex structure that fit your needs. Internally, the SA4NCCP is an association of 4 1-bit full adders intelligently arranged. The 1-bit adder composing the SA4NCCP is designed to be as compact and rectangular as possible in order to lost as few space as possible even when chained into a more complex adder. The elements inside the 1-bit adder have been rearranged to gain in space and compactness. Some guidelines are yet respected; inputs are placed left and outputs right, with the same exception for the carry. Power supplies are yet propagated top to bottom. (See Figure 2 page 4). Each 1-bit adder block is made of two half-adder block and one or-gate. Figure 1: Representation of a full adder. U1 and U2 are half-adders and U3 is a or-gate.

4 Figure 2: Full adder layout.

5 Figure 3: The SA4NCCP 4-bit full adder layout.

6 Each half-adder can output a sum and a carry but for 2 input bits only. A half-adder does not take care of an extra input carry. Another half-adder and a or-gate are necessary to achieve the complete addition operation. Figure 4: Blocks organization in the 1-bit full adder. The blocks are arranged intelligently to follow the guidelines. For example, the or-gate is made by the association of a nor-gate and a not-gate. In the full 1-bit adder, these two blocks are dissociated because not-gate best fitted elsewhere than right after the nor-gate. As half-adders were yet rectangular, their placement came easily. To focus on them, half-adders are able to calculate the sum and carry for two inputs only. They are made by the association of a xor-gate and a and-gate. Figure 5: Half adder Once again, a huge work has been made to stick to the guidelines, especially to minimize space and establishment period. The result is a rectangular layout, easy to interlink into a bigger structure thanks to the propagation of power supplies. The xor-gate is a little more complex gate as it is made of 3 nand-gates and 2 inverters.

7 A A xor B= B A B Figure 6: XOR gate Figure 7: XOR gate layout In the xor-gate layout, choice was made to allow the lost of a little space between the two first-stage nand-gates and the second stage nand-gate in favor of a rectangular design. Thus, less space is lost in interlinking the xor-gate inside the half-adder. It's a little lost for big gains. Or- and and-gates are made associating nor- and nand-gates with inverters. Nor- and nand-gates are a simple association of pmos and nmos transistors. Again, elements are arranged in order to take as few place and be as fast as possible.

8 Figure 8: NAND gate diagram and layout Figure 9: NOR gate diagram and layout

9 SA4NCCP characterization In the previous section, we analyzed the design from the complete structure to the smallest composing block. We will adopt a reverse method to analyze characteristics of the SA4NCCP as response time and maximum working frequency. As pmos and nmos have different behaviors regarding logic signals, mixing both is needed to produce perfect response. In fact, when nmos gate is enabled (logic 1 or Vdd+), a 0 (Vss-) applied on the source is completely translated by a 0 on the drain. On the contrary, a 1 applied on the source is lowered on the drain. Nmos has good 0 but poor 1. Pmos acts as a mirror producing, when gate is disabled, a poor 0 and a good 1 Figure 10: nmos transistor layout and time analysis. We can see that '1' is badly transmitted while '0' is perfectly set.

10 The second very important parameter is establishment time. At each level, a short establishment time will ensure a highest velocity for the component. This establishment time is restricted by the size of transistor. Bigger is the transistor, longer is the way for electrons to reach the other side of the gate and larger is the transition time. That's why the SA4NCCP was designed at each level to be as small as possible, reaching the minimum of space of elements and between elements. Figure 11: Simulation of a XOR gate Figure 12: Simulation of an half-adder. C is carry and S is sum.

11 At half-adder level, the maximum establishment time is 8ps. To be sure, this value is doubled, so the signal is well established. Inverted, we can say that this half-adder can work at 62GHz! Of course, such a frequency is never reached as more complex operations are needed to be useful. Based on this half-adder, the 1-bit full adder will benefit of this high working frequency. Figure 13: Simulation of the 1-bit full adder. Cin is carry input and Cout carry output. S is still sum. The maximum establishment time for the 1-bit full adder is 31ps. Then, this module can be used at a maximum of 16,12GHz. This lowering is due to the cascading of two half-adders and one or-gate.

12 Figure 14: Simulations of the 4-bit full adder. x[0] to x[3] are the four pins of a same input/output, a and b are the 4-bit-encoded words to add and s is the addition result. Once again, cascading element result in an increase of establishment time and a loose of maximum frequency. Thus, the SA4NCCP has an establishment time as low as 0.203ps, 0.406ps when doubled. The SA4NCCP is able to work at 2.46GHz. SA4NCCP capabilities Here is the comparison between the SA4NCCP and the 4-bit full adder example included inside the Microwind package. SA4NCCP Microwind example Working frequency: 2.5GHz Height: 275µm Width: 50µm Surface: 13750µm² Working frequency: 1GHz Height: 105µm Width: 165µm Surface: 17325µm² As a conclusion, we can say that the SA4NCCP strictly follows its guidelines, and reaching its goals of modularity, ease of use and high frequency. Nevertheless, cascading 1-bit full adder is a short term solution which is not viable for wide byte words. In fact, cascading such modules adds their establishment time and decrease its frequency. Such devices are called ripple carry adders. To deal with large numbers, operations must be done in parallel, using another architecture. Carry lookahead adders can then be a solution. Transforming the SA4NCCP in a 4-bit subtractor is easy, only inverting one of the input word and adding 1 is needed. With a multiplexer, the SA4NCCP can become a very efficient adder-subtractor.