3.3V CMOS DUAL J-K FLIP-FLOP WITH SET AND RESET, POSITIVE-EDGE TRIG- GER, AND 5 VOLT TOLERANT I/O DESCRIPTION:

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1 IDT7LV109A.V MOS DUAL J-K FLIP-FLOP WITH SET AND RESET EXTENDED OMMERIAL TEMPERATURE RANGE.V MOS DUAL J-K FLIP-FLOP WITH SET AND RESET, POSITIVE-EDGE TRIG- GER, AND T TOLERANT I/O IDT7LV109A FEATURES: 0. MIRON MOS Technology ESD > 00 per MIL-STD-88, Method 01; > 0 using machine model ( = 00pF, R = 0) 1.7mm pitch SOI, 0.mm pitch SOP, 0.mm pitch SSOP, 0.mm pitch TSSOP packages Extended commercial range of 0 to +8 V =.V ±0.V, Normal Range V =.V to.v, Extended Range MOS power levels (0.µ W typ. static) Rail-to-Rail output swing for increased noise margin All inputs, outputs and I/O are Volt tolerant Supports hot insertion Drive Features for LV109A: High Output Drivers: ±ma Reduced system switching noise APPLIATIONS: V and.v mixed voltage systems Data communication and telecommunication systems DESRIPTION: The LV109A dual J-K flip-flop with set and reset, positive-edge trigger is built using advanced dual metal MOS technology. This device features individual J, K inputs, clock (P) inputs, set (SD) and reset (RD) inputs; also complementary and outputs. The set and reset are asynchronous active low inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the function table. The J and K inputs must be stable one setup time prior to the low-tohigh clock transition for predictable operation. The J-K design allows operation as a D-type flip-flop by tying the J and K inputs together. Inputs can be driven from either.v or V devices. This feature allows the use of this device as a translator in a mixed.v/v supply system. The LV109A has been designed with a ±ma output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. FUNTIONAL BLOK DIAGRAM K 7 J SD RD 1 P Pin numbers are for section 1. Refer to pin configuration for section pin numbers. EXTENDED OMMERIAL TEMPERATURE RANGE 1 c AUGUST Integrated Device Technology, Inc. DS-7/-

2 IDT7LV109A.V MOS DUAL J-K FLIP-FLOP WITH SET AND RESET PIN ONFIGURATION EXTENDED OMMERIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) 1RD 1J 1K 1P 1SD 1 1 GND 1 1 V 7 SO1-7 SO1-8 SO1-9 SO SOP/ SOI/ SSOP/ TSSOP TOP VIEW RD J K P SD Symbol Description Max. Unit ERM () Terminal Voltage with Respect to GND 0. to +. V ERM () Terminal Voltage with Respect to GND 0. to +. V TSTG Storage Temperature to +10 IOUT D Output urrent 0 to +0 ma IIK IOK I ISS ontinuous lamp urrent, VI < 0 or VO < 0 ontinuous urrent through each V or GND 0 ma ±100 ma 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.. V terminals.. All terminals except V. FUNTIONAL DIAGRAM APAITANE (TA = +, f = 1.0MHZ) Symbol Parameter (1) onditions Typ. Max. Unit IN Input apacitance VIN =. pf 1SD 1J J SD 1P P FF1 1K K RD OUT I/O Output apacitance I/O Port apacitance 1. As applicable to the device type. VOUT =. 8 pf VIN =. 8 pf 1 1R D SD J J SD P P FF K K 10 9 PIN DESRIPTION Pin Names Description xp lock Inputs, LOW-to-HIGH, edge-triggered xrd Asynchronous Reset Input (Active LOW) xsd Asynchronous Set Inputs (Active LOW) 1 RD RD xj, xk x Synchronous Inputs True Flip-Flop Outputs x omplement Flip-Flop Outputs

3 IDT7LV109A.V MOS DUAL J-K FLIP-FLOP WITH SET AND RESET EXTENDED OMMERIAL TEMPERATURE RANGE FUNTION TABLE (1) Inputs Outputs Operating Modes xsd xrd xp xj xk x x Asynchronous set L H X X X H L Asynchronous reset H L X X X L H Undetermined L L X X X H H Toggle H H h l 0 0 Load 0 (reset) H H l l L H Load 1 (set) H H h h H L Hold no change H H l h H = HIGH voltage level h = HIGH voltage level of input set-up time prior to the LOW-to-HIGH P transition L = LOW voltage level l = LOW voltage level of input set-up time prior to LOW-to-HIGH P transition X = Don t care = LOW-to-HIGH P Transition 0 = Level of before the indicated steady-state input conditions were established. 0 = omplement of 0 or level of before the indicated steady-state input conditions were established. D ELETRIAL HARATERISTIS OVER OPERATING RANGE Following onditions Apply Unless Otherwise Specified: Operating ondition: TA = 0 c to +8 c Symbol Parameter Test onditions Min. Typ. (1) Max. Unit Input HIGH Voltage Level V =.V to.7v 1.7 V V =.7V to.v VIL Input LOW Voltage Level V =.V to.7v 0.7 V V =.7V to.v 0.8 IIH Input Leakage urrent V =.V VI = 0 to.v ± µ A IIL IOZH High Impedance Output urrent V =.V VO = 0 to.v ±10 µ A IOZL (-State Output pins) IOFF Input/Output Power Off Leakage V =, VIN or VO.V ±0 µ A VIK lamp Diode Voltage V =.V, IIN = 18mA V VH Input Hysteresis V =.V 100 mv IL IH IZ I uiescent Power Supply urrent V =.V VIN = GND or V 10 µa uiescent Power Supply urrent Variation 1. Typical values are at V =.V, + ambient. One input at V 0.V other inputs at V or GND 00 µ A c 1998 Integrated Device Technology, Inc. DS-1

4 IDT7LV109A.V MOS DUAL J-K FLIP-FLOP WITH SET AND RESET EXTENDED OMMERIAL TEMPERATURE RANGE OUTPUT DRIVE HARATERISTIS Symbol Parameter Test onditions (1) Min. Max. Unit Output HIGH Voltage V =.V to.v IOH = 0.1mA V 0. V V =.V IOH = ma V =.V IOH = 1mA 1.7 V =.7V. V =.. V =. IOH = ma. Output LOW Voltage V =.V to.v IOL = 0.1mA 0. V V =.V IOL = ma 0. IOL = 1mA 0.7 V =.7V IOL = 1mA 0. V =. IOL = ma and VIL must be within the min. or max. range shown in the D ELETRIAL HARATERISTIS OVER OPERATING RANGE table for the appropriate V range. TA = 0 to +8. OPERATING HARATERISTIS, T A = V =.V±0.V V =.V±0.V Unit Symbol Parameter Test onditions Typical Typical PD Power Dissipation apacitance per flip-flop L = 0pF, f = 10Mhz pf SWITHING HARATERISTIS (1) V =.V±0.V V =.7V V =.V±0.V Symbol Parameter Min. Max. Min. Max. Min. Max. Unit tplh Propagation Delay ns tphl xp to x or x tplh Propagation Delay ns xsd to x or xrd to tphl Propagation Delay ns xsd to x or xrd to tsu Set-up Time, xj, xk to xp... ns th Hold Time, xj, xk to xp ns trem Removal Time, xsd, xrd to xp ns tw tw Pulse Width LK HIGH or LOW Set or Reset Pulse Width, HIGH or LOW... ns ns tsk(0) Output Skew () 00 ps 1. See test circuits and waveforms. TA = 0 to Skew between any two outputs of the same package and switching in the same direction.

5 IDT7LV109A.V MOS DUAL J-K FLIP-FLOP WITH SET AND RESET EXTENDED OMMERIAL TEMPERATURE RANGE TEST ONDITIONS TEST IRUITS AND WAVEFORMS PROPAGATION DELAY Symbol V (1) =.V ±0.V V () =.V ±0.V &.7V Unit VLOAD x Vcc V Vcc.7 V V / 1. V VLZ mv VHZ mv L 0 0 pf TEST IRUITS FOR ALL OUTPUTS (1, ) Pulse Generator VIN RT V D.U.T. VOUT L 00Ω 00Ω VLOAD Open GND DEFINITIONS: L= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 1. Pulse Generator for All Pulses: Rate 10MHz; tf ns; tr ns.. Pulse Generator for All Pulses: Rate 10MHz; tf.ns; tr.ns. SAME PHASE TRANSITION OUTPUT OPPOSITE PHASE TRANSITION tplh tplh tphl tphl ENABLE AND DISABLE TIMES ONTROL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITH LOSED tpzh SWITH OPEN VLOAD/ DISABLE tphz tplz VLOAD/ VLZ VHZ 1. Diagram shown for input ontrol Enable-LOW and input ontrol Disable-HIGH. SWITH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests OUTPUT SKEW - tsk (x) OUTPUT 1 OUTPUT tplh1 tplh tsk (x) tphl1 tphl Switch VLOAD GND Open tsk (x) tsk(x) = tplh - tplh1 or tphl - tphl1 1. For tsk(o) OUTPUT1 and OUTPUT are any two outputs.. For tsk(b) OUTPUT1 and OUTPUT are in the same bank. SET-UP, HOLD, AND RELEASE TIMES DATA TIMING SYNHRONOUS ONTROL ASYNHRONOUS ONTROL PULSE WIDTH LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tsu tsu tw trem th th

6 IDT7LV109A.V MOS DUAL J-K FLIP-FLOP WITH SET AND RESET EXTENDED OMMERIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX LV XXXX XX Temp. Range Device Type Package D PY PG 109A uarter Size Outline Package (SO1-7) Small Outline I (SO1-8) Shrink Small Outline Package (SO1-9) Thin Shrink Small Outline Package (SO1-10) Dual J-K Flip-Flop with Set and Reset, Postive-Edge Trigger, ±ma 7-0 to +8 ORPORATE HEADUARTERS for SALES: 97 Stender Way or Santa lara, A 90 fax: *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press. The IDT logo is a registered trademark of Integrated Device Technology, Inc.