Octal 3-State Bus Transceivers and D Flip-Flops High-Performance Silicon-Gate CMOS

Transcription

1 TECNICA DATA IN74C652A Octal 3-State Bus Traceivers and D Flip-Flops igh-performance Silicon-Gate CMOS The IN74C652A is identical in pinout to the S/AS652. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with S/ASTT outputs. These devices coist of bus traceiver circuits, D-type flip-flop, and control circuitry arranged for multiplex tramission of data directly from the data bus or from the internal storage registers. Direction and Output Enable are provided to select the read-time or stored data function. Data on the A or B Data bus, or both, can be stored in the internal D flip-flops by low-to-high traitio at the appropriate clock pi (A-to-B Clock or B-to-A Clock) regardless of the select or enable or enable control pi. When A-to-B Source and B-to-A Source are in the real-time trafer mode, it is also possible to store data without using the internal D-type flip-flops by simulta-neously enabling Direction and Output Enable. In this configuration each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state. The IN74C652A has noninverted outputs. Outputs Directly Interface to CMOS, NMOS, and TT Operating Voltage Range: to V ow Input Current: 1.0 μa igh Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74C651AN Plastic IN74C651ADW SOIC T A = -55 to 125 C for all packages PIN ASSIGNMENT OGIC DIAGRAM PIN 24=V CC PIN 12 = GND

2 IN74C652A MAXIMUM RATINGS * Symbol Parameter Value Unit V CC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V V IN DC Input Voltage (Referenced to GND) -1.5 to V CC +1.5 V V OUT DC Output Voltage (Referenced to GND) -0.5 to V CC +0.5 V I IN DC Input Current, per Pin ±20 ma I OUT DC Output Current, per Pin ±35 ma I CC DC Supply Current, V CC and GND Pi ±75 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -65 to +150 C T ead Temperature, 1 mm from Case for 10 Seconds 260 C (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 10 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V CC DC Supply Voltage (Referenced to GND) V V IN, V OUT DC Input Voltage, Output Voltage (Referenced to GND) 0 V CC V T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figures2,3) V CC = V V CC = V V CC = V This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. owever, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be cotrained to the range GND (V IN or V OUT ) V CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. I/O pi must be connected to a properly terminated line or bus.

3 IN74C652A DC EECTRICA CARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditio V 25 C to -55 C V I Minimum igh- evel Input Voltage V I Maximum ow - evel Input Voltage V O Minimum igh- evel Output Voltage V OUT = V or V CC - V I OUT 20 μa V OUT = V or V CC - V I OUT 20 μa V IN =V I or V I I OUT 20 μa V CC Guaranteed imit C C Unit V V V V IN =V I or V I I OUT ma I OUT 7.8 ma V O Maximum ow- evel Output Voltage V IN = V I or V I I OUT 20 μa V V IN =V I or V I I OUT ma I OUT 7.8 ma) I IN Maximum Input eakage Current V IN =V CC or GND (Pi 1,2,3,21,22,and 23) ± ±1.0 ±1.0 μa I OZ Maximum Three- State eakage Current Output in igh-impedance State V IN = V I or V I V OUT =V CC or GND, I/O Pi ±0.5 ±5.0 ±10 μa I CC Maximum Quiescent Supply Current (per Package) V IN =V CC or GND I OUT =0μA μa

4 IN74C652A AC EECTRICA CARACTERISTICS (C =50pF,Input t r =t f = ) V CC Symbol Parameter V 25 C to -55 C t P, t P t P, t P t P, t P t PZ, t PZ t PZ, t PZ t T, t T Maximum Propagation Delay, Input A to Output B (or Input B to Output A) (Figures 2,3 and 9) Maximum Propagation Delay, A-to-B Clock to Output B (or B-to-A Clock to Output A) (Figures 1 and 9) Maximum Propagation Delay, A-to-B Source to Output B (or B-to-A Source to Output A) (Figures 4 and 9) Maximum Propagation Delay, Direction or Output Enable to Output A or B (Figures 5,6 and 10) Maximum Propagation Delay, Direction or Output Enable to Output A or B (Figures 5,6 and 10) Maximum Output Traition Time, Any Output (Figure 2) Guaranteed imit 85 C 125 C Unit C IN Maximum Input Capacitance pf Maximum Three-State I/O Capacitance pf (Output in igh-impedance State C OUT C PD Power Dissipation Capacitance (Per Channel) Used to determine the no-load dynamic power coumption: P D =C PD V CC 2 f+i CC V CC C,V CC =5.0 V 60 pf

5 IN74C652A TIMING REQUIREMENTS (Input t r =t f = ) V CC Guaranteed imit Symbol Parameter V 25 C to-55 C 85 C 125 C Unit t su t h t w t r, t f Minimum Setup Time, Input A to A-to-B Clock (or Input B to B-to-A Clock) (Figure 7) Minimum old Time, A-to-B Clock to Input A (or B-to-A Clock to Input B) (Figure 7) Minimum Pulse Width, A-to-B Clock (or B-to-A Clock) (Figure 7) Maximum Input Rise and Fall Times (Figures 2 and 3) TIMING DIAGRAM

6 IN74C652A FUNCTION TABE Dir. OE CAB CBA SAB SBA A B FUNCTION INPUTS INPUTS Both the A bus and the B bus are inputs. X X X X Z Z The output functio of the A and B bus are disabled. X * X X X * X X X INPUTS INPUTS Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high traition of the clock inputs. OUTPUTS INPUTS The A bus are outputs and the B bus are inputs. The data at the B bus are displayed at the A bus. The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high traition of the clock pulse. X * X X Qn X The data stored to the internal flip-flops, are displayed at the A bus. X * X INPUTS X X * X X * X The data at the B bus are stored to the internal flip-flops on low to high traition of the clock pulse. The states of the internal flip-flops output directly to the A bus. OUTPUTS The A bus are inputs and the B bus are outputs. The data at the A bus are displayed at the B bus. The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flops on low to high traition of the clock pulse. X X * X X Qn The data stored to the internal flip-flops are displayed at the B bus. X * X The data at the A bus are stored to the internal flip-flops on low to high traition of the clock pulse. The states of the internal flip-flops output directly to the B bus. OUTPUTS OUTPUTS Both the A bus and the B bus are outputs X X Qn Qn The data stored to the internal flip-flops are displayed at the A and B bus respectively. Qn Qn The output at the A bus are displayed at the B bus, the output at the B bus are displayed at the A bus respec. X : DON T CARE Z : IG IMPEDANCE Qn : TE DATA STORED TO TE INTERNA FIP-FOPS BY MOST RECENT OW TO IG TRANSITION OF TE COCK INPUTS * : TE DATA AT TE A AND B BUS WI BE STORED TO TE INTERNA FIP-FOPS ON EVERY OW TO TRANSITION OF TE COCK INPUTS

7 IN74C652A SWITCING DIAGRAMS Figure 1. Switching Waveforms Figure 2. A Data Port = Input, B Data Port = Output Figure 3. A Data Port = Output, B Data Port = Input Figure 4. Switching Waveforms Figure 5. Switching Waveforms

8 IN74C652A Figure 6. Switching Waveforms Figure 7. Switching Waveforms Figure 9. Test Circuit Figure 10. Test Circuit

9 IN74C652A EXPANDED OGIC DIAGRAM

10 IN74C652A N SUFFIX PASTIC DIP (MS - 001AF) 24 1 A 12 B Dimeion, mm Symbol MIN MAX A B C 5.33 F D NOTES: 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0.25 mm (0.010) per side. G 0.25 (0.010) M T D N C -T- K SEATING PANE M J F G J 0 10 K M N 0.38 D SUFFIX SOIC (MS - 0AD) -T D A G (0.010) M T C M B K P Symbol MIN MAX A B C D F NOTES: J Dimeio A and B do not include mold flash or protrusion. K Maximum mold flash or protrusion 5 mm (0.006) per side M for A; for B 0.25 mm (0.010) per side. P R C SEATING PANE J R x 45 F M G Dimeion, mm