Advanced WLP Platform for High-Performance MEMS. Presented by Dean Spicer, Director of Engineering

Transcription

1 Advanced WLP Platform for High-Performance MEMS Presented by Dean Spicer, Director of Engineering 1 May 11 th,

2 Outline 1. Application Drivers for High Performance MEMS Sensors 2. Approaches to Achieving High Performance 3. Discrete Packaging 4. Wafer Level Packaging 5. Advanced Wafer Level Packaging - MicraSilQ TM 2

3 Application Drivers for High Performance MEMS 1. A particular subset of accelerometer designs need Advanced Wafer Level Packaging with the MEMS device sealed in high vacuum» Low noise, high sensitivity 3

4 Closed Loop Operation Micromachined High Resolution Accelerometer, Krishnan et al., Journal of Indian Institute of Science, Vol. 87:3 1. Low Noise & High Sensitivity Closed loop configuration 2. Signal from the sensor is the amplitude of the feedback necessary to keep the MEMS mass from moving relative to the input acceleration on the device 3. Improved linearity and range due to very small motion of the MEMS mass 4. Bandwidth of the system increases by a factor equal to the loop gain 5. High SNR elimination of squeeze film damping reduction of Brownian noise 4

5 Brownian Noise Micromachined High Resolution Accelerometer, Krishnan et al., Journal of Indian Institute of Science, Vol. 87:3 Noise due to the impact of gaseous molecules with the MEMS mass T The mass-spring system is in contact with a thermal bath at temperature, T Thermal energy enters from the bath and is dissipated by oscillator motion This motion represents the thermal noise floor of the sensor Noise - want this to be small! A f 4kBTω mq rms noise 0 = Noise floor falls with lowered resonant frequency, increased proof mass and increased Q-factor Where: ω = 0 k m mω = b Q 0 5

6 Q Factor and Noise What does this mean for the noise limit of high performance accelerometers? m = 1 mg rms Anoise 4kBTω0 ω 0 = 4000 rad/s (~640 Hz) = f mq Q ~ 50, Noise (ng/sqrt(hz) Noise (ng/sqrt(hz) Q Pressure (Pa) 6

7 Discrete Packaging for MEMS High performance (low noise) MEMS using discrete packaging» Ceramic package with hermetically sealed lid High vacuum MEMS environment Wide seal ring with high temperature solder (AuSn) or glass frit Getter can be incorporated into the package to ensure performance over the lifetime of the product» Disadvantages Cost - associated die level processing can be >50% of the total device cost Difficult to scale Bulky package consumes valuable board real estate 7

8 Wafer Level Packaging Approaches 1. Standard WLP» Wafer bonding» Device protection, some level of hermeticity» Electrical connections often done using exposed lateral bondpad strategy» Two stage sawing to expose bond pads, then singulate» Still requires die level processing (attach, wirebonding) Hermetic seal Side electrical feed through MEMS layer Cap Base wafer 8

9 Advanced Wafer Level Package MicraSilQ Developed by Micralyne and implemented on a customer design as a next generation solution to remove ceramic package. Getter Metal for In-process Test Lid Wafer Au-Si Eutectic Bond Comb Structures Cavity, Bumps Polysilicon Filled Vias Under Bump Metallization Lead-free Solder Base Wafer Device Wafer 60 µm 9

10 Advanced Wafer Level Packaging Protection of MEMS device Decreased die level processing Electrical connection to MEMS Standard WLP Yes Yes Lateral feed through with wirebond Advanced WLP - MicraSilQ TM Yes Yes Vias with BGAs Vacuum level ~20 Pa (150 mtorr) <0.5 Pa * (4 mtorr) Hermeticity Unknown * * Examination of Key Packaging Metrics of a Hermetically sealed MEMS Accerometer, Krabbe et al., IWLPC Nov

11 Subtle Advantages of Advanced WLP In the past chips made by fabs, packaging done by packaging house 1. Advanced Wafer Level Packaging can skip the need for a separate supplier of packaging services 2. Easier to solve problems that have interactions between MEMS fabrication and the packaging process 3. With separate suppliers, more effort is put into establishing who owns the problem than in actually solving it 11

12 Three Functional Silicon Layers Two Bonds Hermeticity of the bonding technologies is key to fabricating a MEMS inertial sensor capable of high Q factors Bottom wafers are fusion bonded Top wafer is bonded by the formation of Gold-Silicon Eutectic above 363ºC DSID-0C0903A9, Exact bond parameters are critical to the success of the bond and the ultimate performance of the device vacuum level temperature profile Typical bond line is ~100 µm (compare to 500 µm 1500 µm for solder seal of ceramic package) Base Lid Device 500 µm 60 µm 400 µm 12

13 Through Silicon Via Details Via First process Key TSV characteristics:» Doped poly-si fill material» 400 µm» >100 MΩ isolation from the substrate» <5 pf parasitic capacitance» TSV resistivity < 4 mω cm» < 10Ω via resistance UBM and BGA Base Lid Device 13

14 Integrated Getter Cavity Design Patternable Getter (2um) 50 µm gap Lid Wafer 500 µm 10 µm gap DSID-0C0903A9, Device Wafer 60 µm 20 µm gap Base Wafer 400 µm Getter is deposited on the lid wafer prior to bonding Cavity around the MEMS can be designed with bump stops 14

15 Backside Metallization and UBM AlSi metallization for backside metal traces (allows for re-distribution of the contacts) Passivation layer for damage protection and electrical isolation Under bump metallization (UBM) suitable for lead free solder balls SAC 405 solder balls (0.35 mm diameter) Solder balls are placed and then reflowed Ball attached yield of 99.9% across wafer Singulated chip is ready for direct attachment to board UBM optimized to ensure reliable attachment to FR4 15

16 MicraSilQ Wafer Level Packaging Platform > 50% Reduced cost through elimination of external packaging Established process for fast ramp to manufacturing Accelerometer, Gyroscope Simple board reflow mounting Custom device layer for your unique application Through Silicon Via (TSV) Design Kit Available! Lead free solder 16

17 Next Steps for MicraSilQ TM 1. Thinner die» Thinning of lid wafer straight forward» Thinning of base wafer requires development 2. Thicker Device Layer» Allows increased mass of the MEMS (therefore lower noise floor) 3. Vias with metal fill» Requires development» Via material would have to survive the eutectic bond process Base Lid Device 500 µm 60 µm 400 µm 17

18 Micralyne Consolidated Overview Founded 1982 (privatized 1998) Headquartered in Edmonton, Alberta, CA Facilities: 55,000 Sq Ft (5000m 2 ) MEMS Fab, Test, Metrology, Packaging, Administration 6 (150mm) Wafer Production Capacity variable based on mix 5K 10K wafers per month based on 5 layer process ISO 9001 and ISO certified 83 Employees Customers: Fortune 500 System OEMs Fabless MEMS Product Companies Medical, Optical and Industrial Device Companies Core Capabilities MEMS and Micro-fabrication on Silicon, Glass, Quartz and other base wafer materials MEMS Process and Micro Structure IP More than 30 years of micro and nano manufacturing know how Focus Markets Industrial Sensors Bio and Medical Sensors Optical Communications Engagement Model Engineering Services Process Design and Process Integration Modeling and Analysis Manufacturing Services Proof of Concept and Prototype Volume Wafer Production Backend Packaging and Test 18 18

19 Thank You! Dean Spicer, Director of Engineering Tel : x2256 Paul Pickering VP Sales & Marketing paulp@micralyne.com Tel :