SINGULATION BY PLASMA ETCHING. INTEGRATION TECHNIQUES TO ENABLE LOW DAMAGE, HIGH PRODUCTIVITY DICING.

Size: px

Start display at page:

Download "SINGULATION BY PLASMA ETCHING. INTEGRATION TECHNIQUES TO ENABLE LOW DAMAGE, HIGH PRODUCTIVITY DICING."

Joleen Norris
5 years ago
Views:

1 SINGULATION BY PLASMA ETCHING. INTEGRATION TECHNIQUES TO ENABLE LOW DAMAGE, HIGH PRODUCTIVITY DICING. Richard Barnett Dave Thomas Oliver Ansell ABSTRACT Plasma dicing has rapidly gained traction as a viable alternative to conventional blade and laser techniques for wafer singulation. This has been due mostly to the significant benefits plasma dicing delivers in relation to the quality and reliability of devices singulated in this manner. Key to the successful integration of plasma dicing, into the established hierarchy of singulation techniques, is how the ancillary parts of the process flow can be utilized or adapted to accommodate it. More importantly, is the ease at which this can happen and also, how implementation can be achieved in a cost effective manner. INTRODUCTION Deep silicon etching, using the Bosch process, has proven itself to be a ubiquitous technique for all aspects of the semiconductor and allied industries. The MEMS market owes it s existence to this approach, 3D stacking with TSVs would not be possible and now it has turned its sights on exacting a step change in performance and quality for the backend fab space. Much has been written and presented over recent times regarding the redeployment of DRIE as a means of singulating semiconductor die. Here, we will consider the process control techniques available on the DRIE process hardware and the advantages they bring to this application. But, also there will be an examination of how DRIE, in concert with the conventional dicing techniques, may offer broader benefits than if they were considered as competing for sole dominance of the market. BOSCH PROCESS The Bosch process (1) was developed as a means of creating deep anisotropic structures where conventional single step plasma or wet etching could not work. This technique uses a repeating cycle of distinct steps to create anisotropic silicon etching. The steps include a passivation step to protect the sidewall, a polymer removal step to clear the base of the etch front to expose next silicon to be etched and finally an isotropic silicon etch. This cycle is repeated as many times as is necessary to etch the target feature. This is illustrated in Figure 1, below. Figure 1 Basics of Bosch Process The Bosch process was first transferred into a productionised plasma etch tool by Surface Technology Systems plc (STS), one of SPTS predecessors. Many of the improvements to the first embodiment of the Bosch process were developed and introduced to the MEMS market by STS. These included methods of managing process conditions during the process time (Parameter Ramping) and dealing with the process conditions when buried layers were introduced (SOI) (2,3,4). Today, the range of devices and structures fabricated using the Bosch process is considerably broader than it was when first trialled in the mid 1990s (See Figure 2, below). But, when the complex structures used for inertial sensors or biomedical devices are broken down to their simplest form, we are simply etching trenches in silicon. This direct comparison with dicing lanes was the main contributor to the introduction of this technology for the backend singulation activities. 1 Copyright 2015 by ASME

Figure 3 Notching at buried layers Figure 2 Range of features etched using Bosch process NOTCHING For MEMS, in particular, there are many examples of devices etched to a buried and insulating

A parallel, of sorts, in the dicing world is the dicing tape, upon which wafers are mounted for the singulation process to take place.

When the Bosch process is used to etch silicon down to an insulating layer, a build-up of charge can occur on that layer, which will deflect ions laterally into the sidewall of the feature causing a

2 Figure 3 Notching at buried layers Figure 2 Range of features etched using Bosch process NOTCHING For MEMS, in particular, there are many examples of devices etched to a buried and insulating dielectric layer. In most cases, this layer exists purely as a sacrificial element which when removed allows the complex MEMS structures, formed by the Bosch process, to move freely. A parallel, of sorts, in the dicing world is the dicing tape, upon which wafers are mounted for the singulation process to take place. This is, in effect, a sacrificial layer, but more importantly, like the buried dielectric in the MEMS world, can cause some unwanted side-effects during the plasma dicing process. When the Bosch process is used to etch silicon down to an insulating layer, a build-up of charge can occur on that layer, which will deflect ions laterally into the sidewall of the feature causing a notch (See Figure 3, below). Normally, when considering the interdigitated fingers of an inertial device, some notching can be accommodated. However, when the phenomena is transferred to the underside of an active device which is being picked and placed onto a tape reel or other such receptacle, then the risk of damage or compromise is much higher. Consider the uncontrolled creation of a notch on a singulated die. Left unchecked, the constant deflection of ions into the sidewall would remove any of the protective sidewall passivation generated by the Bosch process. This leaves the device sidewall exposed to the free fluorine which isotropically etches the silicon. The longer this occurs the larger the lateral etch into the silicon sidewall becomes. The risk is increased when the use of an overetch has to be implemented. Overetch is the stage of additional etch time after the first portion of the etch reaches the buried layer, in this instance the dicing tape. The overetch is used to ensure the non-uniformity of the bulk etch is managed so that all areas of the wafer receive sufficient etch to remove all of the necessary silicon. The worst case scenario is where the etch front reaching the tape is not detected, but simply a timed etch is applied based on the bulk etch rate. This does not take into account any variation in the wafer thickness nor any change in the etch chamber performance. The ideal case requires an endpoint method able to detect the change in plasma conditions commensurate with reaching the tape. This would require an endpoint capability for low exposed silicon areas. This case would better allow for the minimal application of overetch and mitigate any risk due to excessive etch being applied to the wafer. The low exposed silicon area of the wafers to be singulated can pose a challenge to most endpoint techniques. SPTS developed Claritas (6) to provide clear endpoint capability even when the open area of a wafer was <1%. In the case of plasma dicing, the open area has been observed as <0.001%. Claritas has been able to detect a sufficiently strong signal change, at this level, 2 Copyright 2015 by ASME

Figure 4 Claritas TM endpoint performance versus standard OES It is clear that the erosion of silicon within the die footprint can be considered as large a risk to the device integrity as the chips

Of course, the MEMS world required control of this notching and methods for preventing it have already been implemented and are applicable to the dicing case as well.

3 Figure 4 Claritas TM endpoint performance versus standard OES It is clear that the erosion of silicon within the die footprint can be considered as large a risk to the device integrity as the chips and cracks seen from the conventional blade and laser dicing techniques. Of course, the MEMS world required control of this notching and methods for preventing it have already been implemented and are applicable to the dicing case as well. One of the techniques developed when the Bosch process was first introduced was a management of the standing charge by pulsing the bias RF during the etch. By having the RF off for a period of time during each of the Bosch steps, there would be time for the charge to dissipate. This would prevent deflection of incoming ions and reduce the lateral erosion and hence the notching. In combination with the pulsed bias RF, use of endpoint is critical in avoiding the creation of notching. By detecting that the etch front has reached the tape as early as possible gives the maximum possible headroom to apply the most appropriate overetch. The ability to apply endpoint detection to the overetch step itself can also further protect the device and tape. LANE DEFINITION When considering the Bosch process for a more conventional silicon etch, the appropriate definition of the features to be etched is one of the fundamental aspects. Plasma dicing is no different but not so easily achieved. Consider the substrate to be patterned; existing patterning, thinned (<200µm), surface topography, option to be mounted on to tape frame. None of these conditions provide the best case for use of conventional patterning methodologies. Photolithography can still be included as an option. However, some users may not want the additional steps and associated costs to be added at this stage of the process flow. As per any normal silicon etch, use of photolithography with a PR or oxide mask would provide sound patterning for the etch process. Clearly, sufficient material would be required in order to cope with the selectivity of the etch process and any surface topography, including solder bumps. Figure 7 Use of additional mask to pattern lane for dicing Figure 5 Claritas EPD traces for dicing, including overetch More importantly, the tight process control gained from this will improve throughput, eliminating costly extended timed etches. The images (Figure 6) below highlight what can occur if it is not used to mitigate the situation. Figure 6 Notch control with EPD (Left) and without (Right) For certain categories of device; e.g. silicon submounts, chipcard and PV, the photolithography approach should be the default choice. However, for memory, logic and some MEMS, these require some tangential thinking to provide a defined lane ready for the plasma etch to take place. None of this would affect material within the lanes that could have an impact on the integration of plasma dicing. Current plasma dicing technology is based on silicon DRIE etch and whilst the process modules, such as SPTS Rapier-S, can also do a reasonable job of etching dielectric layers they cannot etch metals. In fact, the chemistries and conditions required for etching metals are not typically compatible with the tapes and frames utilized in the singulation process. Without any additional steps, it is possible to produce defined lanes simply by modifying steps earlier in the process flow, potentially also dealing with the metals issue at the same time. It is suggested that with minor modifications to the mask layouts, removal of the metal and dielectric materials from the lanes can be undertaken at the patterning steps, as they occur throughout the process flow. By considering that to adopt this would require designer time and mask sets, it would be a oneoff cost. However, this would have the secondary effect of eliminating the test structures that normally occupy the dicing 3 Copyright 2015 by ASME

lane rather than taking up die footprint. This would be a problem and could prevent this scheme from being used. There are two ways of countering this aspect.

and arrangement. With this in mind, it would be possible to move the test structures into a region previously used for devices. E.g. For 1mm² die, a reduction in lane width could see approximately 20% increase in die per wafer.

This would allow use of the option to retain the existing upper materials as mask and definition for the dicing lane etch.

4 lane rather than taking up die footprint. This would be a problem and could prevent this scheme from being used. There are two ways of countering this aspect. Benefits of moving to DRIE for dicing have been reported elsewhere (4, 5, 7) and several of these pertain to the ability of designers to free up real estate by narrowing lanes and changing die shape and arrangement. With this in mind, it would be possible to move the test structures into a region previously used for devices. E.g. For 1mm² die, a reduction in lane width could see approximately 20% increase in die per wafer. It is easily conceivable that it would be possible to convert some of those additional die locations into test structures and still retain most of the gain from the design change. This would allow use of the option to retain the existing upper materials as mask and definition for the dicing lane etch. Figure 8 Use of upper layers to define dicing lane for etch Figure 9 Device with existing layers used as mask for dicing etch The alternative approach is to use a combination of the existing blade and/or laser dicing and plasma to effect the singulation. Irrespective of the material in the lanes, there have always been blade and laser solutions for singulation. This can be advantageous when considering definition of lanes for DRIE. It is the impact on die integrity that is the major detractor for the conventional methods. But, when considering them as a direct write for defining the lane for subsequent plasma etch these issues should not come into play. The chipping related to blade dicing would only occur when considering the cut through the whole wafer thickness, this need not be the case when only a cut through the upper layers is completed. Using laser to ablate the upper layers followed by a clean-up of the debris using a blade can also be an option. Neither technique requires an additional masking step with the normal co-ordinate control and alignment of conventional dicing systems applied. The capability to use blade/laser as a patterning step opens up many possibilities. Of course, retaining these techniques as a support mechanism for plasma etch means that some of the benefits may not be extracted. E.g. reduction of lane width, increased pattern density, flexibility of die shape & location. Figure 10 Dicing lane defined with laser and blade Further studies are required to determine the most suitable combined approach and how the different steps need to be optimized to truly work in concert with one another for thinner wafers, smaller die. An in-depth study which considers the die strength behavior of each scheme in direct comparison with one another will also be reported on. DICING TAPES Introduction of a new process technique can be difficult if it requires changes to established protocols or uses new or novel materials. A DRIE solution for dicing would not be totally unfamiliar to frontend fabs and users. However, it presents a new set of criteria to backend fab users, and the frontend vendor also needs to take account of the substrates and protocols used in this area including; materials of substrates, treatment of material, recovery of broken wafers. Figure 11 Broken wafers remounted to complete processing The most significant aspect of the framed substrate is the tape as it serves as the sole preserver of mechanical integrity for the wafer before and after singulation. In order to ease the introduction of plasma based dicing, accommodation of existing tapes, and frames, was the primary aspect included in the SPTS design brief. No element of bespoke material was considered 4 Copyright 2015 by ASME

When considering the conditions the backend substrate, and therefore the tape, has to endure it is wise to understand how the tape would be behave.

5 due to the breadth of the existing infrastructure and the likely resistance to significant change. So an understanding of the materials is paramount to ensure the DRIE system can manage them successfully. When considering the conditions the backend substrate, and therefore the tape, has to endure it is wise to understand how the tape would be behave. For such an established process step as singulation, it can be surprising how many variables there still are when considering the tapes available. This is a reflection of the breadth of device types now being fabricated across the industry. Table 1, below, shows a variety of the tape materials used and some of their properties. Table 1 Examples of tapes used for dicing applications From the considerable range of samples processed it is clear that the tape does not affect the silicon etch performance. All aspects, including clamp, declamp and the etch itself, can be carried out irrespective of the tape used to mount the wafer. This is a very positive indictment of the approach taken in the engineering of the Rapier-S that, in effect, that plasma etch for dicing has been normalized and is a true parallel to silicon etch for MEMS or advanced packaging applications. Figure 12 Example of die singulated with plasma etch; lane defined by laser and blade SUMMARY The work described above is a snapshot of the effort being put together to integrate a frontend technology to a critical backend function. It is clear, however, that DRIE is already a viable and available option for wafer singulation. Some aspects of the tasks necessary for the integration of DRIE into the backend do require additional steps in the main flow to accommodate it. However, schemes have also been suggested which make use of the conventional dicing technologies in combination with DRIE bringing together the best of all. Finally, it is still early in the adoption cycle for DRIE but the basis for future work has been laid down. ACKNOWLEDGMENTS I would like to thank Oliver Ansell, Joanne Carpenter and Will Worster, all of SPTS, for their efforts in the dicing processing and analysis. I would also like to acknowledge the support and collaboration of DISCO in generating some of the data included in this paper. REFERENCES (1) Laermer, F, Schlip A, Method of anisotropically etching silicon. US Patent (2) D.M.Haynes, B.Khamsehpour, H.Ashraf, J.Hopkins, J.K.Bhardwaj, A.M.Hynes, M.E.Ryan Patent No. US , (3) A.M.Hynes, H.Ashraf, J.K.Bhardwaj, J.Hopkins, I.Johnston, J.N.Shepherd Sens.Actuators, 74, 13, (4) Barnett, R, et al, A New Plasma Source for Next Generation MEMS Deep Si Etching, 60th Electronic Components and Technology Conference, Las Vegas, NV, June 2010, pp (5) Barnett, R, et al, Yield and productivity improvements through use of advanced dual plasma source for TSV reveal &wafer dicing applications, 13th Electronics Packaging Technology Conference, Singapore, December 2011, pp (6) Ansell, O, et al Claritas TM A Unique And Robust Endpoint Technology For Silicon Drie Processes With Open Area Down To 0.05%, To Be Published at 27th IEEE Conference on Micro Electro Mechanical Systems (MEMS 2014), San Francisco CA, January (7) Barnett, R. ; SPTS Technol. Ltd., ; Ansell, O. ; Thomas, D. Considerations and benefits of plasma etch based wafer dicing, Electronics Packaging Technology Conference (EPTC 2013), 2013 IEEE 15 th pp Copyright 2015 by ASME

Plasma dicing 300mm framed wafers - Analysis of improvement in die strength and cost benefits for thin die singulation

2017 IEEE 67th Electronic Components and Technology Conference Plasma dicing 300mm framed wafers - Analysis of improvement in die strength and cost benefits for thin die singulation Richard Barnett SPTS