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1 9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) info@systemplus.fr - website : January 2012 Written by: Maher SAHMIMI DISCLAIMER : System Plus Consulting provides cost studies based on its knowledge of the manufacturing and selling prices of electronic components and systems. The given values are realistic estimates which do not bind System Plus Consulting nor the manufacturers quoted in the report. System Plus Consulting is in no case responsible for the consequences related to the use which is made of the contents of this report. The quoted trademarks are property of their owners by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 1

2 Glossary 1. Overview / Introduction Executive Summary Reverse Costing Methodology 2. Wispry Company Profile Wispry Profile Wispry Business Model 3. Samsung Focus FlashTeardown Physical Analysis Synthesis of the Physical Analysis Physical Analysis Methodology Package X-Ray Device Structure Die Dimensions Die Markings Die Bond Pads Die- Fonctions Package Cross-Section ASIC Cross-Section ASIC Process Characteristics MEMS Interconnect Cross Section MEMS Beam Cross Section MEMS Cap Cross Section MEMS Bumping Physical Data Summary Table of Contents 5. Manufacturing Process Flow Global Overview ASIC & MEMS Process Flow Description of the Wafer Fabrication Unit MEMS Sensor Process Flow Description of the MEMS Wafer Bumping Fabrication Unit MEMS Wafer Bumping Process Flow 6. Cost Analysis Synthesis of the Cost Analysis Main Steps of Economic Analysis Yields Explanation Yields Hypotheses Die per wafer & Probe Test ASIC Front-End : Hypotheses ASIC Front-End Cost MEMS Front-End : Hypotheses MEMS Front-End Cost MEMS Front-End Cost per Process Steps MEMS Front-End : Equipment Cost per Family MEMS Back-End 0 : Bumping & Probe Test & Dicing MEMS Die Cost (Front End + Back End 0) Back-End 1 : Packaging Cost Back-End 1 : Final test Cost Component Cost (FE + BE 0 + BE 1) 7. Estimated Price Analysis Definition of Prices Manufacturer Financial Ratios Estimated Manufacturer Price Estimated Selling Price Contact by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 2

35mm PCB ( 4 metal layer) The Package marking includes: Via in the PCB substrate A 2101

3 3.6mm Package Characteristics & Markings Package type: Dimensions: Pin pitch: Substrate: 22-pin FCBGA 4.2mm x 3.6mm x 1mm 0.35mm PCB ( 4 metal layer) The Package marking includes: Via in the PCB substrate A 2101 AC1140AA ORLTB-17 1 Package Top view 4.2mm 1mm Package side view Package Back view 2011 by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 3

Die - Dimensions Die, Optical view 2011 by SYSTEM PLUS

The top layer is a polyimide deposited during the step of wafer bumping.

5 Die SEM View Cap layer Die SEM view A Cap layer protects the MEMS beam. The cap is manufactured by deposition of a thick layer of silicon dioxide. The top layer is a polyimide deposited during the step of wafer bumping. Oxide layer MEMS beam Polyimide layer Die SEM view 2011 by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 5

Copper Metal Layer ASIC ASIC Cross Section 2011 by SYSTEM

6 ASIC Cross section MEMS InterConnect Al Metal Layers Number of ASIC Metal Layers : 4 (3 Aluminum, 1 Copper) Copper Metal Layer ASIC ASIC Cross Section 2011 by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 6

MEMS Metal 3 Layer MEMS Bump Cross Section MEMS Bump Cross Section 2011

7 MEMS Bump Cross section Underfill PCB Metal Layer Bump :Sn-Ag-Cu MEMS Cap Copper Layer MEMS interconnect Polyimid SiN ASIC Die Oxide Oxide MEMS Metal 3 Layer MEMS Bump Cross Section MEMS Bump Cross Section 2011 by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 7

Deposit & Pattern oxide Tungsten Plug Al Metal Layer 1 CMOS wafer Deposit and pattern Al

8 MEMS Process Flow 1/4 Tungsten Plug CMOS wafer First insulation Tungsten Plug ASIC Metalization CMOS wafer Damascene process Copper Oxide Tungsten Plug Oxide CMOS wafer Deposit & Pattern oxide Tungsten Plug Al Metal Layer 1 CMOS wafer Deposit and pattern Al Metal layer by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 8

9 MEMS Die Cost (Front-End + Back-End 0) The Die cost ranges from $xxx to $xxx according to yield variations. The Front-end cost (raw Si substrates, CMOS wafer processing, MEMS wafer processing) represents around xx% of the total wafer cost by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 9

Conclusion Reverse costing analysis represents the best cost/price evaluation given the publically available data, completed with industry expert estimates.

10 Conclusion Reverse costing analysis represents the best cost/price evaluation given the publically available data, completed with industry expert estimates. Given the hypothesis presented in this analysis the major sources of correction would lead to a +/- 10% correction on the manufacturing cost (if all parameters are cumulated) IC +/- 8% MEMS +/- 5% Packaging +/- 10% Test +/- 20% These results are open for discussion. We can re-evaluate this circuit with your information. Please contact us: 2011 by SYSTEM PLUS CONSULTING, all rights reserved. Wispry RF MEMS Antenna Tuner 10

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website :

9 rue Alfred Kastler - BP Nantes Cedex 3 - France Phone : +33 (0) website : 9 rue Alfred Kastler - BP 10748-44307 Nantes Cedex 3 - France Phone : +33 (0) 240 180 916 - email : info@systemplus.fr - website : www.systemplus.fr March 2011 - Version 1 Written by: Romain FRAUX DISCLAIMER