TYPICAL APPLICATION. LTC1595/LTC1596/LTC Serial 16-Bit Multiplying DACs DESCRIPTION FEATURES APPLICATIONS

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1 LTC9/LTC9/LTC9- Serial -Bit Multiplying DACs FEATRES SO- Package (LTC9) DNL and INL: LSB Max Low Glitch Impulse: nv-s Typ Fast Settling to LSB: µs (with LT) Pin Compatible with Industry Standard -Bit DACs: DAC and DAC/AD -Quadrant Multiplication Low Supply Current: µa Max Power-On Reset LTC9/LTC9: Resets to Zero Scale LTC9-: Resets to Midscale -Wire SPI and MICROWIRE TM Compatible Serial Interface Daisy-Chain Serial Output (LTC9) Asynchronous Clear Input LTC9: Clears to Zero Scale LTC9-: Clears to Midscale APPLICATIONS Process Control and Industrial Automation Software Controlled Gain Adjustment Digitally Controlled Filter and Power Supplies Automatic Test Equipment DESCRIPTION The LTC 9/LTC9/LTC9- are serial input, -bit multiplying current output DACs. The LTC9 is pin and hardware compatible with the -bit DAC and comes in -pin PDIP and SO packages. The LTC9 is pin and hardware compatible with the -bit DAC/AD and comes in -pin PDIP and SO wide packages. Both are specified over the industrial temperature range. Sensitivity of INL to op amp V OS is reduced by five times compared to the industry standard -bit DACs, so most systems can be easily upgraded to true -bit resolution and linearity without requiring more precise op amps. These DACs include an internal deglitching circuit that reduces the glitch impulse by more than ten times to less than nv-s typ. The DACs have a clear input and a power-on reset. The LTC9 and LTC9 reset to zero scale. The LTC9- is a version of the LTC9 that resets to midscale., LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. TYPICAL APPLICATION SO- Multiplying -Bit DAC Has Easy -Wire Serial Interface Integral Nonlinearity V IN V.. CLOCK DATA LOAD LD R FB LTC9 GND OT pf + LT V OT 9/9 TA INTEGRAL NONLINEARITY (LSB) DIGITAL INPT CODE 9/9 TA

2 LTC9/LTC9/LTC9- ABSOLTE MAXIMM RATINGS W W W to AGND....V to V to DGND....V to V AGND to DGND... +.V DGND to AGND... +.V to AGND, DGND... ±V R FB to AGND, DGND... ±V Digital Inputs to DGND....V to ( +.V) (Note ) V OT, V OT to AGND....V to ( +.V) Maximum Junction Temperature... C Operating Temperature Range LTC9C/LTC9C/LTC9-C... C to C LTC9I/LTC9I/LTC9-I... C to C Storage Temperature Range... C to C Lead Temperature (Soldering, sec)... C PACKAGE/ORDER I FOR W ATIO TOP VIEW TOP VIEW OT R FB R FB OT OT AGND GND LD STB CLR N PACKAGE -LEAD PDIP S PACKAGE -LEAD PLASTIC SO T JMAX = C, θ JA = C/W (N) T JMAX = C, θ JA = 9 C/W (S) LD SRO STB 9 DGND STB STB LD ORDER PART NMBER N PACKAGE -LEAD PDIP SW PACKAGE -LEAD PLASTIC SO WIDE LTC9ACN LTC9ACS LTC9BCN LTC9BCS LTC9CCN LTC9CCS LTC9AIN LTC9AIS LTC9BIN LTC9BIS LTC9CIN LTC9CIS S PART MARKING 9A 9B 9C 9AI 9BI 9CI LTC9ACN LTC9ACSW LTC9BCN LTC9BCSW LTC9CCN LTC9CCSW T JMAX = C, θ JA = C/W (N) T JMAX = C, θ JA = C/W (SW) ORDER PART NMBER LTC9AIN LTC9AISW LTC9BIN LTC9BISW LTC9CIN LTC9CISW LTC9-ACN LTC9-ACSW LTC9-BCN LTC9-BCSW LTC9-CCN LTC9-CCSW LTC9-AIN LTC9-AISW LTC9-BIN LTC9-BISW LTC9-CIN LTC9-CISW Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS = V ±%, = V, V OT = V OT = AGND = V, T A = T MIN to T MAX, unless otherwise noted. LTC9A/9A/9-A LTC9B/9B/9-B LTC9C/9C/9-C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX NITS Accuracy Resolution Bits Monotonicity Bits INL Integral Nonlinearity (Note ) T A = C ±. ± ± ± LSB T MIN to T MAX ±. ± ± ± LSB

3 ELECTRICAL CHARACTERISTICS = V ±%, = V, V OT = V OT = AGND = V, T A = T MIN to T MAX, unless otherwise noted. LTC9/LTC9/LTC9- LTC9A/9A/9-A LTC9B/9B/9-B LTC9C/9C/9-C SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX NITS DNL Differential T A = C ±. ± ± ± LSB Nonlinearity T MIN to T MAX ±. ± ± ± LSB GE Gain Error (Note ) T A = C ± ± ± LSB T MIN to T MAX ± ± ± LSB = V ±%, = V, V OT = V OT = AGND = V, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Gain Temperature Coefficient (Note ) Gain/ Temperature ppm/ C I LEAKAGE OT Leakage Current (Note ) T A = C ± na T MIN to T MAX ± na Zero-Scale Error T A = C ±. LSB T MIN to T MAX ± LSB PSRR Power Supply Rejection = V ±% ± ± LSB/V Reference Input R REF Input Resistance (Note ) kω AC Performance Output Current Settling Time (Notes, ) µs Mid-Scale Glitch Impulse sing LT Op Amp, C FEEDBACK = pf nv-s Digital-to-Analog Glitch Impulse Full-Scale Transition, = V, nv-s sing LT Op Amp, C FEEDBACK = pf Multiplying Feedthrough Error = ±V, khz Sine Wave mv P-P THD Total Harmonic Distortion (Note 9) db Equivalent DAC Thermal Noise (Note ) f = khz nv/ Hz Voltage Density Analog Outputs (Note ) C OT Output Capacitance (Note ) DAC Register Loaded to All s C OT pf DAC Register Loaded to All s C OT pf Digital Inputs V IH Digital Input High Voltage. V V IL Digital Input Low Voltage. V I IN Digital Input Current. ± µa C IN Digital Input Capacitance (Note ) V IN = V pf Digital Outputs: SRO (LTC9/LTC9-) V OH Digital Output High Voltage I OH = µa V V OL Digital Output Low Voltage I OL =.ma. V = V ±%, = V, V OT = GND = V, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Timing Characteristics (LTC9) t DS Serial Input to Setup Time ns t DH Serial Input to Hold Time ns

4 LTC9/LTC9/LTC9- ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS t Serial Input Data Pulse Width ns t CH Clock Pulse Width High ns t CL Clock Pulse Width Low ns t LD Load Pulse Width ns t ASB LSB Clocked into Input Register ns to DAC Register Load Time = V ±%, = V, V OT = V OT = AGND = V, T A = T MIN to T MAX, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Timing Characteristics (LTC9/LTC9-) t DS Serial Input to Strobe Setup Time STB sed as the Strobe ns t DS STB sed as the Strobe ns t DS STB sed as the Strobe ns t DS STB sed as the Strobe ns t DH Serial Input to Strobe Hold Time STB sed as the Strobe ns t DH STB sed as the Strobe ns t DH STB sed as the Strobe ns t DH STB sed as the Strobe ns t Serial Input Data Pulse Width ns t STB to Strobe Pulse Width (Note ) ns t STB t STB to Strobe Pulse Width (Note ) ns t STB t LD, t LD LD Pulse Width ns t ASB LSB Strobed into Input Register ns to Load DAC Register Time t CLR Clear Pulse Width ns t PD STB to SRO Propagation Delay C L = pf ns t PD STB, STB, STB to SRO C L = pf ns Propagation Delay Power Supply Supply Voltage.. V I DD Supply Current Digital Inputs = V or. µa The denotes specifications which apply over the full operating temperature range. Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : ±LSB = ±.% of full scale = ±.ppm of full scale. Note : sing internal feedback resistor. Note : Guaranteed by design, not subject to test. Note : I OT with DAC register loaded with all s. Note : Typical temperature coefficient is ppm/c. Note : OT load = Ω in parallel with pf. Note : To.% for a full-scale change, measured from the falling edge of LD, LD or LD. Note 9: = V RMS at khz. DAC register loaded with all s; op amp = LT. Note : Calculation from e n = ktrb where: k = Boltzmann constant (J/ K); R = resistance (Ω); T = temperature ( K); B = bandwidth (Hz). Note : Minimum high time for STB, STB, STB. Minimum low time for STB. Note : Minimum low time for STB, STB, STB. Minimum high time for STB.

5 TYPICAL PERFOR A CE CHARACTERISTICS W LTC9/LTC9/LTC9- OTPT VOLTAGE (mv) + Mid-Scale Glitch Inpulse nv-s TYP SING LT OP AMP C FEEDBACK = pf = V LD FALLING EDGE TIME (µs) 9/9 G INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity (INL).. 9 DIGITAL INPT CODE 9/9 TA DIFFERENTIAL NONLINEARITY (LSB) Differential Nonlinearity (INL). 9 DIGITAL INPT CODE 9/9 G DAC OTPT V/DIV GATED SETTLING WAVEFORM µv/div Full-Scale Settling Waveform SING LT OP AMP C FEEDBACK = pf µs/div 9/9 G INTEGRAL NONLINEARITY (LSB).. Integral Nonlinearity vs Reference Voltage DIFFERENTIAL NONLINEARITY (LSB).. Differential Nonlinearity vs Reference Voltage REFERENCE VOLTAGE (V) REFERENCE VOLTAGE (V) 9/9 G 9/9 G ATTENATION (db) Multiplying Mode Frequency Response vs Digital Code D D D D D D D9 D D D D D D D D D ALL BITS OFF ALL BITS ON SING LT OP AMP C FEEDBACK = pf k k k M M FREQENCY (Hz) INTEGRAL NONLINEARITY (LSB) Integral Nonlinearity vs Supply Voltage = V =.V 9 SPPLY VOLTAGE (V) DIFFERENTIAL NONLINEARITY (LSB).. Differential Nonlinearity vs Supply Voltage 9 SPPLY VOLTAGE (V) 9/9 G 9/9 G 9/9 G9

6 LTC9/LTC9/LTC9- TYPICAL PERFOR A CE CHARACTERISTICS SPPLY CRRENT (ma) W Supply Current vs Logic Input Voltage = V INPT VOLTAGE (V) LOGIC THRESHOLD (V) Logic Threshold vs Supply Voltage 9 SPPLY VOLTAGE (V) 9/9 G 9/9 G PIN FNCTIONS LTC9 (Pin ): Reference Input. R FB (Pin ): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp. OT (Pin ): Current Output Pin. Tie to inverting input of current to voltage converter op amp. GND (Pin ): Ground Pin. LD (Pin ): The Serial Interface Load Control Input. When LD is pulled low, data is loaded from the shift register into the DAC register, updating the DAC output. (Pin ): The Serial Data Input. Data on the pin is latched into the shift register on the rising edge of the serial clock. Data is loaded MSB first. (Pin ): The Serial Interface Clock Input. (Pin ): The Positive Supply Input..V.V. Requires a bypass capacitor to ground. LTC9/LTC9- OT (Pin ): True Current Output Pin. Tie to inverting input of current to voltage converter op amp. OT (Pin ): Complement Current Output Pin. Tie to analog ground. AGND (Pin ): Analog Ground Pin. STB, STB, STB, STB (Pins,,, ): Serial Interface Clock Inputs. STB, STB and STB are rising edge triggered inputs. STB is a falling edge triggered input (see Truth Tables). LD, LD (Pins, 9): Serial Interface Load Control Inputs. When LD and LD are pulled low, data is loaded from the shift register into the DAC register, updating the DAC output (see Truth Tables). SRO (Pin ): The Output of the Shift Register. Becomes valid on the active edge of the serial clock. (Pin ): The Serial Data Input. Data on the pin is latched into the shift register on the active edge of the serial clock. Data is loaded MSB first. DGND (Pin ): Digital Ground Pin. CLR (Pin ): The Clear Pin for the DAC. Clears DAC to zero scale when pulled low on LTC9. Clears DAC to midscale when pulled low on LTC9-. This pin should be tied to for normal operation. (Pin ): The Positive Supply Input..V.V. Requires a bypass capacitor to ground. (Pin ): Reference Input. R FB (Pin ): Feedback Resistor. Normally tied to the output of the current to voltage converter op amp.

7 LTC9/LTC9/LTC9- TRTH TABLES Table. LTC9/LTC9- Input Register CONTROL INPTS STB STB STB STB Input Register and SRO Operation Serial Data Bit on Loaded into Input Register, MSB First Data Bit or Appears on SRO Pin After Clocked Bits X X X No Input Register Operation X X X No SRO Operation X X X X X X Table. LTC9/LTC9- DAC Register CONTROL INPTS CLR LD LD DAC Register Operation X X Reset DAC Register and Input Register to All s (LTC9) or to Midscale (LTC9-) (Asynchronous Operation) X No DAC Register Operation X Load DAC Register with the Contents of Input Register BLOCK DIAGRA W (LTC9) R FB k k k k k OT GND DECODER LD LOAD D (MSB) D D D D D (LSB) DAC REGISTER INPT -BIT SHIFT REGISTER IN 9 BD W TI I G DIAGRA (LTC9) t DS t DH W INPT t CL t t CH PREVIOS WORD D MSB D D D LSB t ASB LD t LD 9 TD

8 LTC9/LTC9/LTC9- BLOCK DIAGRA W (LTC9/LTC9-) R FB k k k k k OT OT DECODER AGND CLR LD LD 9 CLR LOAD D (MSB) D D D D D (LSB) DAC REGISTER STB STB STB CLR OT INPT -BIT SHIFT REGISTER IN 9 BD STB SRO DGND W TI I G DIAGRA W (LTC9/LTC9-) STROBE INPT STB, STB, STB (INVERT FOR STB) t DS t DH t DS t DH t DS t DH t DS t DH t STB t STB t STB t STB tstb t STB t STB t STB D MSB D D D D LSB t t ASB LD, LD t LD t LD t PD t PD SRO D (MSB) PREVIOS WORD D PREVIOS WORD D PREVIOS WORD D (LSB) PREVIOS WORD D (MSB) CRRENT WORD 9 TD

9 LTC9/LTC9/LTC9- APPLICATIONS INFORMATION Description W The LTC9/LTC9 are -bit multiplying DACs which have serial inputs and current outputs. They use precision R/R technology to provide exceptional linearity and stability. The devices operate from a single V supply and provide ±V reference input and voltage output ranges when used with an external op amp. These devices have a proprietary deglitcher that reduces glitch impulse to nv-s over a V to V output range. Serial I/O The LTC9/LTC9 have SPI/MICROWIRE compatible serial ports that accept -bit serial words. Data is accepted MSB first and loaded with a load pin. The -pin LTC9 has a -wire interface. Data is shifted into the data input on the rising edge of the pin. At the end of the data transfer, data is loaded into the DAC register by pulling the LD pin low (see LTC9 Timing Diagram). V TO V V The -pin LTC9 can operate in identical fashion to the LTC9 but offers additional pins for flexibility. Four clock pins are available STB, STB, STB and STB. STB, STB and STB operate like the pin of the LTC9, capturing data on their rising edges. STB captures data on its falling edge (see Truth Table ). The LTC9 has two load pins, LD and LD. To load data, both pins must be taken low. If one of the pins is grounded, the other pin will operate identically to LTC9 s LD pin. An asynchronous clear input (CLR) resets the LTC9 to zero scale (and the LTC9- to midscale) when pulled low (see Truth Table ). The LTC9 also has a data output pin SRO that can be connected to the input of another DAC to daisy-chain multiple DACs on one -wire interface (see LTC9 Timing Diagram). nipolar (-Quadrant Multiplying) Mode (V OT = V to ) The LTC9/LTC9 can be used with a single op amp to provide -quadrant multiplying operation as shown in Figure. With a fixed V reference, the circuits shown give a precision unipolar V to V output swing. µp.µf TO NEXT DAC FOR DAISY-CHAINING 9 CLR STB STB LD SRO LD STB STB LTC9 DGND R FB AGND OT OT pf 9/9 Fa + LT V OT V TO µp V.µF LD R FB LTC9 V TO V GND OT (b) pf + LT 9/9 Fb V OT V TO (a) Table. nipolar Binary Code Table MSB DIGITAL INPT BINARY NMBER IN DAC REGISTER LSB Figure. nipolar Operation (-Quadrant Multiplication) V OT = V to V REF ANALOG OTPT V OT (,/,) (,/,) = / (/,) V 9

10 LTC9/LTC9/LTC9- APPLICATIONS INFORMATION W Bipolar (-Quadrant Multiplying) Mode (V OT = to ) The LTC9/LTC9 can be used with a dual op amp and three external resistors to provide -quadrant multiplying operation as shown in Figure (last page). With a fixed V reference, the circuits shown give a precision bipolar V to V output swing. sing the LTC9- will cause the power-on reset and clear pin to reset the DAC to midscale (bipolar zero). Op Amp Selection Because of the extremely high accuracy of the -bit LTC9/LTC9, thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Op amp offset will contribute mostly to output offset and gain and will have minimal effect on INL and DNL. For example, a µv op amp offset will cause about.lsb INL degradation and.lsb DNL degradation with a V full-scale range. The main effects of op amp offset will be a degradation of zero-scale error equal to the op amp offset, and a degradation of full-scale error equal to twice the op amp offset. For example, the same µv op amp offset will cause a.lsb zero-scale error and a.lsb full-scale error with a V full-scale range. Op amp input bias current (I BIAS ) contributes only a zeroscale error equal to I BIAS (R FB ) = I BIAS (R REF ) = I BIAS (k). Table shows a selection of LTC op amps which are suitable for use with the LTC9/LTC9. For a thorough discussion of -bit DAC settling time and op amp selection, refer to Application Note, Component and Measurement Advances Ensure -Bit DAC Settling Time. Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding should be used. I OT (LTC9) and GND (LTC9) must be tied to the star ground with as low a resistance as possible. Table. -Bit Settling Time for Various Amplifiers Driven by the LT9 DAC. LT (Shaded) Offers Fastest Settling Time While Maintaining Accuracy Over Temperature CONSERVATIVE SETTLING TIME AMPLIFIER AND COMPENSATION VALE COMMENTS LT µs pf Good Low Speed Choice LT 9µs pf I B Gives LSB Error at C LT µs pf LSB Error Due to V OS over Temperature LT µs pf LT9 µs pf Good Low Speed Choice LT µs pf Good Low Speed Choice Dual LT µs pf Low Power Dual LT.µs pf Fastest Settling with -Bit Performance

11 LTC9/LTC9/LTC9- PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. N Package -Lead PDIP (Narrow.) (LTC DWG # --).. (..).. (..). ±. (. ±.).* (.) MAX.9. (.9.) ( ). (.) TYP. ±. (. ±.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) MIN. ±. (. ±.). (.) MIN. ±.* (. ±.) N 9 S Package -Lead Plastic Small Outline (Narrow.) (LTC DWG # --).9.9* (..).. (..).. (..) TYP..9 (..).. (..) (..) *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..). (.) TYP.. (.9.9) N Package -Lead PDIP (Narrow.) (LTC DWG # --). ±. (. ±.).. (..).* (9.) MAX..** (..9) SO (.9.) ( ). (.) MIN. (.) MIN. ±. (. ±.) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED. INCH (.mm). (.) TYP. ±. (. ±.). ±.* (. ±.) N 9 SW Package -Lead Plastic Small Outline (Wide.) (LTC DWG # --).9.99** (.9.9)..9 (..).9. (..).. (.9.).9.* (.9.9) 9 TYP.9. (.9.). (.) TYP..9 (..) TYP NOTE.. (..) NOTE:. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS.. (..) *DIMENSION DOES NOT INCLDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED." (.mm) PER SIDE ** DIMENSION DOES NOT INCLDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE NOTE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights..9.9 (..) S (WIDE) 9

12 LTC9/LTC9/LTC9- TYPICAL APPLICATIONS V TO V V R k R k µp.µf TO NEXT DAC FOR DAISY-CHAINING STB CLR STB LD SRO 9 LD STB STB LTC9- DGND R FB AGND OT OT (a) pf / LT + 9/9 Fa R k (k ) / LT + V OT TO RESISTORS: CADDOCK T9-K-- (OR EQIVALENT) k,.%, TC TRACK = ppm/ C µp V TO V V.µF R FB LTC9 OT LD GND R k pf / LT + (b) R k (k ) R k / LT + 9/9 Fb V OT TO Table. Bipolar Offset Binary Code Table DIGITAL INPT BINARY NMBER IN DAC REGISTER MSB LSB ANALOG OTPT V OT (,/,) (/,) V (/,) Figure. Bipolar Operation (-Quadrant Multiplication) V OT = to RELATED PARTS PART NMBER DESCRIPTION COMMENTS DACs LTC9 Dual Serial I/O Multiplying I OT -Bit DAC -Pin SO and PDIP, SPI Interface LTC9 Parallel -Bit Current Output DAC Low Glitch, ±LSB Maximum INL, DNL LTC Serial -Bit Voltage Output DAC Low Noise and Glitch Rail-to-Rail V OT LTC Serial -Bit Voltage Output DAC Low Power, -Lead MSOP Rail-to-Rail V OT LTC/LTC/LTC Serial I/O Multiplying I OT -Bit DACs Clear Pin and Serial Data Output (LTC) ADCs LTC -Bit, ksps V Sampling ADC mw Dissipation, Serial and Parallel Outputs LTC -Bit, ksps Sampling ADC ±.V Input, SINAD = 9dB, THD = db LTC Single V, -Bit ksps ADC Low Power, ±V Inputs LTC -Bit, ADC in SO- ppm (ppm) Offset (Full Scale), Internal Hz/Hz Notches Op Amps LT Precision Operational Amplifier Low Offset, Low Drift LT Dual Low Power, Precision Picoamp Input Op Amp Low Offset, Low Drift LT 9MHz, V/µs, -Bit Accurate Op Amp Precise, µs Settling to.% References LT Precision Reference ltralow Drift, ppm/ C, High Accuracy.% LT Micropower Reference ltralow Drift, ppm/ C, High Accuracy.% Linear Technology Corporation McCarthy Blvd., Milpitas, CA 9- () -9 FAX: () - 9fa LT/TP 99 K REV A PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 99