A few questions to test your familiarity of Lab7 at the end of finishing all assigned parts of Lab 7

Transcription

1 EE457 Lab7 Questions page A few questions to test your familiarity of Lab7 at the end of finishing all assigned parts of Lab 7 1. A. In which parts or subparts of Lab 7 does the STALL signal cause the entire pipeline to be stalled? (Part 1, Part 2, P3_SP1, P3_SP2, P3_SP3, P3_SP4) 1. B. In which parts or subparts of Lab 7 does the STALL signal cause only part of the pipeline to be stalled? (Part 1, Part 2, P3_SP1, P3_SP2, P3_SP3, P3_SP4) 1. C. Are both of the above stall signals initiated by RAW dependencies that cannot be solved by forwarding or is it that in some of the Lab 7 designs there are no RAW dependencies that cannot be solved by forwarding? If so, why are you stalling in those cases? 2. In our Lab 6, both HDU and HDU_Br are in the ID stage. Miss (Bruin/Trojan) says that the HDU [unlike the HDU_Br who serves the Branch instruction (that insists on receiving all forwarding help in ID stage)] can be moved to EX stage. 3. A. The STALL of Q#1.A. above happens in (RF/EX1/EX2/EX12/EX2WB) stage in our design. Note that the ID stage of the CPU pipeline is called RF stage here as there is no instruction decoding in Lab7 because of one hot coding of its opcodes. We just fetch the source registers here and hence it is called the Register Fetch (RF) stage. The stall cannot be moved to take place in any other stage. T / F If you answered False, state to which stage (or stages) it can be moved to. If you answered True, state why it cannot be moved. 3. B. The STALL of Q#1.B. above happens in (RF/EX1/EX2/EX12/EX2WB) stage in our design. The stall cannot be moved to take place in any other stage. T / F / It depends Explain. 4. Unlike in our Lab 6, there is no need to have a Wrist Band Flip Flop (WB_FF) in any part of the Lab 7. T / F Explain your answer.

2 Please look at the solution only after you mentally answered all the questions.

3 EE457 Lab7 Answers page 1. A. In which parts or subparts of Lab 7 does the STALL signal cause the entire pipeline to be stalled? (Part 1, Part 2, P3_SP1, P3_SP2, P3_SP3, P3_SP4) Note: In part 2 we assumed that the clock is wide enough to combine EX2 and WB into EX2WB. 1. B. In which parts or subparts of Lab 7 does the STALL signal cause only part of the pipeline to be stalled? (Part 1, Part 2, P3_SP1, P3_SP2, P3_SP3, P3_SP4) 1. C. Are both of the above stall signals initiated by RAW dependencies that cannot be solved by forwarding or is it that in some of the Lab 7 designs there are no RAW dependencies that cannot be solved by forwarding? If so, why are you stalling in those cases? In P3_SP2 and P3_SP4, there are no RAW dependencies that cannot be solved by forwarding. We are stalling the entire pipeline for one clock when ADD1 comes into EX12 stage to allow it one clock extra time to do both SUB3 and ADD4 operations. Entire pipe needs to be stalled as we do not want the instruction in WB stage which could be helping the instruction in EX12 to leave the WB stage. Some students think that the help from the WB stage is needed only in the first clock when we subtract 4 from the source register (which may be dependent on the instruction in WB stage). They think that the addition of 4 to the result produced by the SUB3 does not need the help from the WB anymore. The fact is that the SUB3 is a combinational logic with some very quick paths and some very slow paths. If the WB instruction is allowed to leave, the help vanishes in the 2 nd clock and the garbage help (inappropriate help or no help) from the WB stage causes the SUB3 output to become invalid quickly through the short paths in the SUB3. The output pins of SUB3 (or for that matter any piece of combinational logic) cannot hold a data for a clock. So it is necessary that the senior in WB is stalled whenever EX12 is stalled. 2. In our Lab 6, both HDU and HDU_Br are in the ID stage. Miss (Bruin/Trojan) says that the HDU [unlike the HDU_Br who serves the Branch instruction (that insists on receiving all forwarding help in ID stage)] can be moved to EX stage. A multi source instruction such as the subu below dependent on the two seniors for its sources cannot be stalled in the EX stage as it cannot hold on the $3 help from Senior #2 (addu) until it received the $2 help from Senior #1 (lw) in the next clock. addu $3, $3, $3 lw $2, 40($8) subu $1, $2, $3

4 3. A. The STALL of Q#1.A. above happens in (RF/EX1/EX2/EX12/EX2WB) stage in our design. Note that the ID stage of the CPU pipeline is called RF stage here as there is no instruction decoding in Lab7 because of one hot coding of its opcodes. We just fetch the source registers here and hence it is called the Register Fetch (RF) stage. The stall cannot be moved to take place in any other stage. T / F If you answered False, state to which stage (or stages) it can be moved to. If you answered True, state why it cannot be moved. The ADD1 instruction needs extra time in EX12 but not in other stages. 3. B. The STALL of Q#1.B. above happens in (RF/EX1/EX2/EX12/EX2WB) stage in our design. The stall cannot be moved to take place in any other stage. T / F / It depends Explain. Lab 7 Parts 1 and 2 use instructions with multiple sources. Hence the stall should happen in the RF (the ID) stage only. It is for the same reason stated in the answer to question #2 above. But in the case of Lab 7 Part 3 Subparts #1 and #3, with a single source register, the stall can be made to happen in the EX1 stage instead of the RF (the ID) stage. In the case of a single source instruction, the question of receiving part of the help and holding on to it while waiting for the other part of the help does not arise. Performance wise, it does not matter whether you stall the dependent instruction in the RF (ID) stage or the EX1 stage. 4. Unlike in our Lab 6, there is no need to have a Wrist Band Flip Flop (WB_FF) in any part of the Lab 7. T / F Explain your answer. Unlike in the lab 6 IF/ID stage register, in all parts of lab #7 the IF/RF (the IF/ID) stage register has onehot control bits as the opcode itself is one hot coded and the 0000 opcode means a NOP. So just clearing the IF/RF register on reset will ensure that the RF stage has a bubble to start with. There is no need for a WB_FF. Some more detailed discussion about WB_FF in Lab 6 design: During system reset period, we want to make sure that all stages except for the IF stage are filled with bubbles. In Lab 6, the IF/ID stage register

5 has no control signals to clear using the /RESET signal. Hence we had to attach a Wrist Band FF (WB_FF). We either set or reset the WB_FF to mark the instruction in the ID stage as destined to be treated as a NOP (Bubble). Note that there is no opcode assigned for a NOP instruction in MIPS ISA. The opcode in MIPS is an R Type opcode. So clearing the IF/ID may or may not create a bubble. Actually it creates a bubble because it is an R type instruction with $0 as its destination. Extract from state.edu/~crawfis/cse675 02/Slides/MIPS%20Instruction%20Set.pdf However imagine the 7 stage pipeline where we have IF1/IF2 stage register besides IF2/ID stage register. Here we need a WB_FF at least associated with the IF1/IF2. So in EE457 we introduced the idea of WB_FF starting from the 5 stage pipeline itself.