FTT1010-M Philips Semiconductors

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1 IMAGE SENSORS FTTM 999 September File under Image Sensors Philips Semiconductors TRAD

FTTM inch optical format M active pixels ( x ) Progressive scan Excellent antiblooming ariable electronic shuttering Square pixel structure and binning % optical fill factor igh dynamic range (>7dB)

2 FTTM inch optical format M active pixels ( x ) Progressive scan Excellent antiblooming ariable electronic shuttering Square pixel structure and binning % optical fill factor igh dynamic range (>7dB) igh sensitivity ow dark current and fixed pattern noise ow readout noise Data rate up to x Mz Mirrored and split readout Description The FTT M is a monochrome progressivescan frametransfer image sensor offering K x K pixels at frames per second through a single output buffer. The combination of high speed and a high linear dynamic range (> true bits at room temperature without cooling) makes this device the perfect solution for highend real time medical Xray, scientific and industrial applications. A second output can either be used for mirrored images, or can be read out simultaneously with the other output to double the frame rate. The device structure is shown in figure. Device structure Optical size:.88 mm () x.88 mm () Chip size:.7 mm () x 6.8 mm () Pixel size: µm x µm Active pixels: () x () Total no. of pixels: 7 () x () Optical black pixels: eft: Right: Timing pixels: eft: Right: Dummy register cells: eft: 7 Right: 7 Optical black lines: Bottom: 6 Top: 6 Z 6 black lines Image Section active pixels active lines Y 6 lines Storage Section Output amplifier W 6 black lines 7 7 cells 7 Output register X Figure Device structure 999 September

3 FTTM Architecture of the FTTM The FTTM consists of a shielded storage section and an open image section. Both sections are electronically the same and have the same cell structure with the same properties. The only difference between the two sections is the optical light shield. The optical centres of all pixels in the image section form a square grid. The charge is generated and integrated in this section. Output registers are located below the storage section. The output amplifiers Y and Z are not used in Frame Transfer mode and should be connected as notused amplifiers. After the integration time the charge collected in the image section is shifted to the storage section. The charge is read out line by line through the lower output register. The left and the right half of each output register can be controlled independently. This enables either single or multiple readout. During vertical transport the C gates separate the pixels in the register. The letters W, X, Y and Z are used to define the four quadrants of the sensor. The central C gates of both registers are part of the W and Z quadrants of the sensor. Both upper and lower registers can be used for vertical binning. Both registers also have a summing gate at each end that can be used for horizontal binning. Figure shows the detailed internal structure. IMAGE SECTION Image diagonal (active video only) Aspect ratio Active image width x height Pixel width x height Geometric fill factor Image clock pins Capacity of each clock phase Number of active lines Number of black reference lines Number of dummy black lines Total number of lines Number of active pixels per line Number of overscan (timing) pixels per line Number of black reference pixels per line Total number of pixels per line 7.8 mm :.88 x.88 mm x µm % A,,,.nF per pin 8 (x) (x) 7 STORAGE SECTION Storage width x height Cell width x height Storage clock phases Capacity of each clock phase Number of cells per line Number of lines.86 x.6 mm x µm B,,,.nF per pin 7 OUTPUT REGISTERS Output buffers (threestage source follower) Number of registers Number of dummy cells per register Number of register cells per register Output register horizontal transport clock pins Capacity of each Cclock phase Overlap capacity between neighbouring Cclocks Output register Summing Gates Capacity of each SG Reset Gate clock phases Capacity of each (one on each corner) (one above, one below) (x7) 7 C, C, C 6pF per pin pf pins (SG) pf pins () pf 999 September

4 FTTM RD 7 dummy pixels black & timing columns K image pixels black & timing columns 7 dummy pixels RD SG C C C C C C OG C C C C C C C C C C C C C C C C C C C C C C C C C C C C C SG OG OUT_Z (not used) A A OUT_Y (not used) A 6 black lines A One Pixel A A K active images lines IMAGE A A B FT CCD B SG: summing gate OG: output gate : reset gate RD: reset drain A B B K storage lines STORAGE A B B B 6 black lines B OUT_W B B OUT_X OG SG C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C SG OG RD column column + column + K column + K + RD A,,, : clocks of image section B,,, : clocks of storage section C, C, C: clocks of horizontal registers Figure Detailed internal structure 999 September

5 FTTM Specifications ABSOUTE MAXIMUM RATINGS MIN. MAX. UNIT GENERA: storage temperature ambient temperature during operation voltage between any two gates DC current through any clock phase (absolute value) OUT current (no short circuit protection) C C µa ma OTAGES IN REATION TO PS: NS, SFD, RD CS, SFS all other pins OTAGES IN REATION TO NS: SFD, RD CS, SFS, PS all other pins NS PS SFD SFS CS OG RD N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain DC CONDITIONS MIN. [] TYPICA [] MAX. [] MAX. [ma] AC COCK EE CONDITIONS MIN. TYPICA MAX. UNIT IMAGE COCKS: Aclock amplitude during integration and hold Aclock amplitude during vertical transport (duty cycle=/8) Aclock low level Charge Reset (CR) level on Aclock 8 STORAGE COCKS: Bclock amplitude during hold Bclock amplitude during vertical transport (duty cycle=/8) 8 OUTPUT REGISTER COCKS: Cclock amplitude (duty cycle during hor. transport = /6) Cclock low level Summing Gate (SG) amplitude Summing Gate (SG) low level.7... OTER COCKS: Reset Gate () amplitude Reset Gate () low level Charge Reset (CR) pulse on Nsub During Charge Reset it is allowed to exceed maximum rating levels (see note ). All voltages in relation to SFS. To set the NS voltage for optimal ertical AntiBlooming (AB), it should be adjustable between minimum and maximum values. Threelevel clock is preferred for maximum charge; the swing during vertical transport should be higher than the voltage during integration. A two level clock (typically ) can be used if a lower maximum charge handling capacity is allowed. Charge Reset can be achieved in two ways: The typical CR level is applied to all image clocks simultaneously (preferred). The typical Aclock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on NS is required. This will also affect the charge handling capacity in the storage areas. 999 September

6 FTTM Timing diagrams (for default operation) AC CARACTERISTICS MIN. TYPICA MAX. UNIT orizontal frequency (/Tp) ertical frequency Charge Reset (CR) time Rise and fall times: image clocks (A) storage clocks (B) register clocks (C) summing gate (SG) reset gate () 8 /6 Tp /6 Tp /6 Tp Mz kz µs ns ns ns ns ns Tp = clock period Duty cycle = % and phase shift of the C clocks is degrees. ine Timing SSC B CR Aigh * D BC Tp Tp Tp 9Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Tp Pixel Timing SSC C C C SG Tp = clock period = / 8Mz =.6ns Pixel output sequence: 7 dummy, black, timing, active, timing, black * During Aigh = the phia high level is increased from to Tp 79 pixels Tp / 6 ine Time: 8 x Tp = 6.7µs D: Frame pulse CR: Charge Reset BC: Black evel Clamp B to : ertical storage clocks C to C: orizontal register clocks SSC: StartStop Cclocks SG: Summing gate : Reset gate Figure ine and pixel timing diagrams 999 September 6

7 FTTM Frame Timing Sensor Output 9 B B B B B Black SSC A,, B,, CR Ahigh * D BC EXT. SUTTER Frame Shift Timing Integration Time Frame Shift Tframe shift = 7 x 8 x N clock periods A B 8 phases correspond with line shifts orizontal freq. 8Mz N =, for example: = ertical freq. x 8 kz x 8 D: Frame pulse CR: Charge Reset BC: Black evel Clamp A to : ertical image clocks B to : ertical storage clocks C to C: orizontal register clocks SSC: StartStop Cclocks SG: Summing gate : Reset gate Figure Frame timing diagrams 999 September 7

8 FTTM ine timing SSC B > time Y / Div. : (B,,, ); (SSC) Figure ertical readout Pixel timing C C C SG > time Y / Div. : (C, C, C); (SG, ) Figure 6 Start horizontal readout 999 September 8

9 FTTM Performance The test conditions for the performance characteristics are as follows: All values are measured using typical operating conditions. NS is adjusted as low as possible while maintaining proper ertical AntiBlooming. Sensor temperature = 6 C (K). orizontal transport frequency = 8Mz. ertical transport frequency = kz (unless specified otherwise). Integration time = ms (unless specified otherwise). The light source is a K lamp with neutral density filters and a.7mm thick BG infrared cutoff filter. For inear Operation measurements, a temperature conversion filter (Melles Griot type no. FCG6, mired, thickness:.mm) is applied. INEAR OPERATION MIN. TYPICA MAX. UNIT inear dynamic range : Charge Transfer Efficiency vertical Charge Transfer Efficiency horizontal Image lag % Smear 9 db Resolution lp/mm 6 % Responsivity 8 kel/lux s Quantum nm % White Shading. % Random NonUniformity (RNU). % NS required for good ertical AntiBlooming (AB) 8 8 Power dissipation at frames/s mw inear dynamic range is defined as the ratio of Q lin to readout noise (the latter reduced by Correlated Double Sampling). Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer. Smear is defined as the ratio of % of the vertical transport time to the integration time. It indicates how visible a spot of % of the image height would become. White Shading is defined as the ratio of the oneσ value of the pixel output distribution expressed as a percentage of the mean value output (low pass image). RNU is defined as the ratio of the oneσ value of the highpass image to the mean signal value at nominal light. DR inear Dynamic Range, 8, ºC 6,, ºC, ºC, 8, 6,,, or. Frequency (Mz) Figure 7 Typical inear dynamic range vs. horizontal readout frequency and sensor temperature 999 September 9

10 FTTM 8 Maximum Readout Speed 7 outputs 6 Images/sec. output Integration time (ms) Figure 8 Maximum number of images/second versus integration time Quantum Efficiency Quantum efficiency (%) Wavelength (nm) Figure 9 Quantum efficiency versus wavelength 999 September

11 FTTM INEAR/SATURATION MIN. TYPICA MAX. UNIT Fullwell capacity saturation level (Qmax) 6 kel. Fullwell capacity shading (Qmax, shading) % Fullwell capacity linear operation (Qlin) kel. Charge handling capacity 6 kel. Overexposure handling x Qmax level Qmax is determined from the lowpass filtered image. Qmax, shading is the maximum difference of the fullwell charges of all pixels, relative to Qmax. The linear fullwell capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity. Charge handling capacity is the largest charge packet that can be transported through the register and readout through the output buffer. Overexposure over entire area while maintaining good ertical AntiBlooming (AB). It is tested by measuring the dark line. Charge andling vs. Integration/Transport oltage 6 / Output Signal (kel.) 9/ 8/ 6 Exposure (arbitrary units) Figure Charge handling versus integration/transport voltage 999 September

12 FTTM OUTPUT BUFFERS MIN. TYPICA MAX. UNIT Conversion factor 6 8 µ/el. Mutual conversion factor matching ( ACF) µ/el. Supply current ma Bandwidth Mz Output impedance buffer (R load =.kω, C load = pf) Ω Matching of the four outputs is specified as ACF with respect to reference measured at the operating point (Q lin /). DARK CONDITION MIN. TYPICA MAX. UNIT Dark current C pa/cm Dark current 6 C..6 na/cm Fixed Pattern Noise 6 C RMS readout 9Mz bandwidth after CDS el. el. FPN is the oneσ value of the highpass image. Dark Current Dark Current (pa/cm ) 6 Temp. ( o C) Figure Dark current versus temperature 999 September

13 FTTM Application information Current handling One of the purposes of PS is to drain the holes that are generated during exposure of the sensor to light. Free electrons are either transported to the RD connection and, if excessive (from overexposure), free electrons are drained to NS. No current should flow into any PS connection of the sensor. During high overexposure a total current to ma through all PS connections together may be expected. The PNP emitter follower in the circuit diagram (figure ) serves these current requirements. NS drains superfluous electrons as a result of overexposure. In other words, it only sinks current. During high overexposure a total current of to ma through all NS connections together may be expected. The NPN emitter follower in the circuit diagram meets these current requirements. The clamp circuit, consisting of the diode and electrolytic capacitor, enables the addition of a Charge Reset (CR) pulse on top of an otherwise stable NS voltage. To protect the CCD, the current resulting from this pulse should be limited. This can be accomplished by designing a pulse generator with a rather high output impedance. Decoupling of DC voltages All DC voltages (not NS, which has additional CR pulses as described above) should be decoupled with a nf decoupling capacitor. This capacitor must be mounted as close as possible to the sensor pin. Further noise reduction (by bandwidth limiting) is achieved by the resistors in the connections between the sensor and its voltage supplies. The electrons that build up the charge packets that will reach the floating diffusions only add up to a small current, which will flow through RD. Therefore a large series resistor in the RD connection may be used. Outputs To limit the onchip power dissipation, the output buffers are designed with open source outputs. Outputs to be used should therefore be loaded with a current source or more simply with a resistance to GND. In order to prevent the output (which typically has an output impedance of about Ω) from bandwidth limitation as a result of capacitive loading, load the output with an emitter follower built from a highfrequency transistor. Mount the base of this transistor as close as possible to the sensor and keep the connection between the emitter and the next stage short. The CCD output buffer can easily be destroyed by ESD. By using this emitter follower, this danger is suppressed; do NOT reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the emitter follower. Slew rate limitation is avoided by avoiding a toosmall quiescent current in the emitter follower; about ma should do the job. The collector of the emitter follower should be decoupled properly to suppress the Miller effect from the basecollector capacitance. A CCD output load resistor of.kω typically results in a bandwidth of Mz. The bandwidth can be enlarged to about Mz by using a resistor of.kω instead, which, however, also enlarges the onchip power dissipation. Device protection The output buffers of the FTTM are likely to be damaged if PS rises above SFD or RD at any time. This danger is most realistic during poweron or poweroff of the camera. The RD voltage should always be lower than the SFD voltage. Never exceed the maximum output current. This may damage the device permanently. The maximum output current should be limited to ma. Be especially aware that the output buffers of these image sensors are very sensitive to ESD damage. Because of the fact that our CCDs are built on an ntype substrate, we are dealing with some parasitic npn transistors. To avoid activation of these transistors during switchon and switchoff of the camera, we recommend the application diagram of figure. Unused sections To reduce power consumption the following steps can be taken. Connect unused output register pins (C...C, SG, OG) and unused SFS pins to zero olts. More information Detailed application information is provided in the application note AN entitled Camera Electronics for the mk x nk CCD Image Sensor Family. 999 September

14 FTTM Device andling An image sensor is a MOS device which can be destroyed by electrostatic discharge (ESD). Therefore, the device should be handled with care. Always store the device with shortcircuiting clamps or on conductive foam. Always switch off all electric signals when inserting or removing the sensor into or from a camera (the ESD protection in the CCD image sensor process is less effective than the ESD protection of standard CMOS circuits). Being a high quality optical device, it is important that the cover glass remain undamaged. When handling the sensor, use fingercots. When cleaning the glass we recommend using ethanol (or possibly water). Use of other liquids is strongly discouraged: if the cleaning liquid evaporates too quickly, rubbing is likely to cause ESD damage. the cover glass and its coating can be damaged by other liquids. Rub the window carefully and slowly. Dry rubbing of the window may cause electrostatic charges or scratches which can destroy the device. SFD.mA BC 8C.mA.mA BC 8C BC 86C 7 Ω nf BAT7 Schottky! Ω BAT7 Schottky! kω CR pulse BAT7 BAT7 + uf ma nf nf nf NS SFD PS RD OUT CS OG keep short <mm!.k Ω nf nf Ω kω kω BFR 9A output for preprocessing ma k Ω keep short! nf <7pF! Figure Application diagram to protect the FTTM 999 September

15 B Philips Semiconductors FTTM Pin configuration The FTTM is mounted in a Pin Grid Array (PGA) package with 76 pins in a x grid of. x. mm. The position of pin A is marked with a gold dot on top of the package. The clock phases of quadrant W are internally connected to X, and the clock phases of Y are connected to Z. Symbol Name Pin # W Pin # X Pin # Y Pin # Z NS NS NS NS NS PS SFD SFS CS OG RD A B C C C SG OUT NC N substrate N substrate N substrate N substrate N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain Image Clock (Phase ) Image Clock (Phase ) Image Clock (Phase ) Image Clock (Phase ) Storage Clock (Phase ) Storage Clock (Phase ) Storage Clock (Phase ) Storage Clock (Phase ) Register Clock (Phase ) Register Clock (Phase ) Register Clock (Phase ) Summing Gate Reset Gate Output Not connected D E E C A A D C D C B9 B8 A8 B A9 B B7 D E E C A B B D C D C A6 A7 B6 A J F G J J J F G F G 6 J6 J 7 F J G J 9 J F G F G J8 J7 8 J J J G F SFD SG NS CS OG NS RD OUT PS A NS SFS C C C NC TOP C C C SFS SG CS OUT PS NS NS RD SFD OG A J G F Z IMAGE Y W STORAGE B X E D C B A NS NS B NS PS FTTM NS NS PS NS B OG RD OUT SG C C NC C SFS OUT RD NS OG SFD NS CS SFS C C C CS NS SG SFD E D C B A Figure FTTM pin configuration (top view) 999 September

16 FTTM Package information Top cover glass to top chip. ±. Chip bottom package.7 ±. SENSOR CRYSTA Chip cover glass. ±. A ZONE Cover glass. ±. COER GASS ±. INDEX MARK PIN TOP IEW 6 ±. ±..7 ±. ±. 8.9 ±..7 ±. COER GASS Image sensor chip. / STANDOFF PIN (.).6 ±. BOTTOM IEW.8 ±. A is the center of the image area. Position of A: 6 ±. to left edge of package ±. to bottom of package Angle of rotation: less than ± Sensor flatness: < 7 µm (P) Cover glass: Corning 79 Thickness of cover glass:. ±. Refractive index: n d =. Single sided AR coating inside (66 nm).6 ±. All drawing units are in mm Figure Mechanical drawing of the PGA package of the FTTM 999 September 6

17 Order codes The sensors can be ordered using the following codes: You can contact the Image Sensors division of Philips Semiconductors at the following address: Philips Semiconductors Image Sensors Internal Postbox WAG Prof. olstlaan 66 AA Eindhoven The Netherlands phone + 7 fax FTTM sensors Description Quality Grade Order Code FTTM/TG FTTM/EG FTTM/IG FTTM/G Test grade Economy grade Industrial grade igh grade Philips reserves the right to change any information contained herein without notice. All information furnished by Philips is believed to be accurate. Philips Electronics N lmtb Philips Semiconductors TRAD

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