Chapter 3 :: equential Logi esign igital esign and Computer Arhiteture avid Money Harris and arah L. Harris Chapter 3 :: Topis Introdution Lathes and Flip-Flops ynhronous Logi esign Finite tate Mahines Timing of equential Logi Parallelism Copyright 27 Elsevier 3-<> Copyright 27 Elsevier 3-<2> Introdution Outputs of sequential logi depend on urrent and prior input values it has memory. ome definitions: tate: all the information about a iruit neessary to explain its future behavior Lathes and flip-flops: state elements that store one bit of state ynhronous sequential iruits: ombinational logi followed by a bank of flip-flops equential Ciruits Give sequene to events Have memory y( (short-term) Use feedbak from output to input to store information Copyright 27 Elsevier 3-<3> Copyright 27 Elsevier 3-<4>
tate Elements Bistable Ciruit The state of a iruit influenes its future behavior tate elements store state Bistable iruit Lath Lath Fli Flip-flop Fundamental building blok of other state elements Two outputs:, No inputs I2 I I I2 Copyright 27 Elsevier 3-<5> Copyright 27 Elsevier 3-<6> Bistable Ciruit Analysis (et/eset) Lath Consider the two possible ases: = : then = and = (onsistent) I Lath N I2 = : then = and = (onsistent) I I2 Bistable iruit stores bit of state in the state variable, (or ) But there are no inputs to ontrol the state Copyright 27 Elsevier 3-<7> N2 Consider the four possible ases: =, = =, = =, = =, = Copyright 27 Elsevier 3-<8> 2
Lath Analysis Lath Analysis =, = : = +? = = + = N =, = : = +? =? Not enough info = +? =? not enough info eset to N2 Can t resolve without knowing the old value of =, = : = +? =? not enough info = +? = now = + = et to N N2 Copyright 27 Elsevier 3-<9> Copyright 27 Elsevier 3-<> Lath Analysis Lath Analysis =, = : then = prev and = prev prev = prev = N N2 remembers its previous value (state) This is a way to build memory N N2 =, = : = +? = = + = invalid state: NOT on t try setting and resetting at the same time! N N2 Copyright 27 Elsevier 3-<> Copyright 27 Elsevier 3-<2> 3
Lath ymbol stands for et/eset Lath tores one bit of state () Control what value is being stored with, inputs et:make the output ( =, =, = ) eset: Make the output ( =, =, = ) Lath ymbol Must do something to avoid invalid state (when = =) Copyright 27 Elsevier 3-<3> Lath Two inputs:, : ontrols when the output hanges (the data input): ontrols what the output hanges to Funtion When =, passes through to (the lath is transparent) When =, holds its previous value (the lath is opaque) Avoids invalid ase when NOT Lath ymbol Copyright 27 Elsevier 3-<4> Lath Internal Ciruit Flip-Flop X X prev prev Copyright 27 Elsevier 3-<5> Two inputs:, Funtion The flip-flop flop samples on the rising edge of When rises from to, passes through to Otherwise, holds its previous value hanges only on the rising edge of A flip-flop is alled an edge-triggered devie beause it is ativated on the lok edge Flip-Flop ymbols Copyright 27 Elsevier 3-<6> 4
Flip-Flop Internal Ciruit Flip-Flop vs. Lath Two bak-to-bak lathes (L and L2) ontrolled by omplementary loks When = L is transparent L2 is opaque passes through to N When = N L2 is transparent L L2 L is opaque N passes through to Thus, on the edge of the lok (when rises from ) passes through to (lath) (flop) (flop) Copyright 27 Elsevier 3-<7> Copyright 27 Elsevier 3-<8> egisters Enabled Flip-Flops 3: 4 4 3: Inputs:,, EN The enable input (EN) ontrols when new data () is stored Funtion EN = passes through to on the lok edge EN = the flip-flop retains its previous state EN Internal Ciruit ymbol 2 3 2 3 EN Copyright 27 Elsevier 3-<9> Copyright 27 Elsevier 3-<2> 5
esettable Flip-Flops Inputs:,, eset Funtion: eset = is fored to eset = the flip-flop behaves like an ordinary flip-flop ymbols eset r esettable Flip-Flops Two types: ynhronous: resets at the lok edge only Asynhronous: resets immediately when eset = Asynhronously resettable flip-flop requires hanging the internal iruitry of the flip-flop (see Exerise 3.) ynhronously resettable flip-flop? eset Internal Ciruit Copyright 27 Elsevier 3-<2> Copyright 27 Elsevier 3-<22> ettable Flip-Flops Inputs:,, et Funtion: et = is set to et = the flip-flop behaves like an ordinary flip-flop ymbols equential Logi equential iruits: all iruits that aren t ombinational A problemati iruit: X Y Z This iruit has no inputs and -3 outputs X Y Z 2 3 4 5 6 7 8 time (ns) et s Copyright 27 Elsevier 3-<23> Copyright 27 Elsevier 3-<24> 6
equential Logi equential iruits: all iruits that aren t ombinational A problemati iruit: X Y Z This iruit has no inputs and -3 outputs It is an astable iruit that osillates Its period depends on the delay of the inverters whih depends on the manufaturing proess, temperature, et The iruit has a yli path: output fed bak to input X Y Z 2 3 4 5 6 7 8 time (ns) ynhronous equential Logi esign Breaks yli paths by inserting registers These registers ontain the state of the system The state t hanges at the lok edge, so we say the system is synhronized to the lok ules of synhronous sequential iruit omposition: Every iruit element is either a register or a ombinational iruit At least one iruit element is a register All registers reeive the same lok signal Every yli path ontains at tleast one register Two ommon synhronous sequential iruits Finite tate Mahines (FMs) Pipelines Copyright 27 Elsevier 3-<25> Copyright 27 Elsevier 3-<26> Finite tate Mahine (FM) Finite tate Mahines (FMs) Consists of: tate register that tores the urrent state and Loads the next state at the lok edge Next tate Current tate Next state is determined by the urrent state and the inputs Two types of finite state mahines differ in the output logi: Moore FM: outputs depend only on the urrent state Mealy FM: outputs depend on the urrent state and the inputs Combinational logi that Computes the next state Computes the outputs Next tate Logi Copyright 27 Elsevier 3-<27> C L Output Logi C L Next tate Outputs M inputs M inputs next state logi next state logi Moore FM next k k state state Mealy FM next k state k state output logi output logi N outputs N outputs Copyright 27 Elsevier 3-<28> 7
Finite tate Mahine Example FM Blak Box Traffi light ontroller Traffi sensors: T A, (TUE when there s traffi) Lights: L A, L B ining Hall Aademi Labs L A T A Bravado L B LA T A L B Ave. orms Inputs:, eset, T A, Outputs: L A, L B T A Traffi Light Controller L A L B Blvd. Fields eset Copyright 27 Elsevier 3-<29> Copyright 27 Elsevier 3-<3> FM tate Transition iagram FM tate Transition iagram Moore FM: outputs labeled in eah state tates: Cirles eset Transitions: Ars L A : green L B : red Moore FM: outputs labeled in eah state tates: Cirles T eset A Transitions: Ars L A : green L B : red T A L A : yellow L B : red 3 L A : red L B : yellow 2 L A : red L B : green Copyright 27 Elsevier 3-<3> Copyright 27 Elsevier 3-<32> 8
FM tate Transition Table FM Enoded tate Transition Table Current tate Inputs Next tate T A ' X X X X 2 2 X 3 2 X 2 3 X X Copyright 27 Elsevier 3-<33> Current tate Inputs Next tate T A ' ' tate Enoding X X X X X 2 X 3 X X ' = ' = T A + Copyright 27 Elsevier 3-<34> FM Output Table FM hemati: tate egister Current tate Outputs L A L A L B L B Output Enoding green yellow red L A = L A = L B = L B = Copyright 27 Elsevier 3-<35> ' ' r eset state register Copyright 27 Elsevier 3-<36> 9
FM hemati: Next tate Logi FM hemati: Output Logi ' L A ' L A T A ' r eset T A ' r eset L B L B inputs next state logi state register inputs next state logi state register output logi outputs Copyright 27 Elsevier 3-<37> Copyright 27 Elsevier 3-<38> FM Timing iagram FM tate Enoding eset T A ' : : L A: L B: Cyle Cyle 2 Cyle 3 Cyle 4 Cyle 5 Cyle 6 Cyle 7 Cyle 8 Cyle 9 Cyle???????? () () 2 () 3 () () () () () 2 () 3 () () Green () Yellow () ed () Green () ed () Green () Yellow () ed () Binary enoding: i.e., for four states,,,, One-hot enoding One state bit per state Only one state bit is HIGH at one I.e., for four states,,,, equires more flip-flops Often next state and output logi is simpler 5 5 2 25 3 35 4 45 T eset A TA L A : green L A : yellow L B : red L B : red t (se) 3 2 Copyright 27 Elsevier L A : red L A : red 3-<39> L B : yellow L B : green Copyright 27 Elsevier 3-<4>
Moore vs. Mealy FM tate Transition iagrams Alyssa P. Haker has a snail that rawls down a paper tape with s and s on it. The snail smiles whenever the last four digits it has rawled over are. esign Moore and Mealy FMs of the snail s brain. reset Moore FM 2 3 4 Mealy FM: ars indiate input/output Mealy FM reset / / / / Copyright 27 Elsevier 3-<4> 2 3 / / / / Copyright 27 Elsevier 3-<42> Moore FM tate Transition Table Moore FM Output Table Current tate Inputs Next tate 2 A ' 2 ' ' tate Enoding 2 3 4 Current tate Output 2 Y Y = 2 Copyright 27 Elsevier 3-<43> Copyright 27 Elsevier 3-<44>
Mealy FM tate Transition and Output Table Moore FM hemati A Current tate Input Next tate Output A ' ' Y tate Enoding 2 3 Copyright 27 Elsevier 3-<45> 2 ' 2 ' ' eset 2 Copyright 27 Elsevier 3-<46> Y Mealy FM hemati Moore and Mealy Timing iagram A ' Y eset Cyle Cyle 2 Cyle 3 Cyle 4 Cyle 5 Cyle 6 Cyle 7 Cyle 8 Cyle 9 Cyle A Moore Mahine?? 2 2 3 4 2 3 4 ' eset Y Y Mealy Mahine?? 2 2 3 2 3 Copyright 27 Elsevier 3-<47> Copyright 27 Elsevier 3-<48> 2
Fatoring tate Mahines Parade FM Break omplex FMs into smaller interating FMs Example: Modify the traffi light ontroller to have a Parade Mode. The FM reeives two more inputs: P, When P =, it enters Parade Mode and the Bravado Blvd. light stays green. When =, it leaves Parade Mode Unfatored FM Fatored FM P T A P Controller FM Mode FM M L A L B T A Lights FM L A L B Copyright 27 Elsevier 3-<49> Controller FM Copyright 27 Elsevier 3-<5> Unfatored FM tate Transition iagram Fatored FM tate Transition iagram PT A eset L A : green L B : red P PT A PT A P T A P 3 P L A : red L B : yellow P L A : yellow L B : red P P 2 L A : red L B : green P T A T A 4 L A : green L B : red T A 7 L A : red L B : yellow T A 5 L A : yellow L B : red 6 L A : red L B : green eset L A : green L B : red T A T A 3 L A : red L B : yellow M M + Lights FM L A : yellow L B : red 2 L A : red L B : green eset P P M: M: Mode FM Copyright 27 Elsevier 3-<5> Copyright 27 Elsevier 3-<52> 3
FM esign Proedure Timing Identify the inputs and outputs keth a state transition diagram Write a state transition table elet state enodings For a Moore mahine: ewrite the state transition table with the seleted state enodings Write the output table For a Mealy mahine: ewrite the ombined state transition and output table with the seleted state enodings Write Boolean equations for the next state and output logi keth the iruit shemati Flip-flop samples at lok edge must be stable when it is sampled imilar il to a photograph, h must tbe stable around the lok edge If is hanging when it is sampled, metastability an our Copyright 27 Elsevier 3-<53> Copyright 27 Elsevier 3-<54> Input Timing Constraints etup time: t setup = time before the lok edge that data must be stable (i.e. not hanging) Hold time: t hold = time after the lok edge that data must be stable Aperture time: t a = time around lok edge that data must be stable (t a = t setup + t hold ) Output Timing Constraints Propagation delay: t pq = time after lok edge that the output is guaranteed to be stable (i.e., to stop hanging) Contamination delay: t q = time after lok edge that might be unstable (i.e., start hanging) t q t pq t setup t hold t Copyright 27 Elsevier a 3-<55> Copyright 27 Elsevier 3-<56> 4
ynami isipline The input to a synhronous sequential iruit must be stable during the aperture (setup and hold) time around the lok edge. peifially, the input must be stable at least t setup before the lok edge at least until t hold after the lok edge ynami isipline The delay between registers has a minimum and maximum delay, dependent on the delays of the iruit elements (a) CL 2 2 T 2 (b) Copyright 27 Elsevier 3-<57> Copyright 27 Elsevier 3-<58> etup Time Constraint Hold Time Constraint epends on the maximum delay from register through the ombinational logi to 2 The input to register 2 must be stable at least t setup before the lok edge 2 C L 2 2 T t pq + t pd + t setup T t pd T (t pq + t setup ) t pq t pd t setup epends on the minimum delay from register through the ombinational logi to 2 The input to register 2 must be stable for at least t hold after the lok edge C 2 L 2 2 t q t hold t d t hold < t q + t d t d > t hold -t q Copyright 27 Elsevier 3-<59> Copyright 27 Elsevier 3-<6> 5
Timing Analysis A B C X' X Y' Y t pd = 3 x 35 ps = 5 ps p t d = 25 ps etup time onstraint: T (5 + 5 + 6) ps = 25 ps f = /T = 4.65 GHz Timing Charateristis per gate t q = 3 ps t pq = 5 ps pq t setup = 6 ps t hold = 7 ps t pd = 35 ps t d = 25 ps Hold time onstraint: t q + t d > t hold? (3 + 25) ps > 7 ps? No! Copyright 27 Elsevier 3-<6> Fixing Hold Time Violation Add buffers to the short paths: Timing Charateristis t q = 3 ps A t pq = 5 ps B C X' X Y' Y t pd = 3 x 35 ps = 5 ps p t d = 2 x 25 ps = 5 ps etup time onstraint: T (5 + 5 + 6) ps = 25 ps f = /T = 4.65 GHz per gate pq t setup = 6 ps t hold = 7 ps t pd = 35 ps t d = 25 ps Hold time onstraint: t q + t d > t hold? (3 + 5) ps > 7 ps? Yes! Copyright 27 Elsevier 3-<62> Clok kew etup Time Constraint with Clok kew The lok doesn t arrive at all registers at the same time kew is the differene between two lok edges Examine the worst ase to guarantee that the dynami disipline is not violated for any register many registers in a system! In the worst ase, 2 is earlier than 2 C 2 L T 2 delay C L 2 2 2 2 T t pq + t pd + t setup + t skew t pd T (t pq + t setup + t skew ) t skew 2 2 t pq t pd t setup t skew Copyright 27 Elsevier 3-<63> Copyright 27 Elsevier 3-<64> 6
Hold Time Constraint with Clok kew Violating the ynami isipline In the worst ase, 2 is later than 2 C 2 L Asynhronous (for example, user) inputs might violate the dynami disipline t setup t hold 2 2 t q t d 2 t q + t d > t hold + t skew t d > t hold + t skew t q button t aperture Case I Case II t skew t hold Copyright 27 Elsevier 3-<65> Copyright 27 Elsevier 3-<66>??? Case III Metastability Flip-flop Internals Any bistable devie has two stable states and a metastable state between them A flip-flop has two stable states ( and ) and one metastable state If a flip-flop lands in the metastable state, it ould stay there for an undetermined amount of time Beause the flip-flop has feedbak, if is somewhere between and, the ross-oupled gates will eventually drive the output to either rail ( or, depending on whih one it is loser to). N metastable N2 stable stable A signal is onsidered metastable if it hasn t resolved to or If a flip-flopflop input hanges at a random time, the probability that the output is metastable after waiting some time, t, is: P(t res > t) = (T /T ) e -t/τ Copyright 27 Elsevier 3-<67> t res : time to resolve to or T, τ : properties of the iruit Copyright 27 Elsevier 3-<68> 7
Metastability Intuitively: T /T desribes the probability that the input hanges at a bad time, i.e., during the aperture time P(t res > t) = (T /T ) e -t/τ τ is a time onstant indiating how fast the flip-flop moves away from the metastable state; it is related to the delay through the ross-oupled gates in the flip-flop P(t res > t) = (T /T ) e -t/τ ynhronizers Asynhronous inputs () are inevitable (user interfaes, systems with different loks interating, et.). The goal of a synhronizer is to make the probability of failure (the output still being metastable) low. A synhronizer annot make the probability of failure. In short, if a flip-flop samples a metastable input, if you wait long enough (t), the output will have resolved to or with high probability. YNC Copyright 27 Elsevier 3-<69> Copyright 27 Elsevier 3-<7> ynhronizer Internals ynhronizer Probability of Failure A synhronizer an be built with two bak-to-bak flip-flops. uppose the input is transitioning when it is sampled by flip-flop, F. The amount of time the internal signal 2 an resolve to a or is (T - t setup ). 2 F T F2 For eah sample, the probability of failure of this synhronizer is: P(failure) = (T /T ) e -(T - t setup )/τ F 2 T F2 2 metastable 2 metastable Copyright 27 Elsevier t t 3-<7> res setup t pq Copyright 27 Elsevier t t 3-<72> res setup t pq 8
ynhronizer Mean Time Before Failure If the asynhronous input hanges one per seond, the probability of failure per seond of the synhronizer is simply P(failure). In general, if the input hanges N times per seond, the probability of failure per seond of the synhronizer is: P(failure)/seond = (NT /T ) e -(T -t setup )/τ Thus, the synhronizer fails, on average, /[P(failure)/seond] This is alled the mean time between failures, MTBF: MTBF = /[P(failure)/seond] = (T /NT ) e (T -t setup )/τ Example ynhronizer F 2 F2 uppose: T = /5 MHz = 2 ns τ = 2 ps T = 5 ps t setup = ps N = events per seond What is the probability of failure? MTBF? P(failure) = (5 ps/2 ns) e-(.9 ns)/2 ps = 56 5.6-6 P(failure)/seond = (5.6-6 ) = 5.6-5 / seond MTBF = /[P(failure)/seond] 5 hours Copyright 27 Elsevier 3-<73> Copyright 27 Elsevier 3-<74> Parallelism Parallelism efinitions Two types of parallelism: patial parallelism dupliate hardware performs multiple tasks at one Temporal parallelism task is broken into multiple stages also alled pipelining for example, an assembly line ome definitions: Token: A group of inputs proessed to produe a group of outputs Lateny: Time for one token to pass from start to end Throughput: The number of tokens that an be produed per unit time Parallelism inreases throughput. Copyright 27 Elsevier 3-<75> Copyright 27 Elsevier 3-<76> 9
Parallelism Example Parallelism Example Ben Bitdiddle is baking ookies to elebrate the installation of his traffi light ontroller. It takes 5 minutes to roll the ookies and 5 minutes to bake them. After finishing one bath he immediately starts the next bath. What is the lateny and throughput if Ben doesn t use parallelism? What is the lateny and throughput if Ben uses parallelism? patial parallelism: Ben asks Allysa P. Haker to help, using her own oven Temporal parallelism: Ben breaks the task into two stages: roll and baking. He uses two trays. While the first bath is baking he rolls the seond bath, and so on. Lateny = 5 + 5 = 2 minutes = /3 hour Throughput = tray/ /3 hour = 3 trays/hour Copyright 27 Elsevier 3-<77> Copyright 27 Elsevier 3-<78> patial Parallelism Temporal Parallelism patial Parallelism Tray Tray 2 Tray 3 Tray 4 Lateny: time to first tray 5 5 2 25 3 35 4 45 5 Time Ben Ben oll Alyssa Alyssa Ben 2 Ben 2 Bake Alyssa 2 Alyssa 2 Legend Temporal Parallelism Tray Tray 2 Tray 3 Lateny: time to first tray 5 5 2 25 3 35 4 45 5 Time Ben Ben Ben 2 Ben 2 Ben 3 Ben 3 Lateny = 5 + 5 = 2 minutes = /3 hour Throughput = 2 trays/ /3 hour = 6 trays/hour Lateny = 5 + 5 = 2 minutes = /3 hour Throughput = trays/ /4 hour = 4 trays/hour Using both tehniques, the throughput would be 8 trays/hour Copyright 27 Elsevier 3-<79> Copyright 27 Elsevier 3-<8> 2