Chapter 3 :: equential Logic esign Chapter 3 :: Topics igital esign and Computer Architecture avid Money Harris and arah L. Harris Introduction Latches and Flip-Flops ynchronous Logic esign Finite tate Machines Timing of equential Logic arallelism Copyright 27 Elsevier 3-<> Copyright 27 Elsevier 3-<2> Introduction Outputs of sequential logic depend on current and prior input values. equential logic thus has memory. ome definitions: tate: all the information about a circuit necessary to explain its future behavior Latches and flip-flops: state elements that store one bit of state ynchronous sequential circuits: combinational logic followed by a bank of flip-flops equential Circuits give sequence to events have memory (short-term) use feedback from output to input to store information Copyright 27 Elsevier 3-<3> Copyright 27 Elsevier 3-<4>
tate Elements Bistable Circuit The state of a circuit influences its future behavior tate elements store state Bistable circuit Latch Latch Flip-flop Fundamental building block of other state elements Two outputs:, No inputs I2 I I I2 Copyright 27 Elsevier 3-<5> Copyright 27 Elsevier 3-<6> Bistable Circuit Analysis Latch Consider the two possible cases: = : then = and = (consistent) I Latch N I2 = : then = and = (consistent) Bistable circuit stores bit of state in the state variable, (or ) But there are no inputs to control the state I I2 N2 Consider the four possible cases: =, = =, = =, = =, = Copyright 27 Elsevier 3-<7> Copyright 27 Elsevier 3-<8> 2
Latch Analysis Latch Analysis =, = : then = and = N =, = : then = prev prev = prev = N N N2 N2 N2 =, = : then = and = N =, = : then = and = N N2 Copyright 27 Elsevier 3-<9> N2 Copyright 27 Elsevier 3-<> Latch ymbol stands for et/eset Latch tores one bit of state () Control what value is being stored with, inputs et:make the output eset:make the output When the set input,, is (and = ), is set to When the reset input,, is (and = ), is reset to Invalid state when = = Latch ymbol Copyright 27 Elsevier 3-<3> Latch Two inputs:, : controls when the output changes (the data input): controls what the output changes to Function When =, passes through to (the latch is transparent) When =, holds its previous value (the latch is opaque) Avoids invalid case when NOT Latch ymbol Copyright 27 Elsevier 3-<4> 3
Latch Internal Circuit Flip-Flop X Copyright 27 Elsevier 3-<5> Two inputs:, Function The flip-flop samples on the rising edge of When rises from to, passes through to Otherwise, holds its previous value changes only on the rising edge of A flip-flop is called an edge-triggered device because it is activated on the clock edge Flip-Flop ymbols Copyright 27 Elsevier 3-<7> Flip-Flop Internal Circuit Flip-Flop vs. Latch Two back-to-back latches (L and L2) controlled by complementary clocks When = L is transparent L2 is opaque passes through to N When = L2 is transparent L is opaque N passes through to L N L2 Thus, on the edge of the clock (when rises from ) passes through to (latch) (flop) Copyright 27 Elsevier 3-<8> Copyright 27 Elsevier 3-<9> 4
egisters Enabled Flip-Flops 3: 4 4 3: Inputs:,, EN The enable input (EN) controls when new data () is stored Function EN = passes through to on the clock edge EN = the flip-flop retains its previous state EN Internal Circuit ymbol 2 3 2 3 EN Copyright 27 Elsevier 3-<2> Copyright 27 Elsevier 3-<22> esettable Flip-Flops Inputs:,, eset Function: eset = is forced to eset = the flip-flop behaves like an ordinary flip-flop ymbols eset r esettable Flip-Flops Two types: ynchronous: resets at the clock edge only Asynchronous: resets immediately when eset = ynchronously resettable flip-flop requires changing the internal circuitry of the flip-flop (see Exercise 3.) Asynchronously resettable flip-flop: eset Internal Circuit Copyright 27 Elsevier 3-<23> Copyright 27 Elsevier 3-<24> 5
ettable Flip-Flops Inputs:,, et Funtion: et = is set to et = the flip-flop behaves like an ordinary flip-flop ymbols equential Logic equential circuits: all circuits that aren t combinational A problematic circuit: X Y Z This circuit has no inputs and -3 outputs X Y Z 2 3 4 5 6 7 8 time (ns) et s Copyright 27 Elsevier 3-<25> Copyright 27 Elsevier 3-<26> ynchronous equential Logic esign Finite tate Machine (FM) Breaks cyclic paths by inserting registers These registers contain the state of the system The state changes at the clock edge, so we say the system is synchronized to the clock ules of synchronous sequential circuit composition: Every circuit element is either a register or a combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register Two common synchronous sequential circuits Finite state machines (FMs) ipelines Consists of: tate register that tore the current state and Load the next state at the clock edge Combinational logic that Computes the next state Computes the outputs Next tate Next tate Logic C L Output Logic C L Current tate Next tate Outputs Copyright 27 Elsevier 3-<28> Copyright 27 Elsevier 3-<29> 6
Finite tate Machines (FMs) Finite tate Machine Example Next state is determined by the current state and the inputs Two types of finite state machines differ in the output logic: Moore FM: outputs depend only on the current state Mealy FM: outputs depend on the current state and the inputs M inputs M inputs next state logic next state logic Moore FM next k k state state Mealy FM next k state k state output logic output logic N outputs N outputs Copyright 27 Elsevier 3-<3> Traffic light controller Traffic sensors:, (TUE when there s traffic) Lights: L A, L B ining Hall Academic Labs L A Copyright 27 Elsevier 3-<3> Bravado Blvd. L B L A L B Fields Ave. orms FM Black Box FM tate Transition iagram Inputs:, eset,, Outputs: L A, L B Moore FM: outputs labeled in each state tates: Circles Transitions: Arcs eset L A : green L B : red TA L A : yellow L B : red Traffic Light Controller L A L B eset 3 L A : red L B : yellow 2 L A : red L B : green Copyright 27 Elsevier 3-<32> Copyright 27 Elsevier 3-<34> 7
FM tate Transition Table FM Encoded tate Transition Table Current tate 2 2 3 X X X X Inputs X X X X Next tate ' Current tate Inputs X X X X X X X X Next tate ' ' tate 2 3 Encoding Copyright 27 Elsevier 3-<35> Copyright 27 Elsevier 3-<37> FM Output Table FM chematic: tate egister Current tate L A Outputs L A L B L B Output green yellow red Encoding ' ' r eset state register Copyright 27 Elsevier 3-<39> Copyright 27 Elsevier 3-<4> 8
FM chematic: Next tate Logic FM chematic: Output Logic L A ' ' L A ' r eset ' r eset L B L B inputs next state logic state register inputs next state logic state register output logic outputs Copyright 27 Elsevier 3-<42> Copyright 27 Elsevier 3-<43> FM Timing iagram FM tate Encoding eset ' : : L A: Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle?? () () 2 () 3 () () ()?? () () 2 () 3 () ()?? Green () Yellow () ed () Green () Binary encoding: i.e., for four states,,,, One-hot encoding One state bit per state Only one state bit is HIGH at once I.e., for four states,,,, equires more flip-flops Often next state and output logic is simpler L B:?? ed () Green () Yellow () ed () 5 5 2 25 3 35 4 45 T eset A TA L A : green L A : yellow L B : red L B : red t (sec) 3 2 Copyright 27 Elsevier L A : red L A : red 3-<44> L B : yellow L B : green Copyright 27 Elsevier 3-<45> 9
Moore vs. Mealy FM tate Transition iagrams Alyssa. Hacker has a snail that crawls down a paper tape with s and s on it. The snail smiles whenever the last four digits it has crawled over are. esign Moore and Mealy FMs of the snail s brain. reset Moore FM 2 3 4 Mealy FM: arcs indicate input/output Mealy FM reset / / / / 2 3 Copyright 27 Elsevier 3-<46> / / / / Copyright 27 Elsevier 3-<47> Moore FM tate Transition Table Moore FM Output Table Current tate Inputs Next tate 2 A ' 2 ' ' tate Encoding Current tate Output 2 3 4 2 Y Copyright 27 Elsevier 3-<48> Copyright 27 Elsevier 3-<5>
Mealy FM tate Transition and Output Table Moore FM chematic A Current tate Input Next tate Output ' 2 2 Y A ' ' Y tate Encoding ' 2 3 ' eset 2 Copyright 27 Elsevier 3-<52> Copyright 27 Elsevier 3-<54> Mealy FM chematic Moore and Mealy Timing iagram A Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle ' Y eset ' eset A Y Y Moore Machine?? 2 2 3 4 2 3 4 Mealy Machine?? 2 2 3 2 3 Copyright 27 Elsevier 3-<55> Copyright 27 Elsevier 3-<56>
Factoring tate Machines arade FM Break complex FMs into smaller interacting FMs Example: Modify the traffic light controller to have a arade Mode. The FM receives two more inputs:, When =, it enters arade Mode and the Bravado Blvd. light stays green. When =, it leaves arade Mode Unfactored FM Factored FM Controller FM Mode FM M L A L B Lights FM L A L B Controller FM Copyright 27 Elsevier 3-<57> Copyright 27 Elsevier 3-<58> Unfactored FM tate Transition iagram Factored FM tate Transition iagram eset L A : green L B : red 3 L A : red L B : yellow L A : yellow L B : red 2 L A : red L B : green 4 L A : green L B : red 7 L A : red L B : yellow 5 L A : yellow L B : red 6 L A : red L B : green eset L A : green L B : red 3 L A : red L B : yellow TA M L A : yellow L B : red 2 L A : red L B : green eset M: M: M + Lights FM Mode FM Copyright 27 Elsevier 3-<59> Copyright 27 Elsevier 3-<6> 2
FM esign rocedure Timing Identify the inputs and outputs ketch a state transition diagram Write a state transition table elect state encodings For a Moore machine: ewrite the state transition table with the selected state encodings Write the output table For a Mealy machine: ewrite the combined state transition and output table with the selected state encodings Write Boolean equations for the next state and output logic ketch the circuit schematic Flip-flop samples at clock edge must be stable when it is sampled imilar to a photograph, must be stable around the clock edge If is changing when it is sampled, metastability can occur Copyright 27 Elsevier 3-<6> Copyright 27 Elsevier 3-<62> Input Timing Constraints etup time: t setup = time before the clock edge that data must be stable (i.e. not changing) Hold time: t hold = time after the clock edge that data must be stable Aperture time: t a = time around clock edge that data must be stable (t a = t setup + t hold ) Output Timing Constraints ropagation delay: t pcq = time after clock edge that the output is guaranteed to be stable (i.e., to stop changing) Contamination delay: t ccq = time after clock edge that might be unstable (i.e., start changing) t ccq t pcq t setup t hold t Copyright 27 Elsevier a 3-<63> Copyright 27 Elsevier 3-<64> 3
ynamic iscipline The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge. pecifically, the input must be stable at least t setup before the clock edge at least until t hold after the clock edge ynamic iscipline The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements (a) CL 2 2 T c 2 (b) Copyright 27 Elsevier 3-<65> Copyright 27 Elsevier 3-<66> etup Time Constraint Hold Time Constraint The setup time constraint depends on the maximum delay from register through the combinational logic. The input to register 2 must be stable at least t setup before the clock edge. 2 C L T c t pcq t pd t setup 2 2 T c The hold time constraint depends on the minimum delay from register through the combinational logic. The input to register 2 must be stable for at least t hold after the clock edge. C 2 L 2 2 t ccq t cd t hold t hold < Copyright 27 Elsevier 3-<67> Copyright 27 Elsevier 3-<7> 4
Timing Analysis Fixing Hold Time Violation A B C X' X Timing Characteristics t ccq = 3 ps t pcq = 5 ps t setup = 6 ps t hold = 7 ps Add buffers to the short paths: A B C X' X Timing Characteristics t ccq = 3 ps t pcq = 5 ps t setup = 6 ps t hold = 7 ps t pd = Y' Y per gate t pd = 35 ps t cd = 25 ps t pd = Y' Y per gate t pd = 35 ps t cd = 25 ps t cd = t cd = etup time constraint: Hold time constraint: etup time constraint: Hold time constraint: T c f c = /T c = t ccq + t pd > t hold? T c f c = t ccq + t pd > t hold? Copyright 27 Elsevier 3-<73> Copyright 27 Elsevier 3-<75> Clock kew etup Time Constraint with Clock kew The clock doesn t arrive at all registers at the same time This may be caused by delay or other timing noise kew is the difference between two clock edges Because there may be many registers in a system, we examine the worst case for each case to guarantee that the dynamic discipline is not violated for any register t skew delay C L 2 2 2 In the worst case, the 2 is earlier than 2 2 2 C 2 L T c 2 T c 2 t pcq t pd t setup t skew Copyright 27 Elsevier 3-<77> Copyright 27 Elsevier 3-<78> 5
Hold Time Constraint with Clock kew Violating the ynamic iscipline In the worst case, 2 is later than 2 2 CL Asynchronous (for example, user) inputs might violate the dynamic discipline t setup t hold 2 2 t ccq t cd 2 t ccq + t cd > t cd > button t aperture Case I Case II t skew t hold Copyright 27 Elsevier 3-<8> Copyright 27 Elsevier 3-<84>??? Case III Metastability Flip-flop Internals Any bistable device has two stable states and a metastable state between them A flip-flop has two stable states ( and ) and one metastable state If a flip-flop lands in the metastable state, it could stay there for an undetermined amount of time Because the flip-flop has feedback, if is somewhere between and, the cross-coupled gates will eventually drive the output to either rail ( or, depending on which one it is closer to). N metastable N2 stable stable A signal is considered metastable if it hasn t resolved to or If a flip-flop input changes at a random time, the probability that the output is metastable after waiting some time, t, is: (t res > t) = (T /T c ) e -t/τ Copyright 27 Elsevier 3-<85> t res : time to resolve to or T, τ : properties of the circuit Copyright 27 Elsevier 3-<86> 6
Metastability Intuitively: T /T c describes the probability that the input changes at a bad time, i.e., during the aperture time (t res > t) = (T /T c ) e -t/τ τ is a time constant indicating how fast the flip-flop moves away from the metastable state; it is related to the delay through the cross-coupled gates in the flip-flop (t res > t) = (T /T c ) e -t/τ ynchronizers Asynchronous inputs () are inevitable (user interfaces, systems with different clocks interacting, etc.). The goal of a synchronizer is to make the probability of failure (the output still being metastable) low. A synchronizer cannot make the probability of failure. In short, if a flip-flop samples a metastable input, if you wait long enough (t), the output will have resolved to or with high probability. YNC Copyright 27 Elsevier 3-<87> Copyright 27 Elsevier 3-<88> ynchronizer Internals ynchronizer robability of Failure A synchronizer can be built with two back-to-back flip-flops. uppose the input is transitioning when it is sampled by flip-flop, F. The amount of time the internal signal 2 can resolve to a or is (T c - t setup ). F 2 T c F2 For each sample, the probability of failure of this synchronizer is: (failure) = (T /T c ) e -(T c - t setup )/τ F 2 T c F2 2 metastable 2 metastable Copyright 27 Elsevier t t 3-<89> res setup t pcq Copyright 27 Elsevier t t 3-<9> res setup t pcq 7
ynchronizer Mean Time Before Failure If the asynchronous input changes once per second, the probability of failure per second of the synchronizer is simply (failure): In general, if the input changes N times per second, the probability of failure per second of the synchronizer is: (failure)/second = (NT /T c ) e -(T c - t setup )/τ Thus, the synchronizer fails, on average, /[(failure)/second] This is called the mean time between failures, MTBF: MTBF = /[(failure)/second] = (T c /NT ) e (T c - t setup )/τ Example ynchronizer F 2 uppose: T c = /5 MHz τ = 2 ps T = 5 ps t setup = ps N = events per second What is the probability of failure? MTBF? (failure) = (failure)/second = F2 MTBF = Copyright 27 Elsevier 3-<9> Copyright 27 Elsevier 3-<92> arallelism arallelism Example ome definitions: Token: A group of inputs processed to produce a group of outputs Latency: Time for one token to pass from start to end Throughput: The number of tokens that can be produced per unit time arallelism increases throughput. Two types of parallelism: patial parallelism duplicate hardware performs multiple tasks at once Temporal parallelism task is broken into multiple stages also called pipelining for example, an assembly line Ben Bitdiddle is baking cookies to celebrate the installation of his traffic light controller. It takes 5 minutes to roll the cookies and 5 minutes to bake them. After finishing one batch he immediately starts the next batch. What is the latency and throughput if Ben doesn t use parallelism? Latency = 5 + 5 = 2 minutes = /3 hour Throughput = tray/ /3 hour = 3 trays/hour Copyright 27 Elsevier 3-<94> Copyright 27 Elsevier 3-<96> 8
arallelism Example patial arallelism What is the latency and throughput if Ben uses parallelism? patial parallelism: Ben asks Allysa. Hacker to help, using her own oven Temporal parallelism: Ben breaks the task into two stages: roll and baking. He uses two trays. While the first batch is baking he rolls the second batch, and so on. patial arallelism Tray Tray 2 Tray 3 Tray 4 Latency: time to first tray 5 5 2 25 3 35 4 45 5 Time Ben Ben oll Alyssa Alyssa Ben 2 Ben 2 Bake Alyssa 2 Alyssa 2 Legend Latency = Throughput = Copyright 27 Elsevier 3-<97> Copyright 27 Elsevier 3-<98> Temporal arallelism Latency: time to first tray 5 5 2 25 3 35 4 45 5 Temporal arallelism Tray Tray 2 Tray 3 Ben Ben Ben 2 Ben 2 Ben 3 Ben 3 Time Latency = Throughput = Copyright 27 Elsevier 3-<> 9