Addressing Process Scaling Challenges in Server Memory Eric Caward, Business Development Manager

Transcription

1 Addressing Process Scaling Challenges in Server Memory Eric Caward, Business Development Manager Linley Spring Processor Conference: April 11, Micron Technology, Inc. All rights reserved. Information, products, and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Statements regarding products, including regarding their features, availability, functionality, or compatibility, are provided for informational purposes only and do not modify the warranty, if any, applicable to any product. Drawings may not be to scale. Micron, the Micron logo, and all other Micron trademarks are the property of Micron Technology, Inc. All other trademarks are the property of their respective owners.

2 B GB Explosive Cloud Growth DRAM TAM 8 6 Market DRAM Cloud 22% 32% CAGR CY16 CY17 CY18 CY19 CY20 CY21 CY22

3 Traditional Supply 0% - 100% Delivering Data Center Access to More Bits Baseline Mature Test/Debug (low volume) Design Qualification (ramping volume) Full Production (high volume)

4 Traditional Supply 0% - 100% Delivering Data Center Access to More Bits Additional Supply Reliable Bits w/ecc Baseline Mature Test/Debug (low volume) Design Qualification (ramping volume) Full Production (high volume)

5 Good bits vs. Bad bits

6 Scope Good of bits Good vs. Bits Bad vs. bits Bad Bits

7 Understanding Error Types Undetected Detected Hard Soft lexicon noun [lek-si-kon, -kuh n] the vocabulary of a particular language, field, social class, person, etc. Uncorrectable Correctable

8 Physics is the Root Cause of Refresh Related Single Bits DRAM Cell Scaling 100% 10% 50nm 1Ynm

9 Physics is the Root Cause of Refresh Related Single Bits DRAM Cell Scaling 100% 10% 50nm 1Ynm

10 Physics is the Root Cause of Refresh Related Single Bits DRAM Cell Scaling Variable Retention Time % 10% nm 1Ynm Effective Internal Refresh (Ext tref=64ms)

11 Predominate Module Field Failures are Correctable 10 s of Millions of Modules Shipped < 0.05% were confirmed fails ~ 0.005% were estimated uncorrectable Includes post production damage, the most predominant of failure mechanisms Pass Correctable Uncorrectable

12 Robust Error Correction in Today s Data Center ECC: Single Bit 100% Correctable Beat Example Data (72 bits) 0 00 FF00FF01 FF00FF AA55AA55 AA55AA55 2 CC 33CC33CC 33CC33CC BB44BB44 BB44BB44 6 DD 22DD22DD 22DD22DD 7 11 EE11EE11 EE11EE11

13 Robust Error Correction in Today s Data Center ECC: Single Bit ECC: Multi Bits 100% Correctable Beat Example Data (72 bits) 0 00 FF00FF01 FF00FF AA55AA55 AA55AA55 2 CC 33CC33CC 33CC33CC BB44BB44 BB44BB44 6 DD 22DD22DD 22DD22DD 7 11 EE11EE11 EE11EE11 x4 Components Able to correct errors in different halves of burst Beat Example Data (72 bits) 0 00 FF00FE00 FF00FF AA55AB55 AA55AA55 2 CC 33CC32CC 33CC33CC F BB44BB44 BB44BBF4 6 DD 22DD22DD 22DD22FD 7 11 EE11EE11 EE11EEF1 x8 Components Standard Config Lockstep Config Beat Example Data (72 bits) 0 00 FF00FF00 FF00FF AA05AA55 AA55AA55 2 CC 330C33CC 33CC33CC BB5BBB44 BB44BB44 6 DD 22DD22DD 22DD22DD 7 11 EE11EE11 EE11EE11

14 Correctable Errors Do Not Foretell Uncorrectable Errors SETUP

15 Correctable Errors Do Not Foretell Uncorrectable Errors SETUP

16 Correctable Errors Do Not Foretell Uncorrectable Errors SETUP

17 Correctable Errors Do Not Foretell Uncorrectable Errors SETUP

18 Correctable Errors Do Not Foretell Uncorrectable Errors SETUP

19 Number of Errors Per Day Total Number of Errors Correctable Errors Do Not Foretell Uncorrectable Errors Number of Correctable Errors 3,000, ,113, ,000,000 2,000, ,000,000 1,000, ,000, Days tested 0 System Correctable fails Cumulative Fails Log. (System Correctable fails)

20 Number of Errors Per Day Total Number of Errors Correctable Errors Do Not Foretell Uncorrectable Errors Number of Correctable Errors 3,000, ,113, ,000,000 2,000, ,000,000 1,000, ,000, Days tested 0 System Correctable fails Cumulative Fails Log. (System Correctable fails) Note: Application tests only finds 1,170 (or % of errors found)

21 Number of Errors Per Day Total Number of Errors Correctable Errors Do Not Foretell Uncorrectable Errors Number of Correctable Errors 3,000, ,113, ,000,000 2,000, ,000,000 1,000, ,000,000 0 Uncorrectable Events Detected Days tested 0 System Correctable fails Cumulative Fails Log. (System Correctable fails) Note: Application tests only finds 1,170 (or % of errors found)

22 No Appreciable Performance Penalty SETUP

23 No Appreciable Performance Penalty SETUP

24 No Appreciable Performance Penalty SETUP

25 Performance 1/s No Appreciable Performance Penalty Results Context Switch Performance Cost lmbench lat_ctx (size=64k ovr=2.68) % % % % % Number of Processes Context Switch 1/s

26 Performance 1/s Bandwidth % Normalized No Appreciable Performance Penalty Results Context Switch Performance Cost lmbench lat_ctx (size=64k ovr=2.68) Single Bit Performance Cost Monitor Data % 60% 400, % 50% 40% 300, % 30% 200,000 Errors % 20% 10% 100, % % 0 Number of Processes Total data bus B/W % imc:n0_h1_c1[4]-errs Context Switch 1/s

27 Performance 1/s Bandwidth % Normalized No Appreciable Performance Penalty Results Context Switch Performance Cost lmbench lat_ctx (size=64k ovr=2.68) Single Bit Performance Cost Monitor Data % 60% 400, % 50% 40% 300, % 30% 200,000 Errors % 20% 10% 100, % % 0 Number of Processes Total data bus B/W % imc:n0_h1_c1[4]-errs Context Switch 1/s >> Error Correction 1/s

28 Achieve Form, Fit, Function, Performance, and Reliability Leverage System Level ECC to Enable More Bits Today