Understanding IRS3B, board-stack and

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Harriet Miller
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Understanding IRS3B, board-stack and mtc

1 Understanding IRS3B, board-stack and mtc operation/calibration Calibration in progress ~31ps RMS timing difference (2 edges) Single edge timing: ~22ps RMS Net timing difference (Ch.7 Ch. 4) [ns] Gary S. Varner 2 JUL 2014 mtc Training Session #3

2 mtc Readout Roadmap Currently at about Phase 1.5 You can get us to Phase 2.5 Specifically Operators need to understand Hardware/Firmware/Software Develop real-time Data Quality Monitoring i What I hope to convey: 1. Details of the hardware: ASIC + boardstack 2. Firmware and Configuration/Operating parameters 3. Understand how to read and comprehend documentation and ask meaningful questions ( it doesn t work notably not amongst them) 2

3 IRS3B Structure 3

4 Hopefully, these will start to make sense in terms of how these settings map onto operational parameters of the IRS3B ASIC 4

5 Simple software Once have writing template that talks to the picoblaze, tuning operational parameters of the IRS3B ASIC really easy 5

6 Servo-controls (3 parameters) Sampling speed Trigger 1-shot Width Adjust T_1_TRG Power (T_1_TRG) 100 ADC 10 Clock [ns] Output Width Trigger output Width September 22, Discharge Current [ua] 6

7 Specifically, for mtc Software Servolock? Trigger 1-shot Width Adjust T_1_TRG Power (T_1_TRG) 100 Keep Firmware Servo [ns] Output Width 10 Don t bother September 22, Discharge Current [ua] 7

8 Firmware Servo-lock 8

9 mtc software pointer 9

10 A word of caution 10

11 What limits timing? Increased Amplification: Want >100 ADC counts (>~ 60mV) for smallest pulses: Carrier Rev C ps 60-70ps 11

12 Oscilloscope on a chip? Calibration ~=?? 12

13 Oscilloscope on a chip? Calibration Modified approximation: ~ = 13

14 Calibration and Sources of Timing i Error voltage noise u timing i uncertainty t t signal height U u U t t t r rise time t r t r 1 3 f 3dB t u U t r u U n t r u U t t r r u t u r f U U s f s 3 f s f 3 db 1 *Diagram, formulas from Stefan Ritt 14

15 Calibration and Sources of Timing Error Contributions to timing resolution: Voltage uncertainties Timing uncertainties voltage noise u timing uncertainty t signal height U *Diagram from Stefan Ritt rise time t r Of these contributions: Random irreducible (without hardware redesign) Deterministic in principle can be calibrated away. Let s talk about where the deterministic pieces come from and what has been done about them. 15

16 First ASIC Calibration Pedestals Each storage cell has its own offset value. Measure with no signal linput. These offsets must be removed in order to see a clean(er) signal. We call this pedestal subtraction. 32k pedestals per channel (quarter million per ASIC!) Example: Before pedestal subtraction After pedestal subtraction 16

17 Comparator Transfer Functions Wilkinson comparator. Ramp is supplied to all storage cells. Comparator output fires when ramp exceeds stored voltage. Signals are stored with DC offset to fit into the comparator s dynamic range. Offset varies somewhat for each storage cell. This is what we try to remove with pedestal correction. Comparator response is nonlinear. Example shown for IRS3B comparator pedestal 17

18 AC vs. DC Response, Pulse Persistence Previous slide transfer functions measured with DC inputs. AC response may not be the same! Why not? One example persistence. Voltage has some dependence on previously stored voltage. Example from Eric Oberla, PSEC3 ASIC. This shows a pulse whose ghost persists for one or more cycles after the pulse. The inverse is almost certainly true: a pulse does not reach its full height due to Original pulse Ghost pulse result of writing pedestal voltage onto original pulse 1 cycle later. 18

19 Timing Uncertainties and Timing Calibration Time interval between delay line stages has intrinsic variation. Not accounting for this properly causes significant timing errors Differential (DNL) and Integral (INL) [run-out] Non-Linearity 19

20 One calibration scheme Have tried many, and they each have their merits and drawbacks 20

21 A word of caution (anon) 21

22 Timing Resolution as a Function of Sample Number 75ps 50ps Should be taking a lot of such data and analyzing it to understand timing error contributions Timing resolution as a function of sample number of the threshold h crossing (pulser data). 22 Indicative of noise contributions.

23 IRS3D Improvements over IRS3B 1. Improved Trigger Sensitivity 2. Timebase Servo-locking 3. dt hardware adjust 4. Improved linearity/dynamic range 5. Improved Wilkinson ADC 6. No high current at power-onon = originally reported for TARGET7/X = demonstrated initially (TARGET7/X), detailed timing confirmed = LABRADOR4 independent confirmation = All ASICs since IRS3C 23

24 Trigger Threshold Improvement A significant improvement for smaller pulses where first strike initiation of the MCP charge development is retarded 16x doesn t improve further, as already at the signal-to-noise limit 24

25 Timebase servo-locking (DLL) dttrim= DLL Coarse Tuning Vadj jn (V) Sampling Rate [GSPS] IRSX SST_FB (tap stage) Feedback Tap Number [of 128] Sampling tracks target delay Target sampling rate: 2.8 GSa/s Feedback tap = 121 (indirect RCO feedback mechanism injects asynchronous noise into timebase generator, degrading di timing i performance so this is a significant ifi improvement) 25

26 Time base non-uniformity 2.6 GSa/s 10-15% of dt typical If can correct, reduces processing time dramatically, as this is the most computationallyintensive aspect of fast feature extraction 26

27 Roughly Adjusted dt Sampling 27GSa/s 2.7GSa/s Sampling not working 3.2GSa/s Simple, linear dt slew correction Still room for improved tuning Sample # Sample # 27

28 Observed IRSX noise ~1.4mV Non-gaussian distributions expected for small noise amplitude due to non-linearity in Gray-code least count Take away message: noise is comparable, or better than IRS3B, and acquired while sampling continues to run 28

29 IRS3B IRS3D 29

30 Improved Residuals, repeatability Note: IRS3D -- no comparator bias tuning yet done ~1% Integral deviation from 3 rd -order over key sensitivity range Shape repeatable samplesample (common lookup table, with only pedestal offset) 30

31 Useful Diagnostic tool Quite sensitive to yuckiness in the data 31

32 Improved Wilkinson cross-feed IRS3B Broadening at the extrema Breakdown of simple ellipses expect otherwise Kinks/inflections i hard to manufacture without some type of digital interference kinks IRS3B broadening Broadening is AC noise In vernacular of CTA colleagues pinch-off kinks Much improved some additional improvement expected with linearity correction 32

33 Result: visually nicer waveforms IRS3B Difference most evident at the extrema of the waveforms jumps IRS3B compression 33

34 IRS3D timing (no detailed timebase calibration) 60 ~31ps RMS timing difference 50 (2 edges) 40 Single edge timing: ~22ps RMS Net timing difference (Ch.7 Ch. 4) [ns] Sing gle photon timing [ps] Single Photon Timing Electronics Contribution [ps] 40ps TTS 35ps TTS For stretch goal of <= 50ps single p.e. timing, the electronics contribution should be <= 36ps for 35ps MCP-PMT TTS (best case) [<= 30ps for 40ps MCP-PMT TTS (worst case)] IRS3D looks capable of achieving this goal. 34

35 Summary Day 3 Final batch of detailed information presented Hopefully useful All of these concepts are straightforward, though much, much, much to be assimilated il all at once Typically 3+ times through needed to get it Essential issues to be addressed d for quality mtc data-taking: Are register configurations/feedbacks being set properly? Can we tell ll? (meaningful DQM tools?) Understanding what is being done? Calibration! (and diagnostics) 35

36 Back-up slides 36

37 Resources (where to find more) Hardware: IRS3B webpage: Board stack schematics: phys hawaii edu/~mza/pcb/itop/carriers/index.html (Interconnect) Firmware: References link: hawaii homepage html Repositories: Software: Will talk about next time:

38 Simplified IRS3B Block Diagram Input Analog Input Sampling SA1 (64) SA2 (64) Transfer A1 (64) B1 (64) A2 (64) B2 (64) Storage W0 W4 W508 W1 W2 W3 W511 Readout x8 12 bit counters (x64) Ramp Generator Timing Generator Per channel: Single input line Common to all channels: 128 sampling cells/capacitors Timing generator 256 transfer cells/capacitors Ramp generator 32,768 storage cells/capacitors 64 counters used to digitize 64-samples in parallel 38

39 mtc Readout 3 DSP_cPCI IRS3B sampling ASIC 12 DAQ fiber transceivers 1,536 channels ch. ASICs 12 SRM board stacks 12 SCROD CAJIPCI clock, trigger, programming g 39

40 Example window buffer mgmt Laser fired randomly with respect to FTSW clock but at a fixed time relative to the global trigger. Example 1: t hit PiLas TrigIn PiLas Fires System Trigger (CAMAC TDC start) 21 MHz FTSW Trigger Issued (CAMAC TDC stop) t FTSW Smaller t hit larger t FTSW 40

41 Understanding Expectations: IRS3B toy Monte Carlo Vpeak Risetime Sampling rate nom dt nom dv 100 ADC 2.7 ns 2.72 Gsa/s ns ADC/sample 40% CFD ratio: Applied between 2 points on leading edge that bracket this transition ssnr = dv/noise Leading Edge time [ns] ~44ps for 100mV peak, 2mV noise 41

Prospect and Plan for IRS3B Readout

Prospect and Plan for IRS3B Readout 1. Progress on Key Performance Parameters 2. Understanding limitations during LEPS operation 3. Carrier02 Rev. C (with O-E-M improvements) 4. Pre-production tasks/schedule