Design and Performance of an Automated Production Test System for a 20,000 channel single-photon, sub-nanosecond large area muon detector

Transcription

1 Design and Performance of an Automated Production Test System for a 20,000 channel single-photon, sub-nanosecond large area muon detector A Thesis submitted to the graduate division of the University of Hawaii at Manoa in partial fulfillment of the requirement for the degree of Master of Science In Electrical Engineering October 2016 By Bronson Riley Edralin Thesis Committee Gary Varner: Chairperson Galen Sasaki Victor Lubecke

2 Contents Abstract Acknowledgements 1. Introduction 2. KL and Muon: Detection and Readout 2.1 The KL and Muon detector (KLM) 2.2 The KLM Readout System 2.3 Required Specifications KLM Readout System TARGETX ASIC 2.4 Motivation for an Automated System 3. Calibration of the TARGETX ASIC ADC 3.1 Architecture 3.2 Timing Generator and its Timing Registers 3.3 Optimization of the Timing Registers 4. Characterization of the TARGETX ASIC ADC Combined with Readout System 4.1 Pedestals 4.2 Noise 4.3 Linearity 4.4 Fit Quality 4.5 Timing Resolution 4.6 Trigger Scan 5. Design of Automated Production Test System 5.1 Architecture 5.2 Tests 5.3 GUI 5.4 Instrument Control 5.5 Ethernet Driver 5.6 Serial Numbering and Logging in a Database System 5.7 Parallel Processing to Reduce Testing Time 6. Results 6.1 Trigger Efficiency 6.2 KLM Event Timing 6.3 KLM Trigger Timing 6.4 Production Test Yield 7 Summary and Future Work 8 Bibliography

3 A Abbreviations

4 Abstract

5 Acknowledgments I would like to acknowledge the University of Hawaii at Manoa (UH Manoa) Instrumentation Development Laboratory (IDLab), and the KEK group for supporting this work. I would also like to thank my research advisor, Dr. Gary Varner, for his support and guidance throughout my time with IDLab. Without the opportunity, I would have never been able to work on complex systems such as this. Much thanks to Dr. Isar Mostafanezhad for his leadership and work on the firmware and software. I would also like to thank Xiowen Shi for his work on the hardware and Chris Ketter for his work on the mechanical design. Thank you Matt Andrew for contribution to some hardware design as well. Thank you everyone who have contributed by using the automated software to test all the KLM electronics that include over 1500 TARGETX ASICs, 150 MotherBoards, 150 SCRODs and 150 RHICs. Some notable testers include Mengyuan Jerry Wu, Kunliang Xiao, Dr. Xiaolong Wang (Virginia Tech), Alfredo Gutierrez (Wayne State), Weng Lam Sio, Cara Van De Verg, James Bynes, Vihtori Virta, Khan Le, Eduardo Casimiro Sanches Tanizaka (University of Sao Paulo), Denise Aliny, Julien Cercillieux and Vani Kalapclev. I must also thank our collaborators, such as PNNL, KEK, Indiana University and Virginia Tech, on this project. I have been very fortunate to be surrounded by knowledgeable and helpful individuals working in IDLab. These people include Harley Cumming, James Bynes, Peter Orel, Andrej Seljak, and everyone else. I would like to take the time to thank the members of my thesis committee, Dr. Galen Sasaki and Dr. Victor Lubecke for their time, instruction and guidance. I would also like to thank the rest of my professors such as Dr. Wayne Shiroma for all that I learned at UH Manoa. I would also like to thank my family for influencing and shaping me into who I am today: My parents Francine and Patrick Edralin; My brothers Chad, Kyric, and Royce Edralin. Lastly I would like to thank my loving wife, Joann Edralin, who has supported my dreams and aspirations to become the best I can be. Thank you and I love you.

6 1 Introduction

7 2. KL and Muon: Detection and Readout 2.1 The KL and Muon detector (KLM) Fig. Upgraded Belle II spectrometer (top half) vs present Belle detector (bottom half) [Belle II 14]

8 (a) (b) (c) (d) Fig. (a) This represents the ENDCAP module which consists of scintillators. (b) This a picture of the BARREL module which consists of scintillators and RPCs. (c) The KEKB particle accelerator is in a form of a ring which has about a 3km circumference reaching a world record in instantaneous luminosity of 2.11 x 1034 cm-2s-1 [ (d) This picture represents the overview structure of the detector where the ENDCAP has 14 layers, 4 sectors WLS fiber scintillators (75 x, 75 y) and the BARREL has 15 layers, 8 sectors.

9 2.2 The KLM Readout System Fig. Some of the KLM electronics can be seen installed within the red circle [Isar]. Fig. KLM electronics are shown installed here [Isar].

10 Fig. Readout can be done through USB, PocketDAQ or Ethernet.

11 2.3 Specifications KLM Readout Module In order to get 20k Scintillator channels, 132 modules are required for the KLM scintillator subdetector where each module covers up to 150 scintillator bars or channels with MPPC readout. Each module consists of: 1x KLM Motherboards Chassis for daughtercards and SCROD 1x KLM Ribbon Header Interface Card (RHIC) Provides MPPC bias, slow control, and routes signals to or from MPPCs to Motherboard 1x KLM SCROD Rev A System Control and Readout Module 10x TARGETX Daughtercards Full waveform sampling/digitizing TARGETX ASIC with 1 GSa/s and 16 channels per daughtercard Fig. Key hardware components and locations [Isar]. Some of the specifications for the KLM Readout Modules can be seen below. Table: KLM Readout Module Specifications. Parameter Value Scintillator channels ~20k TARGETX ASICs (including daughtercards) 1250 Channels per ASIC 16 9U VME Motherboards 132 Endcap Layers 14 Endcap Segments 4 Modules per Endcap 56 Barrel Segments 8 Barrel Layers 15 Modules in Barrel 32 Sample Rate (Gsa/s) 1.0 Single Sample Resolution (bits) 10-12

12 2.3.2 TARGETX ASIC The TARGETX ASIC was designed from Dr. Gary Varner at UH Manoa in IDLab and later fabricated in the TSMC 250nm process. It functions as an advanced ADC that is able to sample radio frequency (RF) signals at 1 GSa/s. A storage array of 512 sets of 32 memory storage cells per channel means there is 16,384 memory storage cells per channel. With this amount of storage per channel, the TARGETX is able to store up to 16.3 us depth. Trigger encoding was used for reducing the number of pins. Table: TARGETX ASIC Specifications Parameter Value Channels 16 Sampling rate 1 GSa/s Channels per ASIC 16 Sampling Array 2x32 Storage Array 512x32 Input Noise 1 mv DC RMS dynamic range 11 bit effective Signal voltage range 1.9 V LVDS sampling clock speed ~16 MHz LVDS digitization & readout clock ~64 MHz (16 chan at once) Single Sample Resolution (bits) 10-12

13 2.4 Motivation for an Automated System There is definitely an overhead associated with designing an automated production test system, but it is well worth the time for the following reasons. For one thing, automated tests are consistently conducted each time compared to it being manually done. Plus the user does not have to physically be there while testing is in motion since results may just be viewed after the test is done. Manual testing may also take more time compared to automated testing and it is also more prone to human-error. More testing time may also translate into more cost for human labor. More in-depth tests could also be done if it is automated since it will take less time compared to it being manually done. There is a definite need for an automated production test system for each KLM Readout Module since there are 132 of them plus 20 spares needed.

14 3. Calibration of the TARGETX ASIC ADC 3.1 Architecture The TARGETX ASIC is a 16-channel transient waveform recorder initially designed to monolithically and inexpensively instrument large deployments of semiconductor photon detectors for large neutrino and muon detectors. The very general nature of the signal recording, the narrow digitization selection window and fast single conversion make it useful in a number of applications. In order to support large arrays, self triggering capabilities have been incorporated to permit event-of-interest identification as well as data sparsification. Fig. Operational overview [datasheet]. It was intended for detectors with the need for sampling rates of Giga-samples per second (Gsa/s). Triggered readout rates can reach up to 100kHz depending upon occupancy, sample resolution and serial readout speed. Each channel has 512 groups of 32 storage cells called windows or 16,384 storage cells available. Serial Config is internal of the chip where the user can program all the registers serially that will keep the chip functioning properly.

15 3.2 Timing Generator and its Timing Registers Driven by the SSTin input LVDS signal, the configurable Timing Generator provides all the timing signals necessary for the chip to operate smoothly where it provides continuous sampling and transferring to a larger storage array bank in groups of 32. While one group of 32 in the sampling stage are busy acquiring new data, the other group of 32 in the sampling stage is buffering its data and transferring it into the storage array. The sampling speed of the TARGETX can be controlled by adjusting VadjP and VadjN voltage lines. Inside the chip, a starved-inverter chain provides delays that are used as timing signals for sampling. Schematic of the base timing generator cell can be seen below. It first starts off with SSPin and SSTin being low, but sampling will start as soon as SSPin is asserted. Later when SSTin is asserted high, the switches will open and the instantaneous value at the input to the switch is then stored on the sampling capacitors. As long as SSPin is asserted sufficiently far in advance, which is typically 8ns or more, and stays valid until after SSTin has passed, SSPin itself is not timing critical. Therefore, the rising edge of the SSTin is the defining timing signal and much effort must be made to ensure its integrity. 64 delayed versions of the SSTin is generated with the desired delay within the TARGETX delay x64. The delay line loop feedback adjusts VadjN for optimum sampling by comparing the SSTin and SSToutFB phase, which is connected to a charge pump whose strength is determined by the Qbias value. An external capacitor stores the value of VadjN. Fig. Sample Timing Generator

16 In order to provide seamless sampling, the strobes SSPin and SSTin must be repeated with a sequential selection of the Write addresses and transfer of those signals into storage with the Write Strobe (WR_STRB) signal. The timing diagram below shows an example for data acquisition at 1GSa/s. WR_ADDR_INC also plays a role in the address selection of the storage cells for transferring from the sampling block to the storage block in groups of 32. Change the timing diagram to include SSPin. Fig. Timing Diagram of the data acquisition for the TARGETX [datasheet]. 3.3 Optimization of the Timing Registers The timing registers, that must be optimized, can be seen in the table below. Table: Timing Registers to be optimized. Register Name Register Number Register Value SSPin LE 64 SSPin TE 65 WR_ADDR_INC1 LE 66 WR_ADDR_INC1 TE 67 WR_STRB1 LE 68 WR_STRB1 TE 69 WR_ADDR_INC2 LE 70 WR_ADDR_INC2 TE 71 WR_STRB2 LE 72 WR_STRB2 TE 73 SSToutFB 75

17 Manually setting each timing register with an arbitrary value and then viewing the waveform to see if it looks better may take forever to do. An automated approach must be taken to fix this. An algorithm was created and implemented in python to exactly that. The default register values must be loaded before running the test. Then a timing register can be programmed serially with an arbitrary value. Then a SINUSOID waveform can be fed into the input of the ASIC. The waveform will be sampled, digitized and later read out. A fit must be made 4. Characterization of the TARGETX ASIC ADC 4.1 Pedestals 4.2 Noise 4.3 Linearity 4.4 Fit Quality

18 4.5 Timing Resolution 4.6 Trigger Scan 5. Design of Automated Production Test System 5.1 Architecture 5.2 Tests 5.3 GUI 5.4 Instrument Control 5.5 Ethernet Driver 5.6 Serial Numbering and Logging in a Database System 5.7 Parallel Processing to Reduce Testing Time 6. Results 6.1 Trigger Efficiency 6.2 KLM Event Timing 6.3 KLM Trigger Timing 6.4 Production Test Yield

19 7 Summary and Future Work 8 Bibliography

20 A Abbreviations UH Manoa University of Hawaii at Manoa IDLab - Instrumentation Development Laboratory KEK High Energy Accelerator Research Organization in Tsukuba, Ibaraki Prefecture, Japan KLM - KL and Muon detector ASIC - Application Specific Integrated Circuit TARGET TeV Array Readout GSa/s Electronics with Trigger TARGETX Generation X in TARGET series MCP - Multichannel Plate UV - Ultraviolet ENC - Equivalent Noise Charge OTA - Operational Transimpedence Amplifier MOSFET - Metal-Oxide-Semiconductor Field Effect Transistor NASA - National Aeronautics and Space Administration LNA - Low Noise Amplifier FET - Field Effect Transistor