Table. J. Va vra,

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Francis Banks
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1 J. Va vra, Table - Charge distribution spread in anode plane - Size of MCP holes - MCP thickness - PC-MCP-IN and MCP-OUT-anode gaps - Pad size and the grid line width - Photocathode choice 1

2 Table ~5 mm (?) 5 mm 2 mm 5 mm 6-7 mm 0.75mm 6µm.75mm 1 mm 6 mm x 6 mm 2 mm x 2 mm 0.25mm * There is a discussion on the following pages about each variable 2

3 MCP-PMT Operation photon Faceplate Photocathode E MCP Photoelectron d ΔV 1 ~ 200V Dual MCP ΔV 2 ~ 2000V Gain ~ 10 6 E(x,D,ΔV 2,ΔV 3,Gain) D ΔV 3 ~ 200V Anode x 3

d = 6 mm: PC-MCP-IN gap d C. Field et al., NIMA 553(2005)96-106 By reducing the d, one reduces a diameter of recoiling photoelectrons, which creates a tail.

4 d = 6 mm: PC-MCP-IN gap d C. Field et al., NIMA 553(2005) By reducing the d, one reduces a diameter of recoiling photoelectrons, which creates a tail. However, reducing this gap also reduces the effective size of the MCP-PMT (the outer pads are cut off): d = 0.75 mm: For a ps TOF counter a loss of effective area may not matter. I recommend smallest possible size (d = 0.75mm) to eliminate tails, which may be a bigger evil. 4

5 The anode charge distribution Approximate estimate: If the ratio of E MCP /E(x,D, ) is large, the field lines will flare out. Following the Gauss law: if E MCP ~10kV/cm, MCP pore size is 25µm, ΔV 3 ~200V, and D ~ 5mm and E(x,D, ) ~200V/0.5cm = 400V/cm, we are expecting a spot size on anode of ~(10000/400) x 25µm ~ 625µm < 1mm. It is very small!!! Making D smaller and E(x,D, ) larger, makes it even smaller. This invites inefficiency!! Exact treatment: Ramo theorem: the instantaneous current I i flowing into one particular electrode i due to a motion of charge q at position r with a velocity v( r), can be calculated using an equation: I i = -q [ v( r). E( r)]/v i where E( r) = V( r) is field created by rising the electrode i to a potential V i while grounding all other electrodes. Therefore, to calculate the charge spread, and therefore be able to design the anode strip width, we need to know the electric field distribution E( r). In practice, to calculate the electric field between the MCP and the anode correctly, one needs the Maxwell electrostatic program, which can handle insulators. Then use RAMO theorem to calculate current through each pad. I think to do it right is a big effort. 5

MCP-OUT-anode gap D, pad size and grid width Charge spread Anode pad design: Based on the Gauss law argument on the previous page, I assume that the avalanche charge distribution at the anode is <1mm

For the multi-photoelectron detection, as one has in the TOF counter, one is better off, but still one does not want to lose too many avalanches!

6 MCP-OUT-anode gap D, pad size and grid width Charge spread Anode pad design: Based on the Gauss law argument on the previous page, I assume that the avalanche charge distribution at the anode is <1mm in diammeter. For the single photoelectron detection, I would worry about the inefficient gaps in the anode structure when pushing for small pad size or large grid size. For the multi-photoelectron detection, as one has in the TOF counter, one is better off, but still one does not want to lose too many avalanches!!! The pad size should not be smaller than 300µm* 12 ~1mm to keep the timing variation within σ ~1ps. However, one may have to relax this requirement in practice. I would choose a design, where a pad size is ~2mm square and the grid line much less than the charge size, i.e., 0.25mm in width. I would keep a distance D so that Burle can insert the getter, which is important. That may keep the present distance of ~5mm (?) Clearly, it needs to be simulated. 6

Nagoya group: Size of MCP holes: 6 or 10 µm? Do not understand why Nagoya people got only σ ~46ps for the MCP-PMT with a 10µm hole for single photo-electrons.

7 Nagoya group: Size of MCP holes: 6 or 10 µm? Do not understand why Nagoya people got only σ ~46ps for the MCP-PMT with a 10µm hole for single photo-electrons. Perhaps, it is due to MCP diameter? I would expect ~30ps based on my measurements with the 64-pad Burle tube. It seems to me that one should try to go for 6 µm MCP hole size. 7

8 Thickness of MCP: 400µm? Nagoya group: What MCP thickness is in the Burle MCP-PMT? Is it also 400 µm? Does it matter for the timing resolution? I would say that it does. It should be as small as possible to limit the timing spread. It seems to me that one should try to go for ~400µm thickness. 8

9 Photocathode: Bialkali or Multi-alkali? Burle info: Pushing the response to the red wavelength region will reduce the chromatic effects Burle is willing to sell this type of the Multi-alkali photocathode for slightly higher price. It seems to me that one should try to go for the multi-alkali photocathode. Perhaps, with a combination with a filter cutting the UV portion away? 9

10 Timing strategy for the single photoelectron signal - Double threshold timing with 2 TDCs - Single threshold with TDC & ADC - Constant-fraction timing with one TDC - Leading and trailing edge timing & Q 10

11 Double-threshold vs. CFD timing (J. Va vra, MCP-PMT log book #1) a) Double threshold timing: b) Phillips CFD timing: It seems to have a similar performance 11

12 Double-threshold vs. CFD timing (J. Va vra, MaPMT log book #1&2) a) Double threshold timing: b) Phillips CFD timing: It seems to have a similar performance 12

13 Single-threshold with ADC correction (J. Va vra, MaPMT log book #1&2) It seems to be equivalent to CFD & double-threshold timing Advantage of ADC: Interpolation between pads -> better pixel resolution 13

14 Prompt ACIS (G. Varner, Univ. of Hawaii) To allow a continuous readout, the samples are not converted, but rather are compared with 2 different thresholds. The timing is performed using a priority encoder to determine the location of the first (last) sample that was on. By determining the trailing edge, a Timeover-Threshold measurement of the charge Q is obtained. 14

15 TOP RICH counter: R&D for Readout ASIC H.Nakano, T.Iijima (Nagoya), H.Ikeda, I.Adachi, S.Nishida (KEK), T.Sumiyoshi (TMU) Time-to-Analog Converter Time resolution <~20ps. Double overlap gates Less dead time (~100ns). 0.35µ CMOS process. TAC-IC Concept INPUT 125ps GATE1 T1 75ps GATE2 AOUT1 AOUT2 T2 V1 = K x T1 V2 = K x T2 40MHz CLOCK 15

TAC-IC Status Test production at VDEC (U.

16 TAC-IC Status Test production at VDEC (U.Tokyo) 1 st batch chip Accommodate 3 types _ C.F.D + TAC L.E.D. + TAC TAC only Work w/ 40MHz clocking. Resolution being measured. H.Nakano, T.Iijima (Nagoya), H.Ikeda, I.Adachi, S.Nishida (KEK), T.Sumiyoshi (TMU) overlap of 2 gates 2 nd batch chip being submitted. Some debugging Aim at higher clocking rate. V2 V1 16

17 Timing strategy for the multi-photoelectron signal - Single threshold with TDC & ADC - A combination of CDF & TDC 17

18 Multi-photoelectron timing resolution Nagoya group: They had ~45 photo-electrons and got σ ~6.2ps with TDC & ADC correction. The intrinsic electronics resolution : σ ~4.7ps. 18

19 A ps TOF counter (H. Frisch & H. Sanders, Univ. of Chicago) A combination of CFD & TDC 19

20 Focusing DIRC R&D (J. Va vra et al., to be published in NIM) A combination of CFD & TDC 20

Study of Timing and Efficiency Properties of Multi-Anode Photomultipliers

Study of Timing and Efficiency Properties of Multi-Anode Photomultipliers T. Hadig, C.R. Field, D.W.G.S. Leith, G. Mazaheri, B.N. Ratcliff, J. Schwiening, J. Uher, J. Va vra Stanford Linear Accelerator