Conceps and trends for Front-end chips in Astroparticle physics

Transcription

1 Conceps and trends for Front-end chips in Astroparticle physics Eric Delagnes Fabrice Feinstein CEA/DAPNIA Saclay LPTA/IN2P3 Montpellier

2 General interest performances Fast pulses : bandwidth > ~ 300 MHz sampling > ~ 1 GHz High rate : minimal dead time < ~ 5 µs, derandomization Sensitivity : dynamical range > ~ 16 bits 1/10 SPE -> 5000 SPE minimal cross-talk < 1% Low power, reliable : 0.35 µm techno. < ~ 500 mw/channel Cheap : integrate ADC,... Minimal digital output : integrate logic

3 Technical solutions tried and used implemented improvements more to come dreams

4 Dynamical range need 16 bits from 1/10 photo-electron for calibration to 5000 PE for high energy for AUGER North, in Orsay (LAL and IPNO) 0.35 µm CMOS front-end 3 gains : MHz analogue BW 16.6 bits dynamic with 10 b. FADC other solutions : 3 gains readout : Icecube, ANTARES 2 gains : 1 to 25 on anode signal : HESS

5 ADC/TDC solution Smart pixel (Heidelberg) : 2 gains, 1 time / trigger 2 integrators + 1 Time to Ampl. Converter -> 3 charges 16 pixels multiplexed on 10 MHz FADC : 8 µs readout DTime prototype advantages : modular, low dead time drawback : 20 ns integration, no info on pulse shape

6 Sampling techniques FADC : standard but expensive and power consuming (clock)² Array of switched capacitors : ex. : Analog Transient Waveform Recorder 1992 when switch open, charge on capa. prop. to instant voltage sampling : time for open signal to travel to next switch

7 Digitization techniques waveform stored in array -> need to digitize serial readout with external FADC or fast ADC fast but expensive serial readout with internal ADC slower, cheaper parallel readout with common ramp ADCs limited by ramp speed, then serial digital output

8 Improvements loop sampling stopped by trigger : stable, saves delay line Analogue Ring Sampler 1997, CEBAF, used by HESS I Domino RS 1999, used by MEG, Magic AMS CMOS 0.8µm LABRADOR used by ANITA matrix instead of line, can read only part of sampler Matacq 1999, SAM 2004, many users, developped industrialised for HESS II by CAEN camera AMS CMOS 0.35µm

9 SAM results PMT-like pulse 1 GS/s SPE spectrum, 12 cells integration, with a HESS PMT 0.1 SPE to 5000 SPE 16 bits dynamics 6000 chips produced now series test beg for HESS II camera electronics

10 t ) u e o h m c a a m at a D e a & r R g g n p o m n M u 4 o 2 S C The system on a chip The ARS1 chip used by ANTARES Time ref. clock Sampling control Waveform mode control ADC manager Dyn. 2 Dyn. 1 Anode Waveform mode 4*128 memory cells (ARS0) ADC ADC erts et ni Readout Serial link Flip-flop + Comp. - PSD manager & L0 trigger SPE mode Charge integrator SPE mode TVC et mi oti ni T ti nit b- at SPE mode Pipeline Analog memory cells 24-bit memory registers Pipeline control trigger L1, L2 manager DACs, registers, configuration interface, Slow control ats( Slow control Serial link L1 trigger L2 trigger Time ref. clock & Synchro

11 Derandomization Events occur with Poisson statistics ATWR : flip-flop between two chips -> (DT)² ARS : analogue/digital FIFO array of 16 memories : charge time time stamp charge time time stamp... charge time time stamp charge time time stamp with asyncronous write and read accesses -> no dead time until readout speed

12 Data compression waveform -> arrival time and charge : data flow / 10 to 20 but pile-up corrupts information -> discriminate : simple shape -> send only time and charge complex shape -> send full waveform analogue pulse shape discri. before digitization -> ARS1 detects large, wide and double pulses numerical discri. after digitization : in FPGA or fast processor

13 A hand held oscilloscope PIPELINE is a system on a chip including a similar SCA CEA/CNRS design The METRIX oscilloscope uses very few other components

14 More coming WILKI : new 16 common ramp ADC in Saclay initially designed for HESS 2 in SAM chip tested 12 bits conversion in 1,2 µs! 3.4 GHz virtual clock => being patented SAM chip versions with : ADC in chip memory depth extended to several 1000 cells readout of several cells in one cycle -> automatic integral as in ARS1 dead-t. free with simultaneous R/W and readout < 60 ns integrate a FIFO integrate some programmable logic, even a µ processor

15 Summary, conclusion analogue BW :80 MHz -> 300 MHz (800 MHz without buffer) technology : 1.2 µm -> 0.8 µm -> 0.35 µm CMOS freq. range : GHz -> 10 Hz 3 GHz dead time : 250 µs -> 2 µs sensitivity : output : 8b -> 12b analogue -> digital applications : neutrino -> gamma, showers GREAT FUTURE FOR FRONT-END CHIPS

16

17 What we learn from the ARS1 Not all features used in chip : hard to develop, test and tune, external components Some functions should be kept, evolved or dropped Trigger, discriminator, counting functions : many cross-calibrations too many pins on signal (impedence match) => should be done externally Many Slow-Control parameters (73 for ARS1) too heavy to use => technology spread should be minimized by design

18 Evolutions SCALE chip being designed in Saclay Waveform and time/charge : can be done by same sampler Pulse shape info : useful online Derandomization, flip-flop : analogue FIFO and flip-flop in same chip ADC in chip causes asyncronous digital output : digital FIFO in the chip, slave to digital front-end