Matching Components (minidsp_a) Description. 4x Decimation (Stereo) 4x Decimation (Mono) MonoDec4xIn. 2x Decimation (Stereo) 2x Decimation (Mono)

Transcription

1 Interpolator Overview The first component of any process flow is the Framework. After that the user may determine that interpolation and/or decimation filters are required in their design. The following table lists (under Matching Components ) the associated stereo Interpolators and Decimators for each Framework. Additionally, there are single channel versions of each Interpolator and Decimator (prefaced with Mono ) available. Framework Name Sample Rates Supported (Fs) Kbps Matching Components (minidsp_a) Matching Components (minidsp_d) AIC3254 8x4x/ AIC3262 8x4x 32, 24, 22.05, 16, Dec4xIn Mono AIC3254 4x2x/ AIC3262 4x2x 96, 88.2 Dec2xIn MonoDec2xIn 2x Decimation 2x Decimation Mono AIC3254 2x1x / AIC3262 2x1x 192, Dec1xIn MonoDec1xIn 1x Decimation 1x Decimation Int2xOut, MonoInt2xOut 8x4x Synch Mono 4x2x Synch 96, 88.2 MonoDec2xIn 2x Decimation Mono 2x1x Synch 192, MonoDec1xIn 1x Decimation Int2xOut MonoInt2xOut 8x4x Asynch Mono 4x2x Asynch 96, 88.2 MonoDec2xIn 2x Decimation Mono

2 8x4x Asynch ADC3x01 4x ADC3x01 2x 96, 88.2 Dec4xIn Dec2xIn MonoDec2xIn Mono Not Applicable Not Applicable 2x Decimation Not Applicable Not Applicable Dynamic Range Compression (DRC) Feature All Interpolators may include a DRC feature in the DAC channel. This is hardware DRC and its parameters can be set on Runtime Properties window. Include_DRC Design time property has to be set to YES for hardware DRC to become active. The DRC algorithm works independently for Left and Right DAC channels. The DRC serves to limit the digital gain provided to the DAC data so as to limit the output data when it is expected to exceed beyond a specified threshold. The rate at which the DRC decreases or increases the gain according to variations in the input amplitude or programmed gain is limited by the attack and decay parameters specified by the user through control registers. Figure: Combined transfer function of the DRC and PGA

3 Configurable Properties (Design Time) Property Scaling Include_DRC YES or NO Enables and Disables DRC Configurable Properties (Run Time) Property Permitted Values DRC_Enable YES / NO DRC Enable or Disable. Make sure to set Include_DRC in Design Time Configurable Properties to YES to activate the DRC block. Volume_Control_dB -63.5dB to 24dB Digital Volume Control. Programmable gain of a digital volume control block that can control the volume of the playback signal from +24dB to 63.5dB in steps of 0.5dB. Default value is 0dB. Performance of DRC can become more noticeable if this value is set very high. Energy_Time_Constant_ms 1 to 350 ms Used in the signal energy calculations by DRC. Only effective when Include_DRC is YES DRC_Hyteresis 0dB, 1dB, 2dB, 3 db It can be programmed to values between 0dB and 3dB in steps of 1dB. It is a programmable window around the programmed DRC Threshold that must be exceeded for a disabled DRC to become enabled, or an enabled DRC to become disabled. For example, if the DRC Threshold is set to -12dBFS and DRC Hysteresis is set to 3dB, then if the gain compression in the DRC is inactive, the output of the DAC Digital Volume Control must exceed 9dBFS before gain compression due to the DRC is activated. Similarly, when the gain compression in the DRC is active, the output of the DAC Digital Volume Control needs to fall below -15dBFS for gain

4 compression in the DRC to be deactivated. The DRC Hysteresis feature prevents the rapid activation and de-activation of gain compression in the DRC in cases when the output of DAC Digital Volume Control rapidly fluctuates in a narrow region around the programmed DRC Threshold. By programming the DRC Hysteresis as 0dB, the hysteresis action is disabled. Recommended Value of DRC Hysteresis is 3 db. DRC_Threshold_dBFS -24dB to -3dB DRC threshold. Level of signal at which gain compression becomes active. DRC_HOLD_Time_WordCLK 0, 32, 64, 128,..,128x4096 DRC hold time in word clocks. DRC Hold is intended to slow the start of decay for a specified period of time in response to a decrease in energy level. DRC_Attack_Rate_perWCLK DRC_Decay_Rate_perWCLK HPF_n0 HPF_n1 HPF_d1 4dB, 2dB, 1dB, 1/2dB,, 1/4096dB 1/64dB, 1/128dB, 1/256dB,.., 1/ dB DRC attack rate per DAC word clock. When the output of the DAC Digital Volume Control exceeds the programmed DRC Threshold, the gain applied in the DAC Digital Volume Control is progressively reduced to avoid the signal from saturating the channel. This process of reducing the applied gain is called Attack. DRC decay rate per DAC word clock. When the DRC detects a reduction in output signal swing beyond the programmed DRC Threshold, the DRC enters a Decay state, where the applied gain in Digital Volume Control is gradually increased to programmed values. High pass filter coefficient n0 High pass filter coefficient n1 High pass filter coefficient d0

5 I2C Interface I2C Address I2CAddress1 I2CAddress2 I2CAddress3 I2CAddress4 I2CAddress5 DSP Memory Address Size DSPCoefBlockStart1 4 DSPCoefBlockStart2 4 DSPCoefBlockStart3 4 DSPCoefBlockStart4 4 DSPCoefBlockStart5 4 Alpha 1minus2alpha HPF_n0 HPF_n1 HPF_d1 Alpha and 1-2alpha are DRC energy filter coefficients; they are calculated by Energy Time Constant.