BUILT-IN SELF-TEST BASED ON TRANSPARENT PSEUDORANDOM TEST PATTERN GENERATION. Karpagam College of Engineering,coimbatore.

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1 Volume 118 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu BUILT-IN SELF-TEST BASED ON TRANSPARENT PSEUDORANDOM TEST PATTERN GENERATION 1 Manikandan.S, 2 Kamalakkannan.G, 3 Logesh.R, 4 Pradeep.S, 5 Madhan.S 1. Assistant Professor, Department of Electronics and Telecommunication Engineering, Karpagam College of Engineering,coimbatore. 2,3,4,5 UG Students, Electronics and Telecommunication Engineering, Karpagam College of Engineering. 1 mailingtomani@gmail.com, 2 wannamailkamal@gmail.com, 3 logeshete18@gmail.com, 4 pradeep1110@gmail.com, 5 smadhan1209l@gmail.com Abstract: To detect the circuit is defect or not by using BSIT to consumption the power and area.to test whether the given circuit is original or duplicate by using BSIT. These technics is based on weighted pseudorandom test pattern generation. Random single input change pattern (RSIC) test generates the low power test patterns to overcome the high-level defect. It consumed more area and power. The LFSR generation circuit is too complex to reduce fault detection occurrence level. To overcome the existing method by using 2-bit inverted LFSR.In simulation method we are implementing Xilinx software to test the circuit. The 2- bit inverted LFSR has more efficient when we compare with the weighted LFSR. Keywords: BIST, LFER, 2-bit inverter. 1. Introduction In built-in self -test method we were checking the value by using weighted pseudorandom test pattern generation (2). In additional we added the transparent method. it means 2-bit inverted linear feedback shift register. It will reduce the power and area. It is mainly used in complementary machines, integrated circuits product industries, automotive electronics industries and medical devices industries.etc.. By using 2 bit inverted linear feedback shift register in built-in self-test method we can overcome the drawbacks like getting the compliment circuits the power and area.in this method Built-In Self-Test we can check the fault coverage and original coverage.in the proposed method we included the transparent pseudorandom test pattern generation.transparent means 2 bit inverted linear feedback shift register, reflected the values in contra. 2. Working Principle In this method we are checking the circuits in the CUT (circuit under test).platform.it will check the input values by BIST (Built-In Self-Test)(1).It has multiplexer used to reduce the switching activities. When the input values given to the circuit under test in the way of pseudorandom test pattern. it will giving the weighted random values to the circuits or chips.(4) When we were using a weighted random values in the circuit. It will getting power and circuits are getting large and area will be increased. So that transparent method were adding to this 2-bit inverted LFSR (linear feedback shift register) instead of normal LFSR (linear feedback shift register). When the values were stored in output register and generating the values should be taken from the stored output.we were using a comparator.it has XOR gate used to compare the actual output and original output values in it.we can reduce the complexity of circuit and power 3. Existing Method In this existing method we havecheck the value neither original value nor fault value Fig 2.In the method of BIST (built-in self-test).circuit or chip fitted to CUT(circuit under test) platform and input register giving the value to the CUT.It evaluate the values and store the values in the output register.we cannot able check the all test values. So that we use pseudorandom test pattern generator.it will generates the values 0-9 only.if we use 2 digits or more to check the values.it means weighted values are given to the pseudo random test pattern generation.the LFSR (linear feedback shift register) circuit become large and complexity of circuit.so that it consumption power for that circuit and taking area also. 505

2 Figure 1. BIST method circuit 4. Block Diagram so that we used a PRPG (pseudorandom pattern generator).in this generator LFSR(linear feedback shift register) is main part, it will generates the random values.if we use the large number of digits to check the values that time it will acted as weighted LFSR.It will get the complex circuit and get the area instead of the weighted LFSR we use the 2-bit inverted LFSR. Figure 3. Block Diagram of BIST 5. Proposed Method In this paperfig 3 we have used the BIST (built-in self test) method.to check the circuit or chips are apt for the original character(3).it is process done continuously Figure 2. LP BIST 506

3 In this process called transparent method(9). It will be reversing the value 0 and 1.It depends upon user desire value. It can check the large number of random values in it. It will reduce the power and area and the time will be reduced 6. Methodology A new LP weighted pseudorandom test pattern generator using weighted test-enable signals is proposed using a new clock disabling scheme (7).Our method generates a series of degraded sub circuits. Fig 2 the new LP BIST scheme selects weights for the testenable signals of all scan chains in each of the degraded sub-circuits, which are activated to maximize the testability.(11) A new LP deterministic BIST scheme is proposed to encode the deterministic test patterns. Only a part of flip flops are activated in each cycle of the whole process of deterministic BIST. A new procedure is proposed to select a primitive polynomial and the number of extra variables injected intothe (LFSR) linear-feedbackshift register that encode all deterministic patterns. The new LP reseeding scheme to cover a number of vectors with fewer care bits, which allows a small part of flip flops to be activated in any clock cycle. frequency are set to 1.5 V and 200 MHz, respectively. The column s peak (mwah, before) and lp peak (mwah, after) show thepeak power for the original deterministic BIST and weighted test-enable-based PRPG, and the proposed LP BIST method.(12) The column rate (%) shows the percentage of peak power for the proposed method compared with the one without the LP design for both the weighted pseudorandom test generation phase and the deterministic BIST phase. (5) Experimental results in Table I show that the proposed LP PRPG phase reduces the peak power to less than 13% for all circuits, and the LP deterministic BIST scheme reduces the peak power to less than 14% in all cases. Experimental results show that the peak power for the PRPG phase is a little more than that for the deterministic BIST phase for the all circuits except s38417 before the LP design is included. This is mainly because only 10% flip flops are activated in any case during the LP weighted pseudorandom testing and the LP deterministic BIST phases 8. Results 7. Advantage The most commonly used linear function of single bits is exclusive-or (XOR)(6). Thus, an LFSR is most often a shift register whose input bit is driven by the XOR of some bits of the overall shift register value.time consumption, By using the pseudorandom test pattern generation method reduces the human work, and using this method, reduces the power consumption Table 1. Power reduction Figure 4. Simulation result of LP BIST 9. Conclusion Table:1 power reduction presents the performance of the proposed LP deterministic BIST scheme on peak power (mille-watt, mwah) reduction when 10% scan chains are activated(8). (10)The supply voltage and A new LP BIST method has been proposed using weighted test-enable signal based pseudorandom test pattern generation and LP deterministic BIST and reseeding. The new method consists of two separate phases: LP weighted pseudorandom pattern generation and LP deterministic BIST with reseeding. The first phase selects weights for test-enable signals of the scan chains in the activated subcircuits. A new procedure has been proposed to select the primitive polynomial and the number of extra inputs injected at the LFSR. A 507

4 new LP reseeding scheme, which guarantees LP operations for all clock cycles, has been proposed to further reduce test data kept on-chip. Experimental results have demonstrated the performance of the proposed method by comparison with a recent LP BIST method. The LP reseeding technique is a little more complicated. This work can be extended to latch-oncapture transition fault testing and small delay defect References [1] F. Brglez, P. Pownall, and P. Hum, Applications of testability analysis: From ATPG to critical path tracing, in Proc. IEEE Int. Test Conf., pp , Nov [2] P. H. Bardell, W. H. McAnney, and J. Savir, Built in Test for VLSI: Pseudorandom Techniques. New York, NY, USA: Wiley, [3] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Courtois, Built-in test for circuits with scan based on reseeding of multiple polynomial linear feedback shift registers, IEEE Trans. Comput.,vol. 44, no. 2, pp , Feb [4] H. K. Lee and D. S. Ha, HOPE: An efficient parallel fault simulator for synchronous sequential circuits, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 15, no. 9, pp , Sep [5] S. Gerstendörfer and H.-J. Wunderlich, Minimized power consumption for scan-based BIST, J. Electron. Test., vol. 16, no. 3, pp , Jun [6] Y. Huang, I. Pomeranz, S. M. Reddy, and J. Rajski, Improving the proportion of at-speed tests in scan BIST, in Proc. IEEE/ACM Int. Conf. Comput.- Aided Design, Nov [7] M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing. Norwell, MA, USA: Kluwer, [8] P. Girard, C.Landrault, S.Pravossoudovitch, A.Virazel, and H.-J. Wunderlich, High defect coverage with low-power test sequences in a BIST environment, IEEE Des. Test Comput., vol. 21, no. 5,pp , Sep./Oct [9] H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, Two-dimensional test data compression for scan-based deterministic BIST, in Proc. Int. Test Conf., Nov [10] P.Girard,C.Landrault,S.Pravossoudovitch, A.Virazel, and H.-J. Wunderlich, High defect coverage with low-power test sequences in a BIST environment, IEEE Des. Test Comput., vol. 21, no. 5,pp , Sep./Oct [11] N. Z. Basturkmen, S. M. Reddy, and I. Pomeranz, A low power pseudorandom BIST technique, J. Electron. Test., Theory Appl., vol. 19, no. 6, pp , Dec [12] M. Chatterjee and D. K. Pradhan, A BIST pattern generator design for near-perfect fault coverage, IEEE Trans. Comput., vol. 52, no. 12, pp , Dec [13] T. Padmapriya and V.Saminadan, Handoff Decision for Multi-user Multiclass Traffic in MIMO- LTE-A Networks, 2nd International Conference on Intelligent Computing, Communication & Convergence (ICCC-2016) Elsevier - Procedia of Computer Science, vol. 92, pp: , August [14] S.V.Manikanthan and D.Sugandhi Interference Alignment Techniques For Mimo Multicell Based On Relay Interference Broadcast Channel International Journal of Emerging Technology in Computer Science & Electronics (IJETCSE) ISSN: Volume- 7,Issue 1 MARCH [15] K. Ramash Kumar, Dr. S. Jeevananthan, Design of Sliding Mode Control for Negative Output Elementary Super Lift Luo Converter Operated in Continuous Conduction Mode, (IEEE conference Proceeding of ICCCCT-2010), pp , /

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