Efficient Test Pattern Generation Scheme with modified seed circuit.

Transcription

1 Efficient Test Pattern Generation Scheme with modified seed circuit. PAYEL MUKHERJEE, Mrs. N.SARASWATHI Abstract This paper proposes a modified test pattern generator which produces single bit change vectors so that switching activity is reduced which inturn helps to test an IC with minimum required. Seed generator circuit has been modified which reduces the area overhead of test pattern generator(tpg) and makes its efficient. The TPG is compatible with test per scan scheme. The paper has been implemented in cadence and all the necessary comparisons have been made. Circuits has been tested with test per scan scheme and necessary comparisons have been made to show reduction in consumption and decrease in area overhead. Index Terms Built-in-self-test(BIST),Seed generator, test per clock, test per scan. I. INTRODUCTION Automatic test equipment (ATE) is generally used to test an IC.But as ATE is costly, it is not always affordable. So testing capability is incorporated in IC itself that is BIST. It is one of the design for testability(dft) technique. BIST makes an IC self testable. Standard BIST architecture consist of test pattern generator(tpg),circuit under test(cut) or design under test(dut) and output data analyser (ODA).Generally there are three different approaches to TPG, exhaustive or pseudo exhaustive test generator method, pseudo random approach and deterministic approach. Disadvantage of exhaustive TPG method is that this method is suitable only for circuits having less number of input bits. If the number of bits are increasing then this method is time consuming. Moreover this method cannot detect bridging fault. So pseudo exhaustive TPG method is proposed where if the circuit is having large number of input bits then we go for horizontal or vertical partitioning so that the total functionality of the circuit is not affected. Pseudo random approach causes more dissipation and causes damage to the circuit[2][3][4].output Data Analyser is used mainly to compress the data at the output and it is matched with the expected outcome to detect whether circuit is faulty or not. Manuscript received April, Fig. 1. Standard BIST Architecture. This paper is based on scan based BIST architecture. Introduction of scan chain makes the circuit more controllable and observable. Each and every point in the circuit becomes testable.we can easily understand whether line is affected or not affected by struck at fault or bridging fault. A. Prior Work So far the BIST technique has been implemented and modified in several ways. One of the approach is to use dual speed LFSR(linear feedback shift register) to reduce the switching activity[5].but disadvantage is here two LFSR are used,one is operated at normal clock and other at slower clock. This approach is further improved by modifying the clock circuit which will provide different speed clock pulses instead of using two LFSR[6].Thus it reduces requirement in the circuit. In other approaches new TPG are proposed to reduce the transition in test pattern and hence the requirement[7][8]. II. TEST PATTERN GENERATION SCHEME The TPG consist of Johnson or SIC, Seed generator circuit, XOR gates, Clock and control circuits. Say there are M scan schains each having scan length l. So l-bit Johnson is required. So vectors generated by Johnson is given by J= J 0 J 1 J 2.J l-1. When the unique Johnson code is generated, it is bit XOR with the seed vector given by S=S 0 S 1 S 2.S M-1. Then the circular shift operation takes place and every unique possible Johnson codeword is generated and bit Xor with seed. The test vectors generated is given by X=X 0 X 1 X 2 X (M-1)l+2. Payel mukherjee, Electronics and telecommunication, SRM university., Chennai,. Tami Nadu India, Mrs N. Saraswathi(Asst Prof), Electronics and telecommunication, SRM university,chennai,. Tami Nadu India 1140

2 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 4, April Initial mode: Here when RJ_Mode is 1 and Init is 0, all the D flipflops in Johnson will be initialized. 2. Circular Shift Register Mode: when RJ_Mode and Init is at logic 1, each Johnson vector will undergo shift operation to generate unique Johnson codeword. 3. Johnson Mode:when RJ_Mode is at logic 0,the Johnson will undergo normal operation and as mod number of Johnson is 2l,it will generate 2l unique Johnson vectors. Fig. 2. Test pattern generation scheme. A. Reconfigurable Johnson Counter Reconfigurable Johnson Counter is preferably used when scan length is less. The reconfigurable Johnson consist of a mux and an AND gate to make it operate in different modes. It has three modes of operation: Fig. 3. Reconfigurable Johnson Counter.. For a 4-bit the analysis is below. Instances cells Cell area Total area Reconfigurable johnson Multiplexer Instances Cells Leakage (nan o Reconfigurable johnson Multiplexer Dynamic (nan o Total (nan o Fig. 4. Implementation results waveform. area(micrometer square)analysis. analysis. 1141

3 A. Scalable SIC Fig. 5. Scalable SIC Counter When scan length is much more than number of scan chain, we go for scalable SIC (single input change) as reconfigurable Johnson increases the area overhead. The SIC consist of adder, subtractor, chain of D flipflops and chain of muxes. Length of shift register must be equal to number of scan chains. It also has three modes of operation: 1. If SE=0, the content of adder is stored in subtractor, when SE=1, count of subtractor is decreased slowly. 2. When SE=1, all D flipflops are not reduced to zeros, atleast one is kept at logic 1 or Number of 1s or 0s needed are shifted into shift register. Instances Cells Cell area (micromete r square) Scalable SIC D flipflop chain Adder Mux chain Subtractor Shift register Total area (micrometer square) Instances Cells Leakage Scalable SIC Counter D flipflop chain Adder Mux chain Subtractor Shift register Dynamic Total Fig. 6. Simulation Result waveform. area analysis. analysis. 1142

4 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 4, April 2014 The above analysis shows the implementation of SIC for scan length of 4 bit. From the analysis it is clear that for shorter scan length Johnson is efficient as it reduces area over head and comparatively consumes less. But for larger scan length, say for l=32, we prefer SIC as it reduces area overhead. If scan length is 32, we need 32 bit Johnson that is it requires 32 D flipflops.but for SIC we need 6 D flipflops for adder, 6 D flipflops for subtractor, 6 multiplexers,6 D flipflops for shift register and some additional gates. For scan length of 32, both Johnson and SIC is implemented and the decrease in area overhead is shown. So for larger scan length SIC is more efficient. Fig. 8. Test Per Clock Scheme. Counter Reconfigurable Johnson Scalable SIC Number of cells used Total cell area(micrometer square) B. Seed Generator Circuit The seed generator circuit is implemented in two different approaches. The mod number of Johnson is 2n, where n is the number of bits. Seed Circuit With Delay Elements: Fig. 7. Table showing reduction in area overhead. A. Test Per Clock (TPC) Scheme The test per clock circuit consist of seed generator circuit. The number of stages of seed generator circuit depends on the scan length. Number of stages should not be less than half of the scan length. According to the scan length, Johnson or SIC is used.test vectors are generated as follows: 1. The Johnson generates unique vector by clocking one time. 2. Seed circuit generates seed vector by clocking one time. 3. Unique test vectors are generated by the XOR operation between seed vectors and Johnson vectors. First approach is to implement the seed circuit with delay elements each providing 2n delay to each flipflops used in LFSR. So seed vector generated with the first clock pulse is held constant for next 2n clock pulses and after XOR operation with each Johnson vector, the seed vector changes in (2n+1)th clock pulse. Seed Circuit With Up: Second approach is to use a frequency divider which is an up and is connected to the clock input of the LFSR.The clock pulse is held constant for 2n times and changes at (2n+1)th time.the implementation result shows that second approach is more efficient compared to previous approach both area and wise. 1143

5 Seed circuit Number of cells used Seed circuit with delay elements Seed circuit with up Total cell area in micrometer square Power Total Fig. 9 seed with delay elements up output acting as frequency divider. seed circuit with up Fig. 10. Table showing reduction in area overhead and consumption. Test per clock scheme is also implemented using reconfigurable Johnson for scan length of 4 using both the the seed generator approaches. The implementation result and the reduction in area and using modified seed circuit is shown below. 1144

6 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 4, April 2014 Instances Test per clock using seed with delay elements. Test per clock using seed with up Number of cells used Total cell area(micrometer square) Power Fig. 11. Simulation Result of Test per clock using Johnson. Simulation Result of Test per clock using SIC. Table showing area and comparision for( TPC using Johnson ) III. TEST PER SCAN (TPS) By test per scan scheme we tests the circuit under test (CUT) or device under test (DUT). Test per scan scheme consist of scan chains,test pattern generator,cut,multiple input shift register(misr) block. The seed generator circuit produces unique seed vector by clocking the circuit.for testing the circuit the seed generator with up is used. The reconfigurable Johnson is operated in all the three modes to generate every possible unique Johnson codeword. After XOR operation between seed vector and Johnson codeword single bit change vectors are generated.these test vectors are given to CUT which should produce the expected outcome and to the scan chain blocks. The output from both scan chain and CUT are given as input to MISR block. A. Scan Chain Fig. 12. Test per scan scheme Scan chain block consist of CUT and chain of D flipflops. Number of D flipflops attached in the scan chain determines the scan length. It has two modes of operation: 1. Scan Mode: Initially the input to CUT is unkhown. So the block has to be operated in scan mode where the D flipflops acts as shift register and accepts the scan data as input. 2. Normal Mode: Now the scan output data act as input to CUT along with the primary inputs. So now when block operates in normal mode the CUT takes the input and gives the output accordingly whereas the D flipflops acts independently taking input from the output port of CUT.Below it shows the analysis of scan chain block having scan length of four. 1145

7 Instances Cells Cell area in Micromete r square Scan chain of scan length l=4 Total area in micrometer Instances Cells Leakage ( nano Scan chain of length l=4 Dynamic (d) Total Fig. 13. Scan Chain Block. Simulation Result. Area Analysis. (d) Power analysis. A. MISR MISR is used as output compressor. Here BILBO ( built in logic block observer) architecture is used for MISR operation. MISR is mainly operated in signature mode and the residue obtained is compared with the expected one. It has four modes of operation: 1. B1=0 and B2=0: shift register mode or pseudo random sequence generator. 2. B1=0 and B2=1 : all flipflops are reset. 3. B1=1andB2=0 : signature mode. 4. B1=1 and B2=1: normal mode or all flipflops work independently.analysis of 8-bit MISR is shown. 1146

8 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 4, April 2014 Instances Cells Cell area in Micromete r square Total area in micrometer MISR(8-bit) Instances Cells Leakage Power Dynamic Power Total MISR-8bit (d) Fig MISR Block. Simulation Result. Area Analysis. (d) Power analysis. C Testing 4 to 16 Decoder Circuit: 1147

9 Instances Cells Cell area in Micromete r square Total area in micormeter TPS MISR Scan chain Johnson CUT Seed Circuit with up Leakage Dynamic Total Instances Cells TPS MISR Scan chain Johnson Seed with up (e) Fig. 15. expected outcome of decoder. TPS (johnson reconfigurable ). Area analysis. (d) analysis. (e) layout. The total and area after layout is milli watt and micrometer square respectively. (d) D. Testing 2-bit Comparator Circuit: 1148

10 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 4, April 2014 Instances Cells Leakage Dynamic TPS MISR Scan chain Johnson CUT SeedCircuit withup Total Instances Cells Cell area in Micrometer square Total area in Micrometer square TPS MISR Scan chain Johnson CUT Seed Circuit with up (e) Fig. 16. expected outcome of 2-bit comparator. TPS (johnson reconfigurable ).. analysis. (d) Area analysis (e) layout. The total and area after layout is milli watt and micrometer square respectively. (d) IV. CONCLUSION The test per clock and the test per scan schemes has been implemented with modified seed circuit(seed circuit with up). Single bit change vectors are generated to test the circuit with minimum. Test vectors are uniform in nature and are unique. Modified seed circuit reduces and area over head in both TPC and TPS scheme. REFERENCES [1] Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes,Feng Liang, Luwen Zhang, Shaochong Lei, Guohe Zhang, Kaile Gao, and Bin Liang, IEEE Trans. on very large Scale integration(vlsi) systems, vol.. 21, no.4, april [2] Y. Zorian, A distributed BIST control scheme for complex VLSI devices, in 11th Annu. IEEE VLSI Test Symp. Dig. Papers, Apr. 1993, pp [3] P. Girard, Survey of low- testing of VLSI circuits, IEEE Design Test Comput., vol. 19, no. 3, pp , May Jun [4] A. Abu-Issa and S. Quigley, Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average- reduction in based BIST, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 5, pp , May [5] S. Wang and S. Gupta, DS-LFSR: A BIST TPG for low switching activity, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,vol. 21, no. 7, pp , Jul [6] P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. Wunderlich, A modified clock scheme for a low BIST test pattern generator, in Proc. 19th IEEE VTS VLSI Test Symp., Mar. Apr.2001,pp

11 [7] C. Laoudias and D. Nikolos, A new test pattern generator for high defect coverage in a BIST environment, in Proc. 14th ACM Great Lakes Symp. VLSI, Apr. 2004, pp [8] F. Corno, M. Rebaudengo, M. Reorda, and M. Violante, A new BIST architecture for low circuits, in Proc. Eur. Test Workshop, May 1999, pp Payel Mukherjee received the B.Tech degree in electronics and telecommunication from college of engineering, Bhubaneshwar, INDIA She is currently pursuing the M.Tech degree from SRM university, Chennai, Tamil Nadu. Her current research include design for testing. Mrs. N. Saraswathi, received B.E degree in electronics and communication from madras university in She has completed her m.tech in vlsi design from anna university,2007. She has teaching experience of about 20 years and is currently the Asst. Prof.(S.G) in SRM university, Chennai, Tamil Nadu. 1150