POWER AND AREA EFFICIENT LFSR WITH PULSED LATCHES

Transcription

1 Volume 115 No , ISSN: (printed version); ISSN: (on-line version) url: ijpam.eu POWER AND AREA EFFICIENT LFSR WITH PULSED LATCHES K Hari Kishore 1, Fazal Noor Basha 2, V Krishna Priya 3, G Prashanth Kumar 4,NLV Krishna Rao 5 1,2,3,4,5 Department of ECE, K L University, Vaddeswaram, Guntur, A.P, India 1 Kakarla.harikishore@kluniversity.in, 3 krishnapriya.varanasi95@gmail.com, 4 prasanthkumar7 93@gmail.com, 5 leelaveerakrishna369@gmail.com. Abstract: The following paper deals with power and area efficient LFSR with pulsed latches. The LFSR uses a large number of flip-flops which consume high amount of power. To reduce this power consumption pulsed latches are used in the place of flipflops. The delayed pulsed clocks are used to reduce the timing issues of pulsed latches. The LFSR of higher order are divided into sub-groups for the reduction of the number of pulsed clock generators. A 4-bit LFSR and an 8-bit LFSR of 0.18um CMOS process with Vdd = 5v is designed. The power consumption and area consumption are compared between the 4-bit and 8-bit LFSR and analysis is given in this paper. Index Terms: low power, area-efficient, pulsed latch, LFSR. 1. Introduction A LSFR is an important block of VLSI circuits. It is mainly used in the testing and fault detection circuits. These are mainly used in circuit testing processes like signature analysis and test pattern generation and also random pattern generation. The LFSR has a wide range of applications which need higher order circuits which take up to 256 bit LFSR. This large size LFSR need lager number of flipflops and consumes a lot of power. The main issue of large size LFSR is powerconsumption and area efficiency. The architecture of LFSR is very simple. For any N-bit LFSR it requires N number of flip-flops and Ex-Or gates are taken as per the polynomial equation chosen for the circuit. The polynomial equation plays an important role in the pattern generation. For a large range of patterns one need to take a suitable polynomial. The Ex-Or gates are responsible for the test pattern generation. These gates are used in the feedback of the circuit. Figure 1. Master-Slave flip-flop Pulsed Latch. The following paper proposes area efficient and power efficient LFSR. For the reduction of the power consumption, pulsed latches are used in the place of flip-flops. The delayed pulsed clocks are used to reduce the timing issues of pulsed latches. The LFSR of higher order are divided into sub-groups for the reduction of the number of pulsed clock generators. The remaining paper is arranged as the following: Section 2 gives the detailed explanation of the proposed circuit architecture. Section 3 deals with calculations and comparisons of proposed circuit. Section 4 draws the conclusions. A. Proposed LFSR 2. Architecture Two latches are used by a master slave flipflop for proper working as shown in above figure 1.. This is replaced with pulsed latch with continuous latch and delayed clock signal as shown in figure 1.. In the suggested system pulsed latches would take the pulsed 447

2 clock signal from the pulsed clock generation circuit. Therefore by usage of the pulsed latch the power and area consumption becomes half which is perfect and finest solution for the necessity of the power and area optimization. The LFSR cannot use the pulsed latch because of its problem in timing analysis, which is shown in figure (2). The LFSR contains numerous latches and pulsed clock signals. The obtained response in waveform shown in figure (2) shows timing problems results in the LFSR. Since input signal for the first latch is consistent during the pulsed clock width then the output of first latch-q1 changes correctly. The output signal Q2 of the 2 nd latch is ambivalent as the input signal Q1 alters during clock pulsed width. The timing problem has only one alternative that is to add delay circuits amid the latches. The first latch output signal is delayed which then reaches next latch to the end of the clock pulse. The output signals of 1 st and 2 nd latch which are Q1 and Q2 changes along the pulsed clock width which is presented in figure 3, but 2 nd and 3 rd latches (D2 and D3) input signals remain the same as the output signals form the 1 st and 2 nd latches (Q1 and Q2) after clock pulse. Hence all the latches have continual input signals during the clock pulse, but there is no timing problem that occurs amid the latches. Figure 3. LFSR with delayed pulsed clock signal waveforms. However, delay circuits imbibe much overheads with respect to power and area. One more alternative for this problem is to utilize numerous non-overlap delayed pulsed clock signals, as shown in figure 4. The pulsed clock signals which are delayed will be produced, when clock pulse signal passes through the delayed circuits. The delayed clock pulse used in next latch is utilized by the present latch. Therefore, the data of each latch renews after updating the data by its next latch. By this, each and every latch will be having a consistent input all along its clock pulse cycle and timing problem will not be occurred amid the latches. As the size increases, the circuit requires numerous delayed circuits. In figure 4, the timing diagram shows the delayed clock pulse signal passes through the delay circuits. Each latch utilizes a clock pulse signal which has been delayed by clock pulse signal which has been utilized by its next latch. By this every latch modifies the data after its next latch renews the data. Figure 2. LFSR with pulsed clock signal waveforms. Figure 4. LFSR with delayed pulsed clock signals and latches. Schematic Waveforms. 3. Simulation results 448

3 The following results are the simulation results obtained by implementing the circuit using Tanner EDA tool. The simulation is carried on 4-bit LFSR and 8- bit LFSR. The power calculations are done through tanner tool and area calculations are done by Verilog HDL. A. 4-Bit Linear Feedback Shift Register Figure 7. Power consumption of 4-bit LFSR using flip-flop pulsed latches The 4-bit LFSR is simulated by using both flip-flop and pulsed latches. The power consumed by both the circuits throughout the simulation is plotted and the average of the power consumption is calculated. B. 8-Bit Linear Feedback Shift Register Figure 5. 4-Bit LSFR using Flip-flops Pulsed latches Figure 6. 8-Bit LSFR using Flip-flops Pulsed latches 449

4 Figure 8. Power consumption of 8-bit LFSR using flip-flop pulsed latches Table 1:performance comparison of LFSRs results are between conventional LFSRs and proposed LFSRs. References [1] A 10-bit column-driver IC with parasitic-insensitive iterative charge-sharing based capacitor-string interpolation for mobile active-matrix LCDs, IEEE J. Solid- State Circuits, vol. 49, no.3, pp , Mar-2014 by H.S.Kim, J.H.Yang, S.H.Park, S.T.Ryu, and G.H.Cho. [2] Flow-through latch and edge-triggered flip-flop hybrid elements, IEEE Int. Solid- State Circuits Conference. (ISSCC) Dig. Tech. Papers, pp , Feb-1996 by H.Partovi. [3] Conditional push-pull pulsed latch with 726 fjops energy delay product in 65 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb-2012, pp by E.Consoli, M.Alioto, G.Palumbo, and J.Rabaey. The 8-bit LFSR is simulated by using both flip-flop and pulsed latches. The power consumed by both the circuits throughout the simulation is plotted and the average of the power consumption is calculated. 4. Conclusion This paper suggested an area and power efficient LFSR by utilizing pulsed latches. The LFSR lessens the power and area consumption by utilizing the pulsed latches instead of flip-flops which is used in present existing system. The timing problem amid the pulsed latches is resolved utilizing numerous nonoverlapped delayed pulsed clock signals using as an alternative for a single pulsed clock signal. As the size of the LFSR increases the power consumption can be reduced but the area consumption is not much decreased. The simulation results are theoretical and they can alter when simulated practically. These comparative [4] Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems, in IEEE J. Solid- State Circuits, volume. 34, no.4, pp in Apr-1999 by V.Stojanovic and V.Oklobdzija. [5] A 9.7 mw AAC-decoding, 620 mw H p 60fps decoding, 8-core media processor with embedded forward bodybiasing and power-gating circuit in 65 nm CMOS technology, in IEEE International Solid State Circuits Conference (ISSCC) Dig. Tech. Papers, Feb-2008, pp by S. Nomura. [6] 6.33 mw MPEG audio decoding on a multimedia processor, in IEEE Int. Solid- StateCircuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp by Y. Ueda. [7] Conditional-capture flip-flop for statistical power reduction, IEEE J. Solid- State Circuits, vol. 36, pp , Aug. 450

5 2001 by B.-S. Kong, S.-S. Kim, and Y.-H. Jun. [8] Implementation of Pulsed Latch and PulsedRegister Circuits to Minimize Clocking Power, /11/$26.00, 2011 by Seungwhun Paik, GiJoon Nam,Youngsoo Shin. [9] Design and Analysis of a Linear Feedback Shift Register with Reduced Leakage Power International Journal of Computer Applications ( ) Volume 56 No.14, Oct-2012 by ] M. Janaki Rani,S. Malarkkan. [10] New Protection Techniques against SEUs formoving Average Filters in a Radiation Environment IEEE transactions on Nuclear science by P. Reyes, P. Reviriego. [11] Front end Design of shift registers using latches, International Research Journal ofengineering and Technology (IRJET) Volume: 03 Issue no: 05, May by N.Nikitha, Pramod Mutalik. [12] T. Padmapriya and V. Saminadan, Priority based fair resource allocation and Admission Control Technique for Multi-user Multi-class downlink Traffic in LTE- Advanced Networks, International Journal of Advanced Research, vol.5, no.1, pp , January

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