Introduction to Serial I/O

Transcription

1 CS/ECE 6780/5780 Al Davis Serial I/O Today s topics: general concepts in preparation for Lab 8 1 CS 5780 Introduction to Serial I/O 2 CS 5780 Page 1

2 A Serial Channel 3 CS 5780 Definitions 4 CS 5780 Page 2

3 Bandwidth 5 CS 5780 More Basics Classic UART: DTE & DCE communications UART is the port» for Freescale this is SCI (serial communications interface) this is just one instance as usual signaling levels are TTL interface logic can be used to convert to RS232 levels e.g. MAX232, MC chips» parity is generated by Tx side and checked by Rx side 6 CS 5780 Page 3

4 Half Duplex Signalling Half Duplex normal usage» fixed Tx and Rx side a.k.a. Simplex signalling expanded version» send can come from either side but only in one direction at a time» problem = collisions solution same as with Ethernet CDMA transmit & receive + compare if Tx & Rx values aren t the same then collision & retry 7 CS 5780 Other Issues Full Duplex more wires but 2 independent communication channels» concurrent send and receive buffers Timing send and receive baud rates must be the same Asynchronous (e.g. SCI) separate send and receive clocks» start sequence is used to synch clocks for the frame model is that drift won t be enough to cause errors intra-frame in high speed signaling (e.g. HT, QPI, etc.) this is a big problem and requires complex and energy hungry circuitry long transmission paths also require significant pre- and post-emphasis circuits Synchronous: multiple options common clock (e.g. SPI) Tx side clock source synchronous signaling 8 CS 5780 Page 4

5 SCI & SPI Illustrated 9 CS 5780 Protocols & Specifications There are many Each one has specifications electrical» what voltage levels mean what logical value» current sink and source requirements cables» often limited to some max length mechanical» what does the connector look like & pin function 10 CS 5780 Page 5

6 2 Common Freescale Options Simple SCI SCI to RS232 conversion 11 CS 5780 RS232 Output Specifications 12 CS 5780 Page 6

7 RS232 DB9 Pin Assignments 13 CS 5780 A Simple Serial Network 14 CS 5780 Page 7

8 RS422/RS423/RS485 Specifications 15 CS 5780 Universal Serial Bus (USB) 16 CS 5780 Page 8

9 Optical SCI Channel Where & Why would you want to do this? 17 CS 5780 SCI 18 CS 5780 Page 9

10 Transmitting in Asynchronous Mode 19 CS 5780 Control Bits for the Transmitter NOTE: Tx Data Reg Empty (TDRE) flag signals that the SCDR register is empty, TDRE is cleared by reading it. Different from previous flag clearing methods where you had to write a 1 to the flag. Read of TC flag (transmit complete) similarly clears it Then write to the SCDR 20 CS 5780 Page 10

11 Transmission Illustrated 21 CS 5780 Pseudo Code for Transmission Process 22 CS 5780 Page 11

12 Receiving in Asynchronous Mode 23 CS 5780 Control Bits for the Receiver 24 CS 5780 Page 12

13 Status Bits Generated by the Receiver 25 CS 5780 Receiving Illustrated 26 CS 5780 Page 13

14 Pseudo Code for Receive Process 27 CS S12C32 SCI Details 28 CS 5780 Page 14

15 More SCI Details 29 CS 5780 SCI I/O Interrupts 30 CS 5780 Page 15

16 SCI Rx, Tx, & ISR s TxFifo full wait until there is space RxFifo full data was lost due to Rx buffer over run 31 CS 5780 SCI Interface Ritual 32 CS 5780 Page 16

17 SCI Interface ISR 33 CS 5780 SCI In/Out Character 34 CS 5780 Page 17

18 Serial Port Printer Interfaces Note: 2 approaches DTR is a handshake saying send me another frame Xoff is a shut up signal more efficient for larger buffers but some timing complexity for on the fly & response time issues 35 CS 5780 SCI Simplex Printer Interface (w/ DTR handshake) 36 CS 5780 Page 18

19 Serial Output w/ DTR 37 CS 5780 DTR Handshake ISR 38 CS 5780 Page 19

20 Serial Output to Printer 39 CS 5780 Using XON/XOFF (busy waiting) 40 CS 5780 Page 20

21 Synchronous = SPI (3 options) 41 CS 5780 SPI Master/Slave Example 42 CS 5780 Page 21

22 SPI Fundamentals 43 CS 5780 More SPI Fundamentals Mode fault occurs when master and slave synchronization is wrong e.g. 2 masters 44 CS 5780 Page 22

23 SPI Pseudo Code 45 CS 5780 SPI Modes CPOL sets SCLK polarity e.g. what is IDLE CPHA sets even or odd clock edges for the receiver shift register 46 CS 5780 Page 23

24 9S12C32 SPI Details (Port M) SPIBR register 47 CS 5780 SPI Control Registers 48 CS 5780 Page 24

25 SPI Modes 49 CS 5780 SPI Mode Selections 50 CS 5780 Page 25

26 Concluding Remarks Serial I/O is very common USB is obviously everywhere SPI & SCI are more prevalent in embedded systems» primarily because it s low cost» most controllers support this your kits support both» difference is synch vs. asynch Too much detail already but advise that you take a look at the DAC application we ll go through the full SCI ritual next lecture» in prep for Lab 8 SPRING BREAK hope you have some fun hope I can catch up 51 CS 5780 Page 26