Laboratory 4. Figure 1: Serdes Transceiver

Transcription

1 Laboratory 4 The purpose of this laboratory exercise is to design a digital Serdes In the first part of the lab, you will design all the required subblocks for the digital Serdes and simulate them In part II of the lab you will compile and download the Serdes design in an FPGA chip and test it Introduction Serdes are used for point-to-point data transfer operations in high speed data networking applications such as routers, backplanes and access switches, and storage area network equipment Serdes devices provide a high speed bus without a lot of connections on a backplane or cables between boxes The SER stands for Serializer It takes parallel data and serializes it into a serial bit stream The input is typically 8 parallel data, which is, encoded with an optional 8B/0B encoder This encoding scheme converts the 8 bits data into a 0-bit format that is transmitted over a serial output "Link" The data rate on the link, in this Gigabit per second data input example (Figure ), is therefore 25 Gigabaud The deserializer, or ES, works in reverse as it takes the serial data, decodes it and converts it back to a parallel data interface along with a "recovered" data clock Figure : Serdes Transceiver A generic functional diagram of a Serdes link is shown in Figure 2 The transmitter portion of a Serdes chip has a parallel digital interface, FIFO, 8B/0B encoder (that can be used or bypassed), and serializer The transmitter output drives a differential signal into, typically, 50-Ohm media (00 Ohm ifferential) and requires no external termination or interface components From:

2 Figure 2: Serdes Functional iagram The receiver performs the deserializer function It has a transition tracking loop that does the data and clock recovery, along with byte alignment, an 8B/0B decoder, word alignment FIFO and digital parallel data interface A simplified block diagram for each Serdes channel with the common chip clock is shown in more detail in Figure 3 Figure 3: Serdes Block iagram Part I In this part of the laboratory exercise you will implement different blocks of the Serdes and then integrate and simulate them in a simple verification testbench The goal of this part of the lab is to verify the functionality of Serdes in simulation Block diagram of a simplified all digital Serdes is shown in Figure 4 2

3 FPGA E2 shift register HEX to seg d[8] d[4] d[3] HEX to seg d[0] 8-bit din Seres serial data generator serial-data_out transmitter SET T x 50 MHz Osc KEY[0] filter SET clock generator x8 serial link HEX to seg d[8] d[4] d[3] HEX to seg d[0] shift register 8-bit din din SET sample SET sprefilter clock data recovery C0 C C2 3-bit counter clr edge edge detection serialdata_in R x Figure 4 Serdes and testbench block diagram Serial data generator Figure 5 shows circuit diagram of the serial data generator This circuit generates a 0 Stage Pseudo-Random or PN ata Sequence of 023 states This sequence is long enough to demonstrate the design's ability to recover the clock The signal that is used in creating the PN ata Sequence is independent of the Edge etection Circuit which recovers the clock for sampling the data This circuit simply Creates ata to demonstrate the igital Clock Recovery concept The INIT signal is used to initialize the serial data generator In normal operation INIT should be set to 0 Initialize all the flip-flops to so that the sequence starts with 0 b 3

4 [0] [] [6] [] [8] [9] serial-data_out INIT Figure 5 0-stage pseudo random serial data generator Edge detection An Edge etection circuit is required to detect all the "0 to " and " to 0" transitions of the incoming data This is similar to a Phase Locked Loop (PLL) device detecting phase changes The circuit needs to generate a pulse from either a "0 to " or a " to 0" transition of the incoming data Figure 6 shows the edge detection circuit Use lpm modules to implement the inverter cells in this circuit 0 SET serial_data_in asynchronous clear edge 0 posedge negedge SET asynchronous clear Figure 6 Edge detection circuit Clock generator Clock generator block generates two clock sources: (25 MHz) signal for pseudo random signal generator block and x8 (0 MHz) clock for clock recovery circuit Clock generator can work in 2 modes: functional and test mode In test mode KEY[0] is used to generate clock This mode will be useful in Part II Figure shows block diagram of clock generator 4

5 50 MHz Osc PLL /5 0 MHz Functional mode Test mode Freq ivider (/8) x8 25 MHz KEY[0] Figure clock generator 3-bit counter This block is a simple 3-bit synchronous counter with asynchronous clear (clr) signal The rising or positive edge of the signal sample is used as the sampling clock of the serial_data_in The sampling should happen almost in the center of the data bit 8-bit shift register The 8-bit shift register blocks are used to deserialize the transmitted and received serial data The output of the shift register block is an 8-bit parallel data and should be updated every 8 bits so that you can see a stable number on -segment s Hex to -segment This block converts a 4-bit hex number to equivalent -segment code Follow the following steps for this part of the lab: Create a new uartus II project for top level Serdes circuit 2 Write Verilog codes for the following subblocks: Serial data generator Clock generator Edge detection 3-bit counter 8-bit shift register Hex to -segment 3 Instantiate all the blocks in Serdes top level and connect them with required logic gates and flip-flops as shown in Figure 6 4 In Serdes top level, connect Tx to Rx internally as shown in Figure 6 5 For simulation purposes you can directly apply a 0 MHz clock signal input and bypass PLL in clock generator module 5

6 6 Simulate Serdes circuit (use timing simulation) and show that the sampled data at the receiver side is the same as the transmitted data You can use output of the shift register blocks to compare transmitted and received data In your report: Include all the Verilog codes that you developed with comments Include the simulation waveforms for:, x8, serial_data_out, Tx, serial_data_in, edge, sprefilter, sample, din, and d[:0] Explain how the pseudo random data generator works Explain how the edge detection circuit works With the help of simulation waveforms explain in detail how the clock and data recovery circuit works and answer the following questions: a What is the role of the 3-bit counter (sampling counter) b What will happen if there are successive bits of the same state in serial data? As an example you can analyze this pattern of data 00 In this example you have two edges (0 ) and ( 0) and three consecutive s in between c Using the AN gate to generate the sample signal in clock recover circuit has the possibility of creating false clocks if there are any glitches at the output With the help of simulation waveforms, explain how the filter block filters the possible glitches Part II In this part of the lab, you will test the Serdes circuit in the FPGA chip Create a new uartus II project for your circuit Instantiate the Serdes block from Part I 2 Use KEY[0] pushbutton for input clock signal (test mode in clock generator block) 3 Use KEY[] pushbutton for reset signal 4 Use HEX0, HEX, HEX2, and HEX3 to transmitted and received data 5 Compile the circuit and download it into the FPGA chip You will test the Serdes in two different modes: Internal connection mode: o The goal in this part is to make sure your circuit from Part I can work in FPGA 6

7 o Make the connection between TX and RX (Figure 4) internally similar to what you have done in Part I o Use the KEY[0] to generate clock o Test the functionality of your circuit by comparing -segment s for transmitted and received data External connection mode: o The goal in this part is to make the external connection between TX and RX and try to look at the link signal with a scope o Remove the internal connection in your Verilog code o Use GPIO_0[0] for TX port and GPIO_0[] for RX port connection o Use the clock generator in functional mode and CLOCK_50 pin as your source of clock (page 33, E2 User Manual) o Connect GPIO_0[0] to GPIO_0[] with an external jumper GPIO_0[0] and GPIO_0[] are connected to pins and 2 of JP connector on E2 board (page 35, E2 User Manual) o Use a scope to look at the link signal o Increase the signal frequency by changing the frequency divider ratio of the PLL and repeat the test 6 In your report include: Verilog codes for this part of the lab Explain what is the effect of increasing frequency of the signal on the link signal quality Propose a circuit to measure the BER (bit error rate) of this Serdes Include the block diagram of your proposed circuit