Short summary of ATLAS Japan Group for LHC/ATLAS upgrade review Liquid Argon Calorimeter

Transcription

1 Preprint typeset in JINST style - HYPER VERSION Short summary of ATLAS Japan Group for LHC/ATLAS upgrade review Liquid Argon Calorimeter ATLAS Japan Group Yuji.Enari@cern.ch ABSTRACT: Short summary of LHC/ATLAS upgrade plan from ATLAS Japan Group. In particular, efforts on the ATLAS Liquid Argon Calorimeter are described.

2 Contents 1. ATLAS Liquid Argon Calorimeter Overview of LAr Phase-I upgrade project Development items for Eack-End electronics system and Japanese contribution Research and development status Demonstrator board Integration and operation AMC R&D FPGA fireware development Resource: person power and cost Person power Cost 8 1. ATLAS Liquid Argon Calorimeter In this report, ATLAS-Japan activities on the ATLAS Liquid Argon (LAr) Calorimeter are described. Up to now we focus on the development for the ATLAS Phase-I upgrade which is scheduled during the second long shutdown (LS2) of the LHC in The ATLAS LAr Calorimeter Phase-I upgrade project proposed to install new trigger readout electronics which is described in the ATLAS LAr Calorimeter Phase-I Upgrade Technical Design Report [1] which released this summer (2013). In the Phase-II upgrade, the main readout of LAr Calorimeter needs to be replaced in order to enhance its performance for the LHC upgrade at the third long shutdown (LS3). We are considering to contribute the Phase-II upgrade as well based on our experiences gaining at the Phase-I upgrade. Therefore, we discuss here mainly the Phase-I upgrade project. 1.1 Overview of LAr Phase-I upgrade project The existing calorimeter trigger information is based on the concept of a Trigger Tower" that sums the energy deposition across the longitudinal layers of the calorimeters in an area of η φ = The Trigger Tower is created through several stages of on-detector analog electronics. The new finer granularity scheme is based on so-called Super-Cells", which provide information of each calorimeter layer for the full η range of the calorimeter, as well as finer segmentation ( η φ = ) in the front and middle layers of the EM barrel (EMB) and endcap (EMEC) for η 2.5. This scheme is detailed for the EMB in Table 1 and is illustrated in Fig. 1. By introducing the Super-Cells, the selectivity of EM and τ objects, the resolution of jets and Missing E T trigger signatures, and the discrimination power against background emerging from both the out-of-time and in-time pileup, can be improved which makes better control on the trigger rates. Performance studies and impact on physics analyses are outlined in the LAr Phase-I TDR [1]. Ultimately the project targets are: 1

3 Table 1. Comparison of the current Trigger Tower granularity vs. the proposed Super-Cell granularity in the LAr EM barrel calorimeter, in terms of both elementary cells and η and φ. The number of elementary cells grouped for the trigger readout in η and φ are indicated by n η and n φ, respectively. Elementary Cell Trigger Tower Super-Cell Layer η φ n η n φ η φ n η n φ η φ 0 Presampler Front Middle Back LAr EM Barrel Existing System Level-1 Trigger Granularity (Trigger Towers) 60 cells per Trigger Tower; all layers summed Phase-I Upgrade Level-1 Trigger Granularity (Super Cells) 10 Super Cells per Trigger Tower EM layer 2 Middle: 4x4 x =0.025x0.025) EM layer 1 Front: 32x1 x =0.0035x0.1) EM layer 0 Presampler: 4x1 x =0.025x0.1) EM layer 3 Back: 2x4 x =0.05x0.025) EM layer 1 Front: 8x1 x =0.0035x0.1) EM layer 0 Presampler: 4x1 x =0.025x0.1) EM layer 2 Middle: 1x4 x =0.025x0.025) EM layer 3 Back: 2x4 x =0.05x0.025) Presampler SC_layer=0 SC_region=0 SC_eta= [ =0.1] SC_region=1 SC_eta=14(15) [ ~0.1(0.)] SC_phi= [ =0.1] Front SC_layer=1 SC_region=0 SC_eta= [ =0.025] SC_region=1 SC_eta= [ =0.025] SC_phi= [ =0.1] Middle SC_layer=2 SC_region=0 SC_eta= [ =0.025] SC_region=1 SC_eta=56 [ 0.075] SC_phi= [ =0.1] Back SC_layer=3 SC_region=0 SC_eta=0... [ =0.1] SC_eta=13 [ ~0.05] SC_phi= [ =0.1] Figure 1. Geometrical representation in η,φ space of an EM Trigger Tower in the current system, where the transverse energy in all four layers are summed (left) and of the Super-Cells proposed for the Phase-I upgrade, where the transverse energy in each layer is retained in addition to the finer granularity in the front and middle layers (right). Each square represents an area of size η φ = Reduce jet backgrounds in the Level-1 EM trigger by deploying shower shape algorithms and high-precision isolation criteria for electron and photon identification. 2. Deploy algorithms currently used in the high-level trigger to improve τ identification in the Level-1 trigger. 3. Improve the Level-1 jet and Missing E T resolutions and efficiencies to effectively reduce the rates while retaining the same physics acceptance of the offline analyses. These improvements will be achieved by taking advantage of the higher η-granularity of the Super- Cells compared to Trigger Towers, the layer segmentation providing longitudinal shower information for the Level-1 trigger, and the higher precision of the energy in the Super-Cells due to a smaller quantization scale. Ultimately the goal is to maintain the thresholds of single and multiobject Level-1 calorimeter triggers at values comparable to those used in Run-1 despite the increased centre-of-mass energy, potential instantaneous luminosity up to L = cm 2 s 1, and pileup up to µ = 80. The architecture of the upgraded calorimeter trigger electronics is shown in Fig. 2, with the upgraded and new components outlined in red. To provide high-granularity and high-precision 2

4 information to upgraded trigger processors called Feature EXtractors (FEXs) [2] in the Level-1 calorimeter trigger system (L1Calo), new LAr Trigger Digitizer Boards (LTDB) are installed in the available spare slots of the Front-End (FE) crates. The upgrade of the layer sum boards and of the baseplanes allows the LTDBs to digitize information with granularity up to η φ = in the front and middle layers of the EM calorimeters. The LTDB also recreates the analog sums and feeds them back to the Tower Builder Board (TBB) to maintain the legacy system as fully operational. The digitized signals are processed remotely by the LAr Digital Processing System (LDPS) modules, which convert the samples to calibrated energies in real-time and interface to the FEX processors. ATLAS-Japan contributes the development on the LDPS in Back-End (BE) system, especially R&D of the high speed data transfer and the digital signal processing to calculate the transverse energy of the Super-Cell precisely. 3

5 4 Preampl. New Layer Sum Boards [LSB] Linear Mixer PZ+Dly Timing Trigger Control RCx MUX/Serializer Optical Links Front-End Board Timing Trigger Control Distribution Controller MUX/Serializer (FPGA) CLK Fanout Crate Monitoring ~250 Gbps/board Optical Links ORx m fibers Channel De-multiplexer INPUT FPGA TTC Partition Master Optical Receiver Deserializer ROD DSP 480Gbps/module 1.92 Tbps/board Optical Receiver Deserializer OTx CLK & Cfg. FPGA LAr Digital Processing System (LDPS) S(t) Receiver Fixed Latency (~3.0us max) LAr Trigger Digitizer Board (LTDB) is(t- i) Trigger Tower Sum and Drivers Tower Builder Board [TBB] Controller Board Shaper SDRAM Timing Trigger Control Rx Timing Trigger Control Rx Output FPGA Feature Extractor [FEX] Level-1 Calorimeter Trigger System Current L1Calo Processors DAQ Figure 2. Schematic block diagram of the Phase-I upgrade LAr trigger readout architecture. Left half is the Front-End (FE) part, right half is the Back-End (BE) part. The FE and the BE are connected via m fibers to transfer the signal from LAr calorimeter. TOP line to DAQ through the ROD is for main readout path, other two line are the path to the L1Calo system. The new components for Phase-I upgrade are indicated by the red outlines and arrows. Baseplane

6 1.2 Development items for Eack-End electronics system and Japanese contribution The LAr calorimeter BE electronics system, called the LAr Digital Processing System (LDPS), must perform following three roles: (i) receiving the digital signals from the 4 LTDBs from the FE, (ii) extracting the transverse energy for each Super-Cell every 25 ns with digital filtering, and (iii) transmitting these data to the L1Calo. The main challenge for the LDPS is the efficient handling of the large data volume: the reception of 25 Tbps for 34,000 Super-Cells and the transmission of 41 Tbps over optical fibers to the L1Calo. The system must also be integrated in the ATLAS data acquisition system, synchronized with the LHC clock, and will provide monitoring capabilities. The hardware implementation will be based on the ATCA (Advanced Telecom Computer Architecture) platform that supports the design of high-density, high-speed communication boards. The proposed LDPS is made up of 31 LAr Digital Processing Blades (LDPBs) housed in three ATCA shelves. Each LDPB consists of one carrier board equipped with four Advanced Mezzanine Cards (AMCs), for a total of 4 AMCs. The three roles listed above are processed all on the AMC for up to 320 Super-Cells, therefore it is designed around a powerful FPGA with high-speed transceivers. The AMC conforms to the standard ATCA protocol and measures 156 mm 73.5 mm to allow four AMCs to fit on a carrier board. The design of the AMC for the LDPS (see Fig. 3) is built around one FPGA with large capabilities for internal logic and memory, digital filtering for signal reconstruction algorithms, and high-speed communications. Developments of the LDPS are proceeded by the ATLAS LAr BE group which consists of nine institutions from five countries (two from France, four from U.S., and one each from Germany, Japan and Russia). ATLAS-Japan contributes development on the AMC with Annecy (France), BNL(US) and Stony Brook (US), and its firmware with Annecy (France), Dresden (Germany) and Arizona (US). Details on the developments are described in the following sections. 1.3 Research and development status We have three R&D activities for the Phase-I upgrade; 1. Integration and operation 2. AMC R&D 3. Digital filtering A demonstrator board for BE electronics is a key role to define these activities Demonstrator board This is a pre-prototype LDPB (LAr Digital Proceeding Board) developed by Annecy group in order to test and demonstrate functionalities of the BE electronics of Phase-I upgrade in Run-2. It receives digital signal from the FE with high-speed links, performs robust energy reconstruction under high pileup conditions within at most ns, and transmits data of reconstructed energy etc to Level-1 trigger system. This provides a new trigger path, where Super-Cell information is available to reduce Level-1 trigger rates by suppresing fake events. We have a plan to install two pre-prototype LDPB (to cover only η φ = ) with the FE components in 2014 during LS1 but before making decision to install them, an ATLAS review will be held in spring In the review, we are required to show that new trigger path will be operated without affecting the existing (legacy) trigger path, which has been well operated in Run-1. 5

7 Optical fibres AMC connector L1Calo e/jfex 4x Optics Tx FLASH Oscillators PLL DC/DC;LDO 1,2 1 Power : V 3.3V-IPMI GBT 1GbE LTDB 4x Optics Rx FPGA SDRAM DDR3 Sensors MMC 4 TTC High Speed Links Reset, JTAG IPM-L Figure 3. Block diagram of an AMC, centered around a high-bandwidth FPGA. The AMC receives (transmits) data over 4 Rx (4 Tx) optical fibers Integration and operation LAr calorimeter group has been preparing a test facility at EMF (LAr Electronics Maintenace Facility, close to ATLAS P1) to test LAr trigger components including the LDPB demonstrator board. Most of tests needed for the ATLAS review mentioned before will be performed. We are in charge of the preparation of test bench to take data from the legacy trigger path, which is necessary to comprare with the new trigger path and to confirm that they are identical and have no effect each other. This work can extend to operation works of Run-2 because the same DAQ system and R&D framework will be used. In addition, we made the demonstrator board (see Fig. 4) in Japan with strong supports of Annecy group in order to have as many tests as possible in parallel. The demonstrator board carries three FPGA which deal with all functionalities (high-speed links, digital processing, monitoring, etc..). These are coded with HDL-based firmware which is the part we would like to contribute. Outcomes from these tests are important for the AMC development AMC R&D The functionalities of the LDPB explained above are integrated in the demonsrator board but in Phase-I upgrade we are required to make components more compact in order to handle all LAr calorimeter data with 31 LDPBs. As mentioned before the proposed design of the LDPB is an ATCA carrier board equipped with four AMC (Advanced Mezzanine Card), where a single AMC corresponds to the demonstrator board. The AMC processes the data of up to 320 channels, where we expect 300 Gbps for Tx and 150 Gbps for Rx without considering overhead, for example, 8b/10b or/and 64b/66b encoding. To handle such high speed links on a high-density board, AVAGO 6

8 Figure 4. The LDPB demonstrator board (ATCA board) with three Altera Stratix IV FPGAs. Figure 5. Block diagram of our test board with Xilinx Kintex-7 FPGA and two sets of MicroPOD. MicroPOD optical modules [3] are chosen. The size of MicroPOD is 7.6 mm 7.6 mm 3.9 mm and eight MicroPOD modules (4 Tx+4 Rx) are installed on the AMC (16 cm 7.4cm). We have started R&D of high-speed and high-density data transter by using MicroPOD and Xilinx-7 series FPGA under KEK Open-It project since summer The experts of the Open-It project help us, in particular, students to design PCB board, FPGA firmware programming and so on. Figure 5 shows the block diagram of our test board (the 1st version), which will be delivered at the end of Janurary in FPGA fireware development We have started the development of new energy recontruction algorithm, which is called filtering, to reduce out-of-time pileup contributions. In Run-I ROD (not Level-1 trigger), so-called optimal filtering (OF) algorithm has been used to reconstruct calorimeter cell energy, where thanks to a bipolar signal shape we can assume that the amplitude and the (offset) time of injected pulse are represented by the linear combination of five samplings. This algorithm is not robust against high pileup and also has poor performance for small signal pulses including pileup. In the LDPB s AMC, such a filtering is performed for the Super-Cells on FPGA with at most 5-6 bunch-crossing latency (5 150 ns), which is the same as the OF. New filtering algorithms, for example, filterings with 32 samplings with the 5 ns latecy, have been already tested and some of them are promising. We need further improvement and tests with HDL-based fireware, which can be tested in the demonstrator board with Run-2 data. 1.4 Resource: person power and cost Person power The present participants to the LAr calorimeter upgrade from Japan is members of the University of Tokyo; 5 permanent staff, 1 post-doc, 1 PhD student and 2 master cource students. We expect that the profile of the person power does not changed so much for both Phase-I and Phase-II upgrade. 7

9 Most of members are based at CERN, which makes easy comunication for our R&D, also we can contribute on the operation of LAr Calorimeter Cost The total estimated cost for Phase-I upgrade for the LAr calorimeter is about 7.9 MCHF (updated from 7.6 MCHF in Section 6 of [1]). It consists of 4.6 MCHF for FE electronics, 0.6 MCHF for optical cables and 2.7 MCHF for BE electronics. The table 2 shows cost estimation for ATLAS-Japan LAr group. The core and R&D costs are MYEN ( 2,277 kchf) and 52 MYEN ( 520 kchf), respectively. These numbers include both Phase-I and Phase-II cost. We ll contribute 538 kchf to the LAr calorimeter group, which is about 6.8% of the total amount, for the Phase-I upgrade. In the Phase-I upgrade, we are strongly involved in R&D of AMC board, FPGA fireware development and so on in the BE electronics instead of in-kind contribution. For the Phase-II upgrade, we are interested in the upgrade of ROD components, which required high-speed data transmission and precise energy reconstruction. Table 2. Budget profile of Japan group for LAr upgrade (in units of Japanese 1000YEN) Total Core 800 8,200 39,800 16,000 11,100 24,900 79,100 35,800 6,000 6, ,700 R&D 6,000 6,000 6,000 6,000 6,000 6,000 6,000 6,000 2,000 2,000 52,000 Total 6,800 14,200 45,800 22,000 17,100 30,900 85,100 41,800 8,000 8, ,700 References [1] ATLAS Collaboration, ATLAS Liquid Argon Calorimeter Phase-I Upgrade Technical Design Report, CERN-LHCC , ATLAS-TDR-022 [2] ATLAS Collaboration, Technical Design Report for the Phase-I Upgrade of the ATLAS TDAQ System, CERN-LHCC , ATLAS-TDR-023 [3] AVAGO, MicroPOD T M and MiniPOD T M 0G Transmitters/Receivers, 8