Status of the CSC Track-Finder

Transcription

1 Status of the CSC Track-Finder D. Acosta, S.M. Wang University of Florida A.Atamanchook, V.Golovstov, B.Razmyslovich PNPI

2 CSC Muon Trigger Scheme Strip FE cards Strip LCT card CSC Track-Finder LCT Motherboard Port Card Sector Receiver Sector Processor FE OPTICAL LCT TMB PC SR SP FE Wire FE cards Wire LCT card µ / chamber µ / port card µ / sector On chamber In periphery crate In counting house CSC Muon Sorter RPC DT µ µ Global µ Trigger µ µ Global L1 D. Acosta, University of Florida /7/

3 Muon Track-Finding Link trigger primitives into tracks Measure P T, ϕ, and η Transmit highest P T candidates to Global L1 ϕ D. Acosta, University of Florida /7/ θ

4 Design Status Nearly complete conceptual design presented late March at SR/SP review Primary concern is the design of the Track Assembler, the heart of the Track-Finder Digests extrapolation results and must determine the quantity and quality of trigger muons Scheme proposed, but must be validated with physics simulation Must avoid ghost tracks for multi-muon trigger, yet maintain high efficiency for high P T single muons

5 Sector Processor Block Diagram Input (x) (x) EU - ( Extrapolations or 1 bits) Extrapolation Units Track Assembler U CUSTOM BACKPLANE Data Control - Data Line - Control Line INPUT DATA & CONTROL INTERFACE - Downloading/ Readout Line Input Data 1x=10 (x) (x) (x) (x) (x) 1(x) EU - EU - EU 1- (1 bits) (1 bits) 1 ( bits) TAU TAU 1 Track Track Track Track Track Track 1 Final Selection Unit FSU DOWNLOADING/ READOUT INTERFACE VME BUS U Extrapolation Unit AU Track Assembling Unit SU Final Selection Unit TA Selected Track Address ID Look-Up Input Data (x) 1(x) EU1 1-1 ( bits) Assignment Unit CLOCKED FIFO Data Extraction MUX LID Pt LUT Output Data x= OUTPUT CONNECTOR D. Acosta, University of Florida /7/

6 Sector Processor Logic 1 1 Chamber ME Chamber ME Perform all combinations of in parallel: 1 i k, 1 i k, i k, i k But not 1 i k 1 Chamber ME Chamber ME1 Track Assembler takes best or per reference segment 1 * 1 1 * 1 * 1 ** 1 1 ** 1** 1 * 1 ** D. Acosta, University of Florida /7/ 11

7 Data Stream Paths 1,, Extrapolations 1 1 Track Assembler Unit (TAU) Extrapolation Units Stream Track types: 1 1 Stream Track Assembler Unit (TAU1) Track types: ,, Extrapolations 1 1 D. Acosta, University of Florida /7/ 1

8 ([bits Quality + bits Number] x ) (+) best (+) best (+) best ([bits Quality + bits Number] x ) bits + bits + bits according to the order of priority (PCB Layout) bits + bits according to the order of priority (PCB Layout) A Multiplexer Sel1 Sel Sel 7 bits: Hit number (1 st chamber) bits Hit number ( nd chamber) bits Hit number ( rd chamber) bits Hit number ( th chamber) bits To Final Selection Unit (Hit Number Part) To Final Selection Unit (Extrapolation Quality Part) LUT Kx1 Link 1 Link Link A A1 B B B1 C C C1 Selection Unit ( Best Tracks) Track Absolute Quality bits + bits: bits select 1, or stream bits select h., m. or l. priority track. Extrapolations Quality Track Local Quality Track Assembler Unit (TAU1)

9 bits: 1 st track segment number bits; nd track segment number bits. Track MUX (if we need only track segments for Pt calculation) From Track Assemling Unit (Hit Number Part) Stream 1 Stream Track Track Track Track Track 1 To Data Extraction Multiplexer We should compare: Track1-Track; Track1-Track; Track1-Track; Track-Track; Track-Track; Track-Track; Track-Track; Track-Track; Track-Track ( bits as total) Hit Number Comparators ( Units) Sel1 Sel Sel Final Decision Unit LUT Kx Each track consists of track segments as maximum Tracks has track segments We need 10 (+)bits to describe all possible combinations From Track Assemling Unit (Extrapolations Quality Part) Stream1 Stream Track Track Track Track Track Track 1 Extrapolations Quality Comparators ( Units) Final Selection Unit

10 A B C C1 LUT1 Kx LUT Kx1 B C A A1 LUT Kx Sel Sel A C B B1 LUT Kx Sel1 A B C LUT Kx A A A1 B B B1 C C C1 Selection Unit (TAU1,TAU) hardware realization

11 Preparation for full SP review in July Finalize backplane and SR SP signals, including -station capability Determine connector space at backplane Estimate FPGA and RAM count Estimate board area (must fit on Ux00mm) Estimate cost Validate basic scheme with simulations