ADL5904. DC to 6 GHz, 45 db TruPwr Detector with Envelope Threshold Detection. Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM ENBL 4 APPLICATIONS

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1 DC to 6 GHz, 4 db TruPwr Detector with Envelope Threshold Detection ADL94 FEATURES RMS and envelope threshold detection Broad input frequency range: dc to 6 GHz RF input range: 4 db ( dbm to + dbm) RMS linear in decibel output, scaled 6. mv/db Input envelope threshold detection and latching Programmable threshold and latch reset function Fast response time: ns from RFIN to / latch All functions temperature and supply stable Operates at. V from 4 C to + C Low power:. ma Power-down capability to µa 6-lead, mm mm LFCSP package RFIN FUNCTIONAL BLOCK DIAGRAM ENBL 4 ADL94 GND ENVELOPE DETECTOR VPOS 7 VIN RST 6 + RMS VCAL CRMS DECL DNC Figure. R S VRMS 88- APPLICATIONS Transmitter signal strength indication (TSSI) Wireless power amplifier input and output protection Wireless receiver input protection GENERAL DESCRIPTION The ADL94 is a dual-function radio frequency (RF) TruPwr detector that operates from dc to 6 GHz. It provides rms power measurement along with a programmable envelope threshold detection function. The rms power measurement function has a 4 db detection range, nominally from dbm to + dbm. The rms power measurement function features low power consumption and an intrinsically ripple free error transfer function. The envelope threshold detection function compares the voltage from an internal envelope detector with a user defined input voltage. When the voltage from the envelope detector exceeds the user defined threshold voltage, an internal comparator captures and latches the event to a set/reset (SR) flip flop. The response time from the RF input signal exceeding the user programmed threshold to the output latching is ns. The latched event is held on the flip-flop until a reset pulse is applied. The RF input of the ADL94 is dc-coupled, allowing operation down to arbitrarily low ac frequencies. It operates on a. V supply and consumes. ma. A disable mode reduces this current to µa when a logic low is applied to the ENBL pin. The ADL94 is supplied in a mm mm, 6-lead LFCSP for operation over the wide temperature range of 4 C to + C. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: Analog Devices, Inc. All rights reserved. Technical Support

2 ADL94 TABLE OF CONTENTS Features... Applications... Functional Block Diagram... General Description... Revision History... Specifications... Absolute Maximum Ratings... 8 ESD Caution... 8 Pin Configuration and Function Descriptions... 9 Typical Performance Characteristics... Test Circuits... 7 Theory of Operation... 8 Basic Connections for RMS Measurement... 8 Choosing a Value for CRMS... 9 VRMS Calibration and Error Calculation... Basic Connections for Threshold Detection... and Response Time... Setting the VIN Threshold Detection Voltage... Evaluation Board Schematic and Configuration Options... Outline Dimensions... 7 Ordering Guide... 7 REVISION HISTORY 7/7 Rev. A to Rev. B Changes to Basic Connection for RMS Measurement Section and Figure Change to Figure 4... Change to C4 Default Value, Table /7 Rev. to Rev. A Changes to Ordering Guide... 7 /6 Revision : Initial Version Rev. B Page of 7

3 ADL94 SPECIFICATIONS VPOS =. V, continuous wave (CW) input, TA = C, ZO = Ω, Capacitor CRMS = nf, unless otherwise noted. Table. Parameter Test Conditions/Comments Min Typ Max Unit OVERALL FUNCTION Frequency Range dc to 6 MHz f = MHz ±. db Input Range 4 db Input Level, ±. db Maximum Three-point calibration at dbm, dbm, and + dbm dbm Minimum dbm VRMS Output Voltage RFIN pin = dbm.6 V RFIN pin = dbm.4 V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm.4/+. db VRMS Logarithmic Slope PIN = dbm to dbm 6. mv/db PIN = dbm to + dbm. mv/db VRMS Logarithmic Intercept PIN = dbm to dbm. dbm PIN = dbm to + dbm 6 dbm VIN Setpoint Voltage For threshold detection at dbm 74 mv For threshold detection at dbm 4 mv For threshold detection at dbm 8 mv Threshold Variation vs. 4 C < TA < +8 C, PIN dbm ±. db Temperature 4 C < TA < +8 C, PIN dbm./ db 4 C < TA < +8 C, PIN dbm./ db 4 C < TA < + C, PIN dbm ±. db 4 C < TA < + C, PIN dbm./ db 4 C < TA < + C, PIN dbm./ db f = MHz ±. db Input Range 4 db Input Level, ±. db Maximum Three-point calibration at dbm, dbm, and + dbm dbm Minimum dbm VRMS Output Voltage RFIN pin = dbm.6 V RFIN pin = dbm.4 V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db VRMS Logarithmic Slope PIN = dbm to dbm 6.8 mv/db PIN = dbm to + dbm.4 mv/db VRMS Logarithmic Intercept PIN = dbm to dbm 4.7 dbm PIN = dbm to + dbm.7 dbm VIN Setpoint Voltage For threshold detection at dbm 7 V For threshold detection at dbm 8 mv For threshold detection at dbm 8 mv Rev. B Page of 7

4 ADL94 Parameter Test Conditions/Comments Min Typ Max Unit Threshold Variation vs. 4 C < TA < +8 C, PIN dbm /. db Temperature 4 C < TA < +8 C, PIN dbm.4/. db 4 C < TA < +8 C, PIN dbm.4/ db 4 C < TA < + C, PIN dbm /. db 4 C < TA < + C, PIN dbm.4/. db 4 C < TA < + C, PIN dbm.4/ db f = MHz ±. db Input Range 4 db Input Level, ±. db Maximum Three-point calibration at dbm, dbm, and + dbm dbm Minimum dbm VRMS Output Voltage RFIN pin = dbm.6 V RFIN pin = dbm.6 V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db 4 C < TA < +8 C, PIN = dbm /. db 4 C < TA < + C, PIN = dbm./+. db VRMS Logarithmic Slope PIN = dbm to dbm 4.9 mv/db PIN = dbm to + dbm mv/db VRMS Logarithmic Intercept PIN = dbm to dbm.7 dbm PIN = dbm to + dbm.6 dbm VIN Setpoint Voltage For threshold detection at dbm 74 mv For threshold detection at dbm 9 mv For threshold detection at dbm 8 mv Threshold Variation vs. 4 C < TA < +8 C, PIN dbm ±. db Temperature 4 C < TA < +8 C, PIN dbm.4/. db 4 C < TA < +8 C, PIN dbm./ db 4 C < TA < + C, PIN dbm ±. db 4 C < TA < + C, PIN dbm.4/. db 4 C < TA < + C, PIN dbm./ db f = 9 MHz ±. db Input Range 4 db Input Level, ±. db Maximum Three-point calibration at dbm, dbm, and + dbm 7 dbm Minimum 8 dbm VRMS Output Voltage RFIN pin = dbm.6 V RFIN pin = dbm.7 V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm /. db 4 C < TA < + C, PIN = dbm /. db 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm.4/+. db VRMS Logarithmic Slope PIN = dbm to dbm.9 mv/db PIN = dbm to dbm.8 mv/db VRMS Logarithmic Intercept PIN = dbm to dbm 6.8 dbm PIN = dbm to dbm 4.8 dbm VIN Setpoint Voltage For threshold detection at dbm 7 mv For threshold detection at dbm 4 mv For threshold detection at dbm 8 mv Rev. B Page 4 of 7

5 ADL94 Parameter Test Conditions/Comments Min Typ Max Unit Threshold Variation vs. 4 C < TA < +8 C, PIN dbm ±. db Temperature 4 C < TA < +8 C, PIN dbm./+. db 4 C < TA < +8 C, PIN dbm./. db 4 C < TA < + C, PIN dbm ±. db 4 C < TA < + C, PIN dbm./+. db 4 C < TA < + C, PIN dbm./. db f = 9 MHz ±. db Input Range 4 db Input Level, ±. db Maximum Three-point calibration at dbm, dbm, and + dbm 7 dbm Minimum 8 dbm VRMS Output Voltage RFIN pin = dbm.6 V RFIN pin = dbm. V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db 4 C < TA < +8 C, PIN = dbm./. db 4 C < TA < + C, PIN = dbm.4/. db VRMS Logarithmic Slope PIN = dbm to dbm 4.8 mv/db PIN = dbm to dbm 6.9 mv/db VRMS Logarithmic Intercept PIN = dbm to dbm.9 dbm PIN = dbm to dbm.8 dbm VIN Setpoint Voltage For threshold detection at dbm 774 mv For threshold detection at dbm 4 mv For threshold detection at dbm 78 mv Threshold Variation vs. 4 C < TA < +8 C, PIN dbm./+. db Temperature 4 C < TA < +8 C, PIN dbm./ db 4 C < TA < +8 C, PIN dbm ±. db 4 C < TA < + C, PIN dbm./+. db 4 C < TA < + C, PIN dbm./ db 4 C < TA < + C, PIN dbm ±. db f = 6 MHz ±. db Input Range 4. db Input Level, ±. db Maximum Three-point calibration at dbm, dbm, and + dbm 6 dbm Minimum 7. dbm VRMS Output Voltage RFIN pin = dbm.6 V RFIN pin = dbm. V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db 4 C < TA < +8 C, PIN = dbm./ db 4 C < TA < + C, PIN = dbm./ db VRMS Logarithmic Slope PIN = dbm to dbm 6. mv/db PIN = dbm to dbm 7. mv/db VRMS Logarithmic Intercept PIN = dbm to dbm 4 dbm PIN = dbm to dbm.7 dbm VIN Setpoint Voltage For threshold detection at dbm 77 mv For threshold detection at dbm 6 mv For threshold detection at dbm 76 mv Rev. B Page of 7

6 ADL94 Parameter Test Conditions/Comments Min Typ Max Unit Threshold Variation vs. 4 C < TA < +8 C, PIN dbm./+. db Temperature 4 C < TA < +8 C, PIN dbm./ db 4 C < TA < +8 C, PIN dbm.4/. db 4 C < TA < + C, PIN dbm./+. db 4 C < TA < + C, PIN dbm./ db 4 C < TA < + C, PIN dbm.4/. db f = MHz ±. db Input Range 4 db Input Level, ±. db Maximum Three-point calibration at 8 dbm, dbm, and + dbm 7 dbm Minimum dbm VRMS Output Voltage RFIN pin = dbm.4 V RFIN pin = dbm.44 V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db 4 C < TA < +8 C, PIN = dbm./. db 4 C < TA < + C, PIN = dbm.4/. db VRMS Logarithmic Slope PIN = 8 dbm to dbm.9 mv/db PIN = dbm to + dbm 8.8 mv/db VRMS Logarithmic Intercept PIN = 8 dbm to dbm. dbm PIN = dbm to + dbm 9.7 dbm VIN Setpoint Voltage For threshold detection at dbm 68 mv For threshold detection at dbm 77 mv For threshold detection at dbm mv Threshold Variation vs. 4 C < TA < +8 C, PIN dbm ±. db Temperature 4 C < TA < +8 C, PIN dbm ±. db 4 C < TA < +8 C, PIN dbm./. db 4 C < TA < + C, PIN dbm ±. db 4 C < TA < + C, PIN dbm ±. db 4 C < TA < + C, PIN dbm./. db f = 8 MHz ±. db Input Range 7 db Input Level, ±. db Maximum Three-point calibration at dbm, dbm, and + dbm 9 dbm Minimum 8 dbm VRMS Output Voltage RFIN pin = dbm.4 V RFIN pin = dbm.6 V VRMS Deviation vs. Temperature Deviation from output at C 4 C < TA < +8 C, PIN = dbm./+. db 4 C < TA < + C, PIN = dbm./+. db 4 C < TA < +8 C, PIN = dbm /. db 4 C < TA < + C, PIN = dbm /. db VRMS Logarithmic Slope PIN = dbm to dbm 6.4 mv/db PIN = dbm to dbm 9.9 mv/db VRMS Logarithmic Intercept PIN = dbm to dbm.9 dbm PIN = dbm to dbm.7 dbm VIN Setpoint Voltage For threshold detection at dbm 4 mv For threshold detection at dbm 9 mv For threshold detection at dbm 9 mv Rev. B Page 6 of 7

7 ADL94 Parameter Test Conditions/Comments Min Typ Max Unit Threshold Variation vs. 4 C < TA < +8 C, PIN dbm ±. db Temperature 4 C < TA < +8 C, PIN dbm ±.4 db 4 C < TA < +8 C, PIN dbm.6/+.4 db 4 C < TA < + C, PIN dbm ±. db 4 C < TA < + C, PIN dbm ±.4 db 4 C < TA < + C, PIN dbm.6/+.4 db THRESHOLD DETECT OUTPUT,, and RST pins, 9 MHz input frequency Propagation Delay RFIN pin = off to dbm, VIN = 4 mv ( db overdrive) ns RFIN pin = off to dbm, VIN = 7 mv ( db overdrive) ns Output Voltage, Low IOL = ma mv High IOH = ma. V RESET INTERFACE RST pin RST Input Voltage Low.6 V High V RST Input Bias Current na Reset Time RST at % to low and high ns COMPARATOR INTERFACE VIN pin VIN Input Range to. V VIN Input Bias Current µa VIN for Comparator Disable VPOS V VCAL INTERFACE VCAL pin VCAL Output Voltage RFIN pin = off 7 mv RFIN pin = dbm, 9 MHz 8 mv RFIN pin = dbm, 9 MHz. V POWER-DOWN INTERFACE ENBL pin Voltage Level to Enable VPOS V Voltage Level to Disable.6 V Input Bias Current VENBL =. V < na POWER SUPPLY INTERFACE VPOS pin Supply Voltage...4 V uiescent Current TA = C, no signal at RFIN. ma TA = C, no signal at RFIN 4 ma Power-Down Current ENBL = low µa Rev. B Page 7 of 7

8 ADL94 ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage, VPOS. V Input Average RF Power dbm Equivalent Voltage, Sine Wave Input.6 V peak Maximum Junction Temperature C Operating Temperature Range 4 C to + C Storage Temperature Range 6 C to + C Lead Temperature (Soldering, 6 sec) C Driven from a Ω source. Input ac-coupled with an external 8. Ω shunt resistor. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table. Thermal Resistance Package Type θja θjc Unit CP C/W Thermal impedance simulated value is based on no airflow with the exposed pad soldered to a 4-layer JEDEC board. Thermal impedance from junction to exposed pad on underside of package. ESD CAUTION Rev. B Page 8 of 7

9 ADL94 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN RST ENBL RFIN DNC VCAL DECL ADL94 TOP VIEW (Not to Scale) GND VRMS 4 9 CRMS VPOS DNC VPOS DNC Table 4. Pin Function Descriptions NOTES. DNC = DO NOT CONNECT.. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE. Figure. Pin Configuration Pin No. Mnemonic Description RFIN RF Input. The RFIN pin is dc-coupled and is not internally matched. A broadband Ω match is achieved using an external 8. Ω shunt resistor with a.47 µf ac coupling capacitor placed between the shunt resistor and the RF input. Smaller ac coupling capacitor values can be used if low frequency operation is not required., 6, 8 DNC Do Not Connect. Do not connect to these pins. VCAL Threshold Calibration. The voltage on this pin determines the correct threshold voltage that must be applied to Pin 6 (VIN ) to set a particular RF power threshold. This process has two steps: first, measure the output voltage on VCAL with no RF signal applied to RFIN (this voltage is typically 7 mv). Next, apply the RF input power to RFIN, which causes the circuit to trip and again measure the voltage on the VCAL pin. The difference between these two voltages is equal to the threshold voltage that must be applied to VIN during operation. 4 DECL Internal Decoupling. Bypass this pin to ground using a 4. Ω resistor connected in series with a nf capacitor., 7 VPOS The supply voltage range =. V ±%. Place power supply decoupling capacitors on Pin. There is no requirement for power supply decoupling caps on Pin 7. 9 CRMS RMS Averaging Capacitor. Connect a capacitor between the DECL pin and the CRMS pin to set the appropriate level of rms averaging. Set the value of the rms averaging capacitor based on the peak to average ratio and bandwidth of the input signal and based on the desired output response time and residual output noise. VRMS RMS Detector Output. The output from the VRMS pin is proportional to the logarithm of the rms value at the input level. GND Device Ground. Connect the GND pin to system ground using a low impedance path.,, Differential Digital Outputs of Threshold Detect Flip Flop. latches high when the output of the internal envelope detector exceeds the threshold voltage on the internal comparator VIN input. 4 ENBL Device Enable. Connect the ENBL pin to logic high to enable the device. RST Flip Flop Reset. Taking RST high clears the latched flip flop output, setting the and outputs to low and high, respectively. 6 VIN Inverting Input to the Threshold Detection Comparator. The voltage on this pin is compared to the output voltage of the internal envelope detector, which is driven by the RF input level. If the output voltage of the envelope detector exceeds the voltage on VIN, the flip flop latches the output to high and the output to low. EPAD Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane. 88- Rev. B Page 9 of 7

10 ADL94 TYPICAL PERFORMANCE CHARACTERISTICS VPOS =. V, CRMS = nf, Input levels referred to Ω source. Input RF signal is a sine wave (CW), unless otherwise indicated MHz MHz MHz 9MHz 9MHz 6MHz MHz 8MHz P IN = +dbm P IN = dbm P IN = dbm.6.6 P IN = dbm P IN = dbm Figure. VRMS vs. Input Level (PIN) for Various Frequencies ( MHz to 6 GHz) at C FREUENCY (GHz) Figure 6. VRMS vs. Frequency for Four Input Levels ( MHz to 6 GHz) CALIBRATION AT dbm, dbm, AND +dbm CW 6 AM PEP = 6.8dB 64 AM PEP = 7.dB PSK PEP = 4.dB Figure 4. VRMS and Error from CW Linear Reference vs. Input Level and Signal Modulation (PSK, 6 AM, 64 AM), Frequency = 9 MHz, CRMS = µf (PEP Is Peak Envelope Power) CW 4 CARRIER CDMA PEP =.db CARRIER CDMA PEP =.6dB. CALIBRATION AT dbm, dbm, AND +dbm Figure. VRMS and Error from CW Linear Reference vs. Input Level and Signal Modulation (One-Carrier W-CDMA, Four-Carrier W-CDMA), Frequency =.4 GHz, CRMS = µf CW 6 AM PEP = 6.8dB 64 AM PEP = 7.dB PSK PEP = 4.dB. CALIBRATION AT dbm, dbm, AND +dbm Figure 7. VRMS and Error from CW Linear Reference vs. Input Level and Signal Modulation (PSK, 6 AM, 64 AM), Frequency =.4 GHz, CRMS = µf CW LTE TM -CARRIER MHz PEP =.8dB. CALIBRATION AT dbm, dbm, AND +dbm Figure 8. VRMS and Error from CW Linear Reference vs. Input Level and Signal Modulation (LTE TM One-Carrier, MHz), Frequency =.4 GHz, CRMS = µf Rev. B Page of 7

11 ADL94 RF BURST ENABLE P IN = +dbm RF BURST ENABLE P IN = +dbm P IN = dbm P IN = dbm P IN = dbm P IN = dbm CH mv Ω M µs.ms/s 4ns/pt A CH.4V Figure 9. Output Response to RF Burst Input, Carrier Frequency = 9 MHz, CRMS = nf (see Figure 4 in the Test Circuits Section) 88-9 CH mv Ω M 4µs.MS/s 8ns/pt A CH.4V Figure. Output Response to RF Burst Input, Carrier Frequency = 9 MHz, CRMS = nf (see Figure 4 in the Test Circuits Section) 88- RF BURST ENABLE P = +dbm P = dbm P = dbm INPUT RETURN LOSS (db) NO EXTERNAL SHUNT RESISTOR ON RFIN WITH 8.Ω SHUNT RESISTOR ON RFIN CH V Ω CH mv Ω M 4µs MS/s 8ns/pt A CH.4V Figure. Output Response to Gating on ENBL Pin for Various RF Input Levels, Carrier Frequency = 9 MHz, CRMS = nf.4 6 C. + C +8 C C 4 Figure. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at MHz FREUENCY Figure. Input Return Loss vs. RF Frequency (With and Without External 8. Ω Shunt Resistor) from MHz to 6 GHz OUTPUT (V).4 6 C. + C +8 C C 4 Figure 4. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at MHz Rev. B Page of 7

12 ADL94.4 C. + C +8 C. + C Figure. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at MHz.4 6 C. + C +8 C C 4 Figure 6. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at MHz.4 6 C. + C +8 C C 4 Figure 7. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at 9 MHz OUTPUT (V).4 6 C. + C +8 C C 4 Figure 8. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at MHz OUTPUT (V).4 6 C. + C +8 C C 4 Figure 9. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at MHz OUTPUT (V).4 6 C. + C +8 C C 4 Figure. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at 9 MHz Rev. B Page of 7

13 ADL C. + C +8 C C 4 Figure. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at.9 GHz.4 6 C. + C +8 C C 4 Figure. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at.6 GHz.4 6 C. + C +8 C C 4 Figure. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at. GHz OUTPUT (V).4 6 C. + C +8 C C 4 Figure 4. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at.9 GHz OUTPUT (V).4 6 C. + C +8 C C 4 Figure. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at.6 GHz OUTPUT (V).4 6 C. + C +8 C C 4 Figure 6. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at. GHz Rev. B Page of 7

14 ADL C. + C +8 C C 4 Figure 7. VRMS and Log Conformance Error vs. Input Level (PIN) for Various Temperatures at.8 GHz 88-7 OUTPUT (V).4 6 C. + C +8 C C 4 Figure. Distribution of Log Conformance Error with Respect to Calibration at C vs. Input Level (PIN) for Various Temperatures at.8 GHz 88- FREUENCY (Hits) FREUENCY (Hits) Figure 8. Distribution of VRMS, PIN = dbm, 9 MHz Figure. Distribution of VRMS, PIN = dbm, 9 MHz FREUENCY (Hits) FREUENCY (Hits) SLOPE (mv/db) Figure 9. Distribution of Slope at 9 MHz, Intercept Calculated Using VRMS at dbm and dbm INTERCEPT (dbm) Figure. Distribution of Intercept at 9 MHz, Slope Calculated Using VRMS at dbm and dbm 88- Rev. B Page 4 of 7

15 ADL94 CH.V Ω Mns GS/s A CH.V CH mv Ω T ps/pt Figure. Output Response, PIN = Off to 6 dbm, VIN (4 mv) Set to Trigger at dbm (Overdrive Level = db) 88- CH.V Ω Mns GS/s A CH.V CH.V Ω Figure 6. Output Response, PIN = Off to dbm, VIN (4 mv) Set to Trigger at dbm (Overdrive Level = db) 88-6 CH.V Ω Mns GS/s A CH.V CH mv Ω T ps/pt Figure 4. Output Response, PIN = Off to 9 dbm, Overdrive Threshold Voltage Set to Trigger at dbm (Overdrive Level = db, VIN = 7 mv) 88-4 CH.V Ω Mns GS/s A CH.V CH mv Ω Figure 7. Output Response, PIN = Off to dbm, Overdrive Threshold Voltage Set to Trigger at dbm (Overdrive Level = db, VIN = 7 mv) 88-7 pf pf RST PULSE pf pf CH.V Ω Mns GS/s A CH 4mV CH mv Ω T ps/pt Figure. Output Response vs. Load Capacitance, PIN = Off to dbm; Overdrive Threshold Voltage Set to Trigger at dbm (Overdrive Level = db, VIN = 6 mv) 88- CH.V Ω CH.V Ω Mns GS/s A CH.6V Figure 8. Response of Output to RST 88-8 Rev. B Page of 7

16 ADL94 V IN (V)...GHz.GHz.GHz.9GHz.9GHz.6GHz.6GHz.8GHz SUPPLY CURRENT (ma) C + C +8 C + C. Figure 9. VIN vs. PIN at Various Frequencies 88-9 Figure 4. Supply Current vs. Input Level (PIN) for Various Temperatures 88-4 Rev. B Page 6 of 7

17 ADL94 TEST CIRCUITS ROHDE & SCHWARZ SIGNAL GENERATOR SMR 4 PULSE IN RF OUT AGILENT A FUNCTION/ARBITRATRY WAVEFORM GENERATOR CH CH ADL94 EVALUATION BOARD RFIN VPOS HP E6A POWER SUPPLY VRMS ENBL TEKTRONIX DIGITAL PHOSPHOR OSCILLOSCOPE TDS4 MΩ TRIGGER Figure 4. Hardware Configuration for Output Response to RF Burst Input Measurements 88-4 ROHDE & SCHWARZ SIGNAL GENERATOR SMR 4 PULSE IN RF OUT AGILENT A FUNCTION/ARBITRATRY WAVEFORM GENERATOR CH CH ADL94 EVALUATION BOARD RFIN VPOS HP E6A POWER SUPPLY VRMS ENBL TEKTRONIX DIGITAL PHOSPHOR OSCILLOSCOPE TDS4 MΩ TRIGGER Figure 4. Hardware Configuration for Output Response to ENBL Pin Gating Measurements 88-4 Rev. B Page 7 of 7

18 ADL94 THEORY OF OPERATION The ADL94 is a true rms detector with a 4 db measurement range at.9 GHz with useable range up to 6 GHz. It features no error ripple over its range, low temperature drift, and very low power consumption. Temperature stability of the rms output measurements provides ±. db error (typical) over the temperature range of 4 C to +8 C at up to. GHz. The measurement output voltage scales linearly in decibels with a slope of typically 6.9 mv/db at.9 GHz. The core rms processing of the ADL94 uses a proprietary multistage technique that provides accuracy for complex modulation signals irrespective of the crest factor of the input signal. An integrating filter capacitor at the CRMS pin performs the square domain averaging. RFIN ENBL 4 ADL94 GND ENVELOPE DETECTOR VPOS 7 VIN RST 6 + RMS VCAL CRMS DECL DNC Figure 4. Functional Block Diagram R S VRMS The output of the first signal processing stage (the envelope detector), also drives the noninverting input of a threshold detecting comparator. The inverting input of this comparator is typically driven by a fixed external dc voltage. When the output of the envelope detector exceeds the voltage on the inverting input of the comparator, the comparator goes high. This excursion is then captured and held by an SR flip flop. The state of this flip flop is then held until the level sensitive RST pin is taken high. BASIC CONNECTIONS FOR RMS MEASUREMENT The ADL94 requires a single supply of. V. The supply is connected to the VPOS supply pins. Decouple these pins using V POS.V two capacitors with values equal or similar to those shown in the Figure 44. Place these capacitors as close to Pin as possible. Connect Pin (GND) and the exposed pad to a ground plane with low electrical and thermal impedance. A single-ended input at the RFIN pin drives the ADL94. Because the input is dc-coupled, an external ac coupling capacitor must be used. A 47 nf capacitor is recommended for applications that require frequency coverage from 6 GHz down to tens of kilohertz. For applications that do not need such low frequency coverage, a larger value of capacitance can be used. In addition to the ac-coupling capacitor, an external 8. Ω shunt resistor is required to provide a wideband input match. Figure shows a comparison of the input return loss, with and without the external shunt resistor. The rms measurement voltage is available on the VRMS pin. Place a nf load capacitor on this pin. The DECL pin provides a bypass capacitor connection for an on-chip regulator. The DECL pin is connected to ground with a 4. Ω resistor and a. µf capacitor. The CRMS pin is the averaging node for the rms computation. Place an rms averaging capacitor between the CRMS and DECL pins. For information on choosing the CRMS capacitor, see the Choosing a Value for CRMS section. Using smaller values for CRMS allows quicker response times to a pulsed waveform. Higher values of CRMS are required for correct rms computation as the peak to average ratio of modulated signals increases and the bandwidth of the modulated signals decreases. If the threshold detection circuitry is not used, the VIN pin can be tied to VPOS or left open (this pin has an internal pull-up to VPOS). The ENBL pin configures the device enable interface. Connecting the ENBL pin to a logic high signal ( V to. V) enables the device, and connecting the pin to a logic low signal ( V to.6 V) disables the device. The exposed pad is internally connected to GND and must be soldered to a low impedance ground plane..µf pf ENABLE/ DISABLE ENBL VPOS 4 7 VIN RST 6 ADL94 + R S RFIN 47nF RFIN ENVELOPE DETECTOR RMS VRMS V RMS 8.Ω GND VCAL CRMS DECL DNC nf nf 4.Ω Rev. B Page 8 of 7 nf Figure 44. Basic Connections for RMS Power Measurement 88-4

19 ADL94 CHOOSING A VALUE FOR C RMS CRMS provides the averaging function for the internal rms computation. Using the minimum value for CRMS allows the quickest response time to a pulsed waveform, but leaves significant output noise on the output voltage signal. However, a large filter capacitor reduces output noise and improves the rms measurement accuracy but at the expense of the response time. In applications where the response time is not critical, place a relatively large capacitor on the CRMS pin. In Figure 44, a value of nf is used. For most signal modulation schemes, this value ensures excellent rms measurement accuracy and low residual output noise. There is no maximum capacitance limit for CRMS. Figure 4 and Figure 46 show how output noise varies with CRMS when the ADL94 is driven by a single-carrier W-CDMA (Test Model TM-64, peak envelope power =.6 db, bandwidth =.84 MHz) and by an LTE signal (Test Model TM-, peak envelope power =.8 db, bandwidth = MHz), respectively. Figure 4 and Figure 46 also show how the value of CRMS affects the response time. This response time is measured by applying an RF burst at.4 GHz at dbm to the ADL94. The % to 9% rise time and 9% to % fall time are then measured. RISE/FALL TIMES (µs) k k k. % TO 9% RISE TIME (µs) 9% TO % FALL TIME (µs) OUTPUT NOISE (mv p-p).. C RMS CAPACITANCE (nf) Figure 4. Output Noise, Rise and Fall Times vs. CRMS Capacitance, Single-Carrier W-CDMA (Test Model TM-64) at 9 MHz with PIN = dbm 6 4 OUTPUT NOISE (mv p-p) RISE/FALL TIMES (µs) Rev. B Page 9 of 7 k k k.. % TO 9% RISE TIME (µs) 9% TO % FALL TIME (µs) OUTPUT NOISE (mv p-p). C RMS CAPACITANCE (nf) Figure 46. Output Noise, Rise and Fall Times vs. CRMS Capacitance, Single-Carrier LTE (Test Model TM-) at 9 MHz with PIN = dbm Table shows the recommended minimum values of CRMS for various modulation schemes. Table also shows the output rise and fall times and noise performance. Using lower capacitor values results in faster response times but can result in degraded rms measurement accuracy. If the output noise shown in Table is unacceptably high, it can be reduced by increasing CRMS or by implementing an averaging algorithm after the output voltage of the ADL94 is sampled by an analog-to-digital converter (ADC). The values in Table were experimentally determined to be the minimum capacitance that ensures good rms accuracy for that particular signal type. This test was initially performed with a large capacitance value on the CRMS pin (for example, µf). The value of VRMS was noted for a fixed input level (for example, dbm). The value of CRMS was then progressively reduced (this can be accomplished with press-down capacitors) until the value of VRMS started to deviate from its original value (this indicates that the accuracy of the rms computation is degrading and that CRMS is becoming too small). In general, the minimum CRMS value required increases as the peak to average ratio of the carrier increases. The minimum required CRMS also tends to increase as the bandwidth of the carrier decreases. With narrow-band carriers, the noise spectrum of the VRMS output tends to have a correspondingly narrow profile. The relatively narrow spectral profile requires a larger value of CRMS that reduces the low-pass corner frequency of the averaging function and ensures a valid rms computation. Table. Recommended Minimum CRMS Values for Various Modulation Schemes Peak Envelope Modulation/Standard Power Ratio Ratio (db) Carrier Bandwidth (MHz) CRMSMIN (nf) Output Noise (mv p-p) Rise/Fall Times (µs) PSK, MSPS (SR COS) Filter, α =.). 4 4/ PSK, MSPS (SR COS Filter, α =.). 8./6 64 AM, MSPS (SR COS Filter, α =.) /76 64 AM, MSPS (SR COS Filter, α =.) /76 64 AM, MSPS (SR COS Filter, α =.) / W-CDMA, One-Carrier, TM /76 W-CDMA Four-Carrier, TM-64, TM-, TM-6, TM /76 LTE, TM, One-Carrier, MHz (48 PSK Subcarriers).8 8 / OUTPUT NOISE (mv p-p) 88-47

20 ADL94 VRMS CALIBRATION AND ERROR CALCULATION The measured transfer function of the ADL94 at 9 MHz is shown in Figure 47, which contains plots of both output voltage and log conformance error vs. input level for one device. As the input level varies from dbm to + dbm, the output voltage varies from mv to approximately.7 V V OUT + C V OUT C.4 V OUT +8 C ERROR + C. ERROR C ERROR +8 C Figure 47. VRMS and Log Conformance Error at 9 MHz, 4 C, + C, and +8 C with Log Conformance Error Calculated Based on Two-Point Calibration at dbm and + dbm Calibration must be performed to achieve high accuracy because the output voltage for a particular input level varies from device to device. For a two-point calibration, the equation for the idealized output voltage is VRMS (IDEAL) = Slope (PIN Intercept) () where: Slope is the change in output voltage divided by the change in input level (unit is mv/db). PIN is the input level (unit is dbm). Intercept is the calculated input level at which the output voltage is equal to V (note that Intercept is an extrapolated theoretical value and not a measured value). Intercept has a unit of dbm. In general, calibration is performed during equipment manufacture by applying two or more known signal levels to the input of the ADL94 and measuring the corresponding output voltages. The calibration points must be within the linear operating range of the device. With a two-point calibration, calculate the slope and intercept as follows: Slope = (VRMS VRMS)/(PIN PIN) () Intercept = PIN (VRMS/Slope) () After the slope and intercept are calculated (and stored in some form), use the following equation to calculate an unknown input level based on the output voltage of the detector: PIN (Unknown) = (VRMS (MEASURED)/Slope) + Intercept (4) The log conformance error is the difference between this straight line and the actual performance of the detector. Error (db) = (VRMS (MEASURED) VRMS(IDEAL))/Slope () Use multipoint calibration to extend the measurement dynamic range further. In this case, the transfer function is segmented, with each segment having its own slope and intercept. Figure 48 shows the error plot of the same device with calibration points at dbm, dbm, and + dbm. The three-point calibration results in tighter log conformance and a slight extension of the linear operating range of the device V OUT + C V OUT C.4 V OUT +8 C ERROR + C. ERROR C ERROR +8 C Figure 48. VRMS and Log Conformance Error at 9 MHz, 4 C, + C, and +8 C with Log Conformance Error Calculated Based on Three-Point Calibration at dbm, dbm, and + dbm Where three-point calibration is used, two values of slope and two values of intercept must be calculated and stored during calibration. In addition, the transition point between the two calibration regions must be recorded so that the system knows which slope/intercept pair to use. In a typical system, the output of the ADL94 is sampled by a precision ADC. For the example in Figure 48 (calibration points at dbm, dbm, and + dbm), the ADC output code for an input power of dbm is stored with the calculated slopes and intercept. When the system is in operation in the field, the code from the ADC is compared to this stored code to determine whether to use the upper or lower slope/intercept pair. The calibration scheme for ADL94 can be extended beyond three points. This technique can be used, for example, to linearize the response for input powers below dbm. This effort, however, is less beneficial if the device is to be used over a wide temperature range. The multidevice plots (see Figure, Figure 9 to Figure, Figure to Figure 7, and Figure ) show how temperature stability becomes less predictable at low input power level Rev. B Page of 7

21 ADL94 BASIC CONNECTIONS FOR THRESHOLD DETECTION V POS.V THRESHOLD VOLTAGE INPUT RESET INPUT.µF pf ENABLE/ DISABLE ENBL VPOS 4 7 VIN RST 6 ADL94 + R S RFIN 47nF RFIN ENVELOPE DETECTOR RMS VRMS 8.Ω GND VCAL CRMS DECL DNC CALIBRATION VOLTAGE OUTPUT Figure 49 shows the basic connections for operating the ADL94 in threshold detection mode. A threshold voltage is applied to the VIN input that corresponds to the RF power level at which the circuit trips. When the level on RFIN drives the envelope detector to an output voltage that exceeds the programmed threshold, the comparator output goes high causing the output to latch high and the output to latch low. The levels on and can be reset by setting the RST pin high (note that the RST function is level triggered, not edge triggered). and are held at low and high states respectively as long as RST is high, even if the RF input level is exceeding the programmed threshold voltage. RST must be taken low for the threshold detection circuit to reactivate. AND RESPONSE TIME Figure shows the response of the output when the input power exceeds the programmed threshold by approximately db. The response time from the input power exceeding the threshold to the output reaching % of its final value is approximately ns 4.Ω nf Figure 49. Basic Connections for Threshold Detection The response time of the and outputs is somewhat dependent on the level of overdrive with higher overdrive levels, giving a slightly faster response time. Figure shows the response of the output when the RF input level overdrives the threshold by db, which reduces the response time to approximately ns. Overdrive levels beyond db tend not to reduce the response time below this level. Capacitive loading on and also affects the response time, as shown in Figure. 88- CH.V Ω Mns GS/s A CH 4mV CH mv Ω Figure. Output Response, PIN = Off to dbm, Overdrive Threshold Voltage Set to Trigger at dbm (Overdrive Level = db, VIN = 7 mv) Figure shows the response of the output, which goes low when the input threshold is exceeded. As shown in Figure, the response time of is equal to that of the output. 88- CH.V Ω Mns GS/s A CH.V CH mv Ω Figure. Output Response at 9 MHz, PIN = Off to 9 dbm, Overdrive Threshold Voltage Set to Trigger at dbm (Overdrive Level = db) Rev. B Page of 7 88-

22 ADL94 CH.V Ω Mns GS/s A CH.6V CH mv Ω Figure. Output Response, PIN = Off to 7 dbm, Overdrive Threshold Voltage Set to Trigger at dbm (Overdrive Level = db) SETTING THE V IN THRESHOLD DETECTION VOLTAGE Figure shows the typical relationship between the voltage on the VIN pin and the resulting RF power threshold that causes and to latch high and low, respectively. This data is also presented in Table 6. V IN (V)...GHz.GHz.GHz.9GHz.9GHz.6GHz.6GHz.8GHz. Figure. VIN Threshold Voltage vs. PIN at Various Frequencies Use Figure and Table 6 to set the threshold voltage on the VIN pin. However, because the relationship between the threshold voltage on VIN and the resulting RF threshold power varies from device to device, there is an error level of up to ±. db. For example, if the voltage on VIN is set to cause the circuit to trip when the input power exceeds dbm at 9 MHz (VIN = 4 mv from Table 6), the trip point can vary from device to device by ±. db at frequencies at or above MHz and +. db to. db for frequencies below MHz. In Table 6, no recommended voltages are provided for input power levels below dbm from MHz to. GHz and below dbm at.8 GHz. This is as a result of the increased temperature drift at these input power levels. Likewise, from MHz to. GHz, no recommended voltages are provided for input power levels above dbm because, at this power level, the response of the ADL94 starts to become more nonlinear To set the threshold detect level more precisely, there are two calibration options. A single-point calibration is easily accomplished by applying the threshold trip power level and then adjusting VIN until trips high. Initially, set VIN to a high level such as V, and then assert RST high and back to low to ensure that is low. Next, apply the RF input threshold power level to RFIN. Then, reduce the voltage on VIN until the output goes high. Use this resulting voltage to set the threshold level when the equipment is in operation. Alternatively, by measuring the voltage on the VCAL output pin with and without RF power applied, an equation can be derived that establishes a precise relationship between the VIN voltage and the associated RF input power trip point. Within the linear operating range of the ADL94, there is a linear relationship between VCAL VCALOFF and the input voltage on RFIN. VCAL VCALOFF = Slope (VRFIN Intercept) (6) where: VCAL is the measured output voltage on the VCAL pin. VCALOFF is the measured output voltage on the VCAL pin with no RF input signal applied. VRFIN is the RF input power (in dbm) converted into volts rms, that is, PIN R log = V RFIN (8) where: R is the characteristic impedance (usually Ω). PIN is the input power in dbm. Rewriting the equation results in V CAL V Slope CALOFF = PIN R log Intercept The voltage that must be applied to the VIN pin for a particular input power is equal to (VCAL VCALOFF). Therefore, Equation 9 can be rewritten as VIN = Slope PIN R log Intercept (9) () Rev. B Page of 7

23 ADL94 Table 6. Recommended Typical Values for Threshold Voltage (VIN ) When Operating Uncalibrated Input Threshold Power (dbm) Threshold Voltage (mv) MHz MHz MHz 9 MHz 9 MHz 6 MHz MHz 8 MHz N/A N/A. 9 4 N/A. 4 N/A N/A N/A N/A N/A N/A N/A N/A N/A 64. N/A N/A N/A N/A N/A N/A N/A 64 N/A means not applicable Rev. B Page of 7

24 ADL94 Use a two-point or a three-point calibration to establish the slope and intercept values in Equation. The procedure for a two-point calibration is as follows:. With no RF input signal applied, measure the voltage on the VCAL pin (VCALOFF).. Apply an RF input power that is towards the bottom end of the RF input range (RFINLOW). Calculate the associated rms input voltage (VRMSLOW) and measure the voltage on the VCAL pin (VCALLOW).. Apply an RF input power that is towards the top end of the RF input range (RFINHIGH). Calculate the associated rms input voltage (VRMSHIGH) and measure the voltage on the VCAL pin (VCALHIGH) pin. 4. Calculate SLOPE using the following equation: Slope = (VCALHIGH VCALLOW)/(VRMSHIGH VRMSLOW). Calculate intercept using the following equation: Intercept = VRFIN (VCAL VCALOFF)/Slope When the slope and intercept are known, nsert them into the equation for VIN. V = Slope R log P IN THRESHOLD Intercept where PTHRESHOLD is the desired RF power level at which the circuit trips. () Rev. B Page 4 of 7

25 APPLICATIONS INFORMATION EVALUATION BOARD SCHEMATIC AND CONFIGURATION OPTIONS The ADL94-EVALZ is a fully populated, 4-layer, FR4- based evaluation board. Apply a power supply of. V to the VPOS and GND test loops. To exercise the RMS detector portion of the circuit, apply the RF signal to be measured to the RFIN SMA connector. The corresponding rms output voltage is then available on the VRMS SMA connector and on the TP test point. ADL94 To operate the threshold detection circuitry, apply the RF signal that is being monitored again to the RFIN SMA connector. Apply the dc threshold voltage that causes the circuit to trip to the VIN_N SMA connector or to the TPVIN_N yellow test point. Reset the internal SR flip flop by pressing the RST button. Detailed configuration options for the evaluation board are listed in Table 7. VPOS S 9--- R kω AGND ENBL YEL VPOS R8 RST.kΩ 4 BS C DNI TBD6 R4 kω AGND RFIN JOHNSON AGND TPVIN_N YEL VIN_N JOHNSON C7.µF AGND DNI AGND R TBD4 DNI L TBD4 DNI AGND R Ω C TBD4 DNI R TBD4 DNI L TBD4 DNI AGND R9 Ω C TBD4 DNI C4.47µF R8 8.Ω AGND TCAL YEL R Ω R6 4.Ω C.µF AGND DECL 4 ENBL 4 DECL 6 VIN RFIN 9 CRMS RST VCAL C.µF ADL94ACPZN VPOS VPOS DNC DNC DNC GND EPAD PAD GND BLK C6 pf DUT BAR VRMS AGND Figure 4. Evaluation Board Schematic AGND AGND VPOS RED VPOS C7 X.µF AGND AGND R9 Ω C 4 TBD6 JOHNSON4-7-8 DNI AGND AGND X AGND R Ω C6 TBD6 DNI AGND TP YEL C4 nf AGND 4 JOHNSON4-7-8 AGND R6 VRMS 4 JOHNSON4-7-8 AGND 88-6 Rev. B Page of 7

26 ADL94 Table 7. Evaluation Board Configuration Options Component Function Notes Default Values RFIN, R, R, R, R8, R9, R, L, L, C, C4, C VCAL, VIN_N, TPVIN_N, C7, RF input VCAL threshold calibration R6, C DECL internal decoupling node VPOS, GND, C7, C6 VRMS, TP, R6, C4 C,, X, X, R9, R, C, C6 Power supply interface Output interface RMS averaging capacitor Threshold detect output ( and ) Apply the RF input signal to the ADL94 to the SMA connector labeled RFIN. The ADL94 RFIN pin (Pin ) is dc-coupled and is not internally matched. A broadband Ω match is achieved using an external 8. Ω shunt resistor with a.47 µf ac coupling capacitor placed between the shunt resistor and the RF input. An external preemphasis network can be built to improve flatness vs. frequency using the components between R8 and the RFIN SMA connector. The output voltage from the threshold calibration pin (VCAL, Pin ) is available on the yellow VCAL clip lead. Use the voltage on this pin to determine the correct threshold voltage that must be applied to Pin 6 (VIN ) to set a particular RF power threshold. This process includes two steps: first, measure the output voltage on the VCAL yellow clip lead with no RF signal applied to RFIN (this voltage is approximately 7 mv). Next, apply the RF input power to RFIN, which causes the circuit to trip, and again measure the voltage on the VCAL yellow clip lead. The difference between these two voltages is equal to the voltage that must be applied to VIN during operation. This voltage can be applied either to the VIN_N SMA connector or to the TPVIN_N yellow clip lead. Use C7 to provide noise decoupling of the applied input voltage. A resistor in series with a capacitor to ground must be connected to the DECL pin (Pin 4). Apply the. V power supply for the evaluation board to the VPOS (red) and GND (black) test loops. The nominal supply decoupling consists of a pf capacitor and a. µf capacitor, with the pf capacitor placed closest to the VPOS pin (Pin ). The rms output voltage is available on the VRMS SMA connector or on the TP yellow clip lead. Set the value of the rms averaging capacitor based on the peak to average ratio and bandwidth of the input signal and based on the desired output response time and residual output noise. The threshold detect flip flop outputs ( and ) are available on the SMA connectors labeled and and on the -pin headers labeled X and X. To test the response time of and, remove R9 and R and probe X and X with low capacitance FET probes. ENBL, S, R Enable interface The ADL94 can be enabled by applying. V to the ENBL SMA connector or using the S switch. The enable voltage must be equal to but not greater than the. V supply voltage. RST push-button switch, R4, C, R8 VIN_N, TPVIN_N, C7 Threshold detect reset Threshold detect level set The threshold detect flip-flop is reset using the RST push-button switch. The RST switch is connected the VPOS supply voltage through a. kω resistor (R8). A kω pull-down resistor (R4) is connected to the RST pin, which pulls RST low in the absence of any other stimulus. The ADL94 normally powers up with the and outputs high and low, respectively. A reset on the power-up circuit can be implemented by installing a capacitor on C. When the VPOS supply turns on, RST goes high momentarily before being pulled low by R4. The voltage applied to the VIN_N SMA connector or to the TPVIN_N yellow test loop drives the inverting input of the threshold detect comparator (VIN ) and thereby defines the RF power level that trips the threshold detect comparator and flip flop. The threshold detect voltage can be optionally decoupled using C7. C4=.47uF (4) R8 = 8. Ω (4) R, R9, R = Ω (4) R, R = open (4) L, L = open (4) C, C = open (4) C7 = open (6) C = nf (4) R6 = 4. Ω (4) C7 =. µf (4), C6 = pf (4) VPOS =. V R6 = Ω (4) C4 = nf (6) C =. µf (4) C = C6 = open (6) R9, R = Ω (6) R = kω (6) R4 = kω (6) R8 =. kω (6) C = open (6) C7 = open (6) Rev. B Page 6 of 7

27 ADL94 OUTLINE DIMENSIONS PIN INDICATOR.. S.9. BSC DETAIL A (JEDEC 9) PIN INDICATOR AREA OPTIONS (SEE DETAIL A) EXPOSED PAD.7.6 S PKG SEATING PLANE TOP VIEW TOP VIEW..4.. MAX. NOM COPLANARITY.8. REF 8 BOTTOM VIEW COMPLIANT TOJEDEC STANDARDS MO--WEED-6.. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. --7-E Figure. 6-Lead Lead Frame Chip Scale Package [LFCSP] mm mm Body and.7 mm Package Height (CP-6-) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding Ordering uantity ADL94ACPZN-R7 4 C to + C 6-Lead LFCSP, 7 Tape and Reel CP-6-4 ADL94-EVALZ Evaluation Board Z = RoHS Compliant Part. 6 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D88--7/7(B) Rev. B Page 7 of 7