Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs ADV7192

Transcription

1 a Video Encoder with Six -Bit DACs, 5 MHz Oversampling and Progressive Scan Inputs ADV79 APPLICATIONS DVD Playback Systems PC Video/Multimedia Playback Systems Progressive Scan Playback Systems FEATURES Six High-Quality -Bit Video DACs -Bit Internal Digital Video Processing Multistandard Video Input Multistandard Video Output Oversampling with Internal 5 MHz PLL Programmable Video Control Includes: Digital Noise Reduction Gamma Correction Black Burst LUMA Delay CHROMA Delay Multiple Luma and Chroma Filters Luma SSAF (Super Subalias Filter) Average Brightness Detection Field Counter Macrovision Rev. 7. CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support. Teletext Iertion Port (PAL-WST) -Wire Serial MPU Interface (I C -Compatible and Fast IC) I C Interface Supply Voltage 5 V and 3.3 V Operation 8-Lead LQFP Package GENERAL DESCRIPTION The ADV79 is part of the new generation of video encoders from Analog Devices. The device builds on the performance of previous video encoders and provides new features like interfacing progressive scan devices, Digital Noise Reduction, Gamma Correction, Oversampling and 5 MHz operation, Average Brightness Detection, Black Burst Signal Generation, Chroma Delay, an additional Chroma Filter, and other features. The ADV79 supports NTSC-M, NTSC-N (Japan), PAL N, PAL M, PAL-B/D/G/H/I and PAL- standards. Input standards supported include ITU-R.BT5 :: YCrCb in 8-bit or -bit format and 3 -Bit YCrCb progressive scan format. The ADV79 can output Composite Video (CVBS), S-Video (Y/C), Component YUV or RGB and analog progressive scan in YPrPb format. The analog component output is also compatible with Betacam, MII, and SMPTE/EBU N levels, SMPTE 7 M NTSC, and ITU R.BT 7 PAL. Please see Detailed Description of Features for more information about the ADV79. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM DIGITAL INPUT VIDEO INPUT PROCESSING ANALOG OUTPUT PLL AND 5MHz 7MHz CLOCK CHROMA LPF DEMUX ITU R.BT 5/ 8-BIT YCrCb IN :: FORMAT VIDEO OUTPUT PROCESSING VIDEO SIGNAL PROCESSING AND YCrCbTOYUV MATRIX COLOR DNR GAMMA CORRECTION VBI TELETEXT CLOSED CAPTION CGMS/WSS -BIT DAC OVERSAMPLING SSAF LPF LUMA LPF -BIT DAC -BIT DAC OR -BIT DAC OVERSAMPLING COMPOSITE VIDEO Y [S-VIDEO] C [S-VIDEO] RGB YUV YPrPb TV SCREEN OR PROGRESSIVE SCAN DISPLAY -BIT DAC -BIT DAC IC INTERFACE ADV79 SSAF is a trademark of Analog Devices Inc. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendatio). IC is a registered trademark of Philips Corporation. Throughout the document YUV refers to digital or analog component video. Information furnished by Analog Devices is believed to be accurate and reliable. However, no respoibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 78/39-7 World Wide Web Site: Fax: 78/3-873 Analog Devices, Inc.,

2 ADV79 MPU PORT DESCRIPTION REGISTER ACCESSES REGISTER PROGRAMMING MODE REGISTERS TIMING REGISTERS SUBCARRIER FREQUENCY AND PHASE REGISTERS CLOSED CAPTIONING REGISTERS NTSC PEDESTAL/PAL TELETEXT REGISTERS TELETEXT REQUEST REGISTER CGMS_WSS REGISTERS CONTRAST REGISTER COLOR REGISTERS CC AND CC BIT DESCRIPTIONS HUE ADJUST REGISTER (HCR) HCR BIT DESCRIPTION BRIGHTNESS REGISTER (BCR) BCR BIT DESCRIPTION SHARPNESS RESPONSE REGISTER (PR) PR BIT DESCRIPTION DNR REGISTERS DNR BIT DESCRIPTIONS GAMMA CORRECTION REGISTERS BRIGHTNESS DETECT REGISTER OUTPUT CLOCK REGISTER OCR BIT DESCRIPTIONS APPENDIX Board Design and Layout Coideratio APPENDIX Closed Captioning APPENDIX 3 Copy Generation Management System (CGMS) APPENDIX Wide Screen Signaling APPENDIX 5 Teletext Iertion APPENDIX Optional Output Filter APPENDIX 7 DAC Buffering APPENDIX 8 Recommended Register Values APPENDIX 9 NTSC Waveforms (With Pedestal) NTSC Waveforms (Without Pedestal) PAL Waveforms Video Measurement Plots UV Waveforms Output Waveforms APPENDIX Vector Plots OUTLINE DIMENSIONS CONTENTS FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS Static Performance 5 V Static Performance 3.3 V Dynamic Specificatio 5 V Dynamic Specificatio 3.3 V Timing Characteristics 5 V Timing Characteristics 3.3 V ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDERING GUIDE PACKAGE THERMAL PERFORMANCE PIN FUNCTION DESCRIPTIONS DETAILED DESCRIPTION OF FEATURES GENERAL DESCRIPTION DATA PATH DESCRIPTION INTERNAL FILTER RESPONSE FEATURES: FUNCTIONAL DESCRIPTION BLACK BURST OUTPUT BRIGHTNESS DETECT CHROMA/LUMA DELAY CLAMP OUTPUT CSO, HSO, AND VSO OUTPUTS COLOR BAR GENERATION COLOR BURST SIGNAL COLOR S CHROMINANCE UNDERSHOOT LIMITER DIGITAL NOISE REDUCTION DOUBLE BUFFERING GAMMA CORRECTION NTSC PEDESTAL POWER-ON RESET PROGRESSIVE SCAN INPUT REAL-TIME, SUBCARRIER RESET, AND TIMING RESET SCH PHASE MODE SLEEP MODE SQUARE PIXEL MODE VERTICAL BLANKING DATA INSERTION AND BLANK INPUT YUV LEVELS BIT INTERFACE OVERSAMPLING AND INTERNAL PLL VIDEO TIMING DESCRIPTION RESET SEQUENCE

3 ADV79 SPECIFICATIONS (VAA = 5 V, VREF =.35 V, RSET, = unless otherwise noted. All specificatio TMIN to TMAX 5 V SPECIFICATIONS unless otherwise noted.) Parameter Min Typ STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity3 Differential Nonlinearity3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Input Leakage Current Input Leakage Current5 DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Leakage Current7 Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching3 Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF8 POWER REQUIREMENTS VAA Normal Power Mode IDAC (Max)9 ICCT ( Oversampling), ICCT ( Oversampling), IPLL Sleep Mode IDAC ICCT Max Unit Bits.. LSB LSB..8 ±.5 ma ma RL = 3 Ω RL = Ω RSET, RSET = Ω.5. % V kω pf V V ma ma ma ma µa µa. 85 NOTES All measurements are made in Oversampling Mode unless otherwise specified. Temperature range T MIN to TMAX: C to 7 C. 3 Guaranteed by characterization. For all inputs but PAL_NTSC and ALSB. 5 For PAL_NTSC and ALSB inputs. For all outputs but VSO/TTX/CLAMP. 7 For VSO/TTX/CLAMP output. 8 Measurement made in Oversampling Mode. 9 IDAC is the total current required to supply all DACs including the V REF Circuitry. All six DACs ON. ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specificatio subject to change without notice. 3 VIN =. V or. V ISOURCE = µa ISINK = 3. ma.8 Guaranteed Monotonic V V µa µa pf..5 V V µa pf µa µa Test Conditio IOUT = ma

4 ADV79 SPECIFICATIONS (V = 3.3 V, V =.35 V, R 3.3 V SPECIFICATIONS AA REF SET, = unless otherwise noted. All specificatio TMIN to TMAX unless otherwise noted.) Parameter Min Typ Max Unit Bits.. LSB LSB ± V V µa µa µa pf ISOURCE = µa ISINK = 3. ma V V µa µa pf RL = 3 Ω RL = Ω, RSET, = Ω ma ma % V kω pf IOUT = ma.35 V IVREFOUT = µa STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current3 Input Leakage Current Input Current, IIN Input Capacitance, CIN.8 DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current5 Three-State Leakage Current Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT...5 VOLTAGE REFERENCE Reference Range, VREF7 POWER REQUIREMENTS VAA Normal Power Mode IDAC (Max)8 ICCT ( Oversampling)9, ICCT ( Oversampling)9, IPLL Sleep Mode IDAC ICCT V ma ma ma ma Test Conditio Guaranteed Monotonic VIN =. V or. V µa µa. 85 NOTES All measurements are made in Oversampling Mode unless otherwise specified and are guaranteed by characterization. In Oversampling Mode, power requirement for the ADV79 is typically 3. V. Temperature range T MIN to TMAX: C to 7 C. 3 For all inputs but PAL_NTSC and ALSB. For PAL_NTSC and ALSB inputs. 5 For all outputs but VSO/TTX/CLAMP. For VSO/TTX/CLAMP output. 7 Measurement made in Oversampling Mode. 8 IDAC is the total current required to supply all DACs including the V REF Circuitry. 9 All six DACs ON. ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specificatio subject to change without notice.

5 ADV79 (VAA = 5 V 5 mv, VREF =.35 V, RSET, = unless otherwise noted. All specificatio TMIN to TMAX unless otherwise noted.) 5 V DYNAMIC SPECIFICATIONS Parameter Min Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain3 Differential Phase3 SNR (Pedestal)3 Typ SNR (Ramp)3 Max.9.7 (.) (.5) (78) (78) (.7) (3).3 (.5).5 (.3) Unit Degrees % ±% ± Degrees ±% ±% ±% db db % Degrees db rms db p-p db rms db p-p Test Conditio Referenced to IRE RMS Peak Periodic RMS Peak Periodic NOTES All measurements are made in Oversampling Mode unless otherwise specified and are guaranteed by characterization. Temperature range T MIN to TMAX: C to 7 C. 3 Values in parentheses apply to Oversampling Mode. Specificatio subject to change without notice. (VAA = 3.3 V 5 mv, VREF =.35 V, RSET, = unless otherwise noted. All MIN to TMAX unless otherwise noted.) 3.3 V DYNAMIC SPECIFICATIONS specificatio T Parameter Hue Accuracy Color Saturation Accuracy Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Differential Gain3 Differential Phase3 SNR (Pedestal)3 SNR (Ramp)3 Min Typ Max (.5) (.) (78) (78) () (.5) Unit Degrees % ±% db db ±% ± Degrees ±% % Degrees db rms db p-p db rms db p-p NOTES All measurements are made in Oversampling Mode unless otherwise specified and are guaranteed by characterization. Temperature range T MIN to TMAX: C to 7 C. 3 Values in parentheses apply to Oversampling Mode. Specificatio subject to change without notice. 5 Test Conditio Referenced to IRE RMS Peak Periodic RMS Peak Periodic

6 ADV79 (V = 5 V 5 mv, V 5 V TIMING CHARACTERISTICS specificatio T to T AA MIN Parameter Min Typ REF = MAX.35 V, RSET, = V unless otherwise noted. All unless otherwise noted.) Max Unit khz µs µs µs µs µs Test Conditio MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t SCLOCK Low Pulsewidth, t Hold Time (Start Condition), t3 Setup Time (Start Condition), t Data Setup Time, t5 SDATA, SCLOCK Rise Time, t SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t After This Period the First Clock Is Generated Relevant for Repeated Start Condition ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew MHz Clock Cycles Clock Cycles TELETEXT PORT Digital Output Access Time, t Data Setup Time, t7 Data Hold Time, t8 3 RESET RESET Low Time 3 CLOCK AND PIXEL PORT3 fclock Clock High Time, t9 Clock Low Time, t Data Setup Time, t Data Hold Time, t Control Setup Time, t Control Hold Time, t Digital Output Access Time, t3 Digital Output Hold Time, t Pipeline Delay, t5 ( Oversampling) Pipeline Delay, t5 ( Oversampling) PLL PLL Output Frequency 5 MHz NOTES Temperature range T MIN to TMAX: C to 7 C. Guaranteed by characterization. 3 Pixel Port coists of: Data: P7 P, Y/P8 Y7/P5 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN Teletext Port coists of: Digital Output: TTXREQ Data: TTX Specificatio subject to change without notice.

7 ADV79 (VAA = 3.3 V 5 mv, VREF =.35 V, RSET, = unless otherwise noted. All MIN to TMAX unless otherwise noted.) 3.3 V TIMING CHARACTERISTICS specificatio T Parameter Max Unit khz µs µs µs µs µs MHz Clock Cycles TELETEXT PORT Digital Output Access Time, t Data Setup Time, t7 Data Hold Time, t8 3 RESET RESET Low Time 3 PLL PLL Output Frequency 5 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t SCLOCK Low Pulsewidth, t Hold Time (Start Condition), t3 Setup Time (Start Condition), t Data Setup Time, t5 SDATA, SCLOCK Rise Time, t SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 Min ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew CLOCK AND PIXEL PORT 3 fclock Clock High Time, t9 Clock Low Time, t Data Setup Time, t Data Hold Time, t Control Setup Time, t Control Hold Time, t Digital Output Access Time, t3 Digital Output Hold Time, t Pipeline Delay, t5 ( Oversampling) Typ 8 8, 5 3 MHz NOTES Temperature range T MIN to TMAX: C to 7 C. Guaranteed by characterization. 3 Pixel Port coists of: Data: P7 P, Y/P8 Y7/P5 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN Teletext Port coists of: Digital Output: TTXREQ Data: TTX Specificatio subject to change without notice. 7 Test Conditio After This Period the First Clock Is Generated Relevant for Repeated Start Condition

8 ADV79 t5 t3 t3 SDA t t SCL t t7 t t8 Figure. MPU Port Timing Diagram CLOCK t9 I/PS PIXEL INPUT DATA O/PS t t HSYNC, VSYNC, BLANK Cb Y Cr Y Cb t HSYNC, VSYNC, BLANK, CSO_HSO, VSO, CLAMP Y t3 t Figure. Pixel and Control Data Timing Diagram TTXREQ t CLOCK t7 t8 TTX CLOCK CYCLES CLOCK CYCLES CLOCK CYCLES 3 CLOCK CYCLES CLOCK CYCLES Figure 3. Teletext Timing Diagram CLOCK PROGRESSIVE SCAN INPUT Y Y9 INCLUDING SYNC INFORMATION t9 t t Y Y Y Y3 Y Y5 Cb Cb9 Cb Cb Cb Cb3 Cb Cb5 Cr Cr9 Cr Cr Cr Cr3 Cr Cr5 t Figure. Progressive Scan Input Timing 8

9 ADV79 ABSOLUTE MAXIMUM RATINGS PACKAGE THERMAL PERFORMANCE VAA to GND V Voltage on any Digital Input Pin.. GND.5 V to VAA +.5 V Storage Temperature (TS) C to +5 C Junction Temperature (TJ) C Body Temperature (Soldering, secs) C Analog Outputs to GND GND.5 V to VAA The 8-lead package is used for this device. The junction-toambient (θja) thermal resistance in still air on a four-layer PCB is.7 C. To reduce power coumption when using this part the user can run the part on a 3.3 V supply, turn off any unused DACs. The user must at all times stay below the maximum junction temperature of C. The following equation shows how to calculate this junction temperature: NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditio above those listed in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. Junction Temperature = (VAA (IDAC + ICCT)) θja + 7 C TAMB IDAC = ma + (sum of the average currents coumed by each powered-on DAC) Average current coumed by each powered-on DAC = (VREF K )/RSET VREF =.35 V K =. CSO_HSO VSO/ TTX/CLAMP Cr[] Cr[3] Cr[] Cr[] DGND VDD Cr[] Cr[5] Cr[] Cr[8] Cr[7] Cb[] Cr[9] Cb[] Cb[] VDD Cb[3] DGND PIN CONFIGURATION NC NC RESET PIN IDENTIFIER 59 PAL_NTSC P 3 P 58 RSET 57 V REF 5 COMP P 5 P3 P 7 55 DAC A 5 DAC B P VAA 5 AGND ADV79 LQFP P 9 P7 Y[]/P8 5 DAC C TOP VIEW (Not to Scale) 5 DAC D Y[]/P9 Y[]/P 3 9 AGND 8 VAA 7 DAC E Y[3]/P Y[]/P 5 Y[5]/P3 DAC F Y[]/P 7 RSET 3 DGND 5 COMP Y[7]/P5 8 Y[8] 9 ALSB Y[9] SCRESET/RTC/TR SCL SDA AGND CLKIN CLKOUT VAA DGND VDD TTXREQ Cb[9] Cb[8] Cb[7] Cb[] Cb[5] VSYNC BLANK Cb[] HSYNC VDD NC = NO CONNECT DGND ORDERING GUIDE Model Temperature Range Package Description Package Option ADV79KST C to 7 C 8-Lead Quad Flatpack ST-8 CAUTION ESD (electrostatic discharge) seitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV79 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautio are recommended to avoid performance degradation or loss of functionality. 9 WARNING! ESD SENSITIVE DEVICE

10 ADV79 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Input/ Output, 3 NC P P7 I 8 Y/P8 Y7/P5 I 9,, 3, 8, 79, 33, 3, 9, 8 3 Y8 Y9 VDD DGND P G HSYNC I/O VSYNC I/O 5 BLANK I/O 3, , 9, 5 3 Cb Cb9, Cb Cb3 I TTXREQ O AGND G CLKIN I 37 38, 8, CLKOUT VAA SCL SDA SCRESET/ RTC/TR ALSB RSET I I 5 COMP O 7 5 DAC F DAC E DAC D O O O DAC C DAC B DAC A O O O 5 57 COMP VREF O I/O 58 RSET I 59 PAL_NTSC RESET I I CSO_HSO VSO/TTX/CLAMP O I/O 3 7, 7 7 Cr Cr, Cr5 Cr9 I O P I I/O I Function No Connect. 8-Bit :: Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P (Pin Number 3). -Bit :: Multiplexed YCrCb Pixel Port (Bits 8 5). -Bit Progressive Scan Input for Ydata (Bits 7). -Bit Progressive Scan Input Is Ydata (Bits 8 and 9). Digital Power Supply (3.3 V to 5 V). Digital Ground. HSYNC (Modes,, and 3) Control Signal. This pin may be configured to be an output (Master Mode) or an input (Slave Mode) and accept Sync Signals. VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input (Slave Mode) and accept VSYNC as a Control Signal. Video Blanking Control Signal. This signal is optional. For further information see Vertical Blanking and Data Iertion Blanking Input section. -Bit Progressive Scan Input Port for Cb Data. Teletext Data Request Output Signal, used to control teletext data trafer. Analog Ground. TTL Clock Input. Requires a stable 7 MHz reference clock for standard operation. Alternatively, a.55 MHz (NTSC) or 9.5 MHz (PAL) can be used for square pixel operation. Clock Output Pin. Analog Power Supply (3.3 V to 5 V). MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. Multifunctional Input: Real Time Control (RTC) input, Timing Reset input, Subcarrier Reset input. TTL Address Input. This signal sets up the LSB of the MPU address. A Ω resistor connected from this pin to AGND is used to control full-scale amplitudes of the Video Signals from the DAC D, E, F. Compeation Pin for DACs D, E, and F. Connect a. µf Capacitor from COMP to VAA. S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing.33 ma output. S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing.33 ma output. Composite/Y (Progressive Scan)/Y/Green Analog Output. This DAC is capable of providing.33 ma output. S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing.33 ma output. S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing.33 ma output. Composite/Y(Progressive Scan)/Y/Green Analog Output. This DAC is capable of providing.33 ma output. Compeation Pin for DACs A, B, and C. Connect a. µf Capacitor from COMP to VAA. Voltage Reference Input for DACs or Voltage Reference Output (.35 V). An external VREF cannot be used in Oversampling Mode. A Ω resistor connected from this pin to AGND is used to control full-scale amplitudes of the Video Signals from the DAC A, B, C. Input signal to select PAL or NTSC mode of operation, pin set to Logic selects PAL. The input resets the on-chip timing generator and sets the ADV79 into default mode. See Appendix 8 for Default Register settings. Dual function CSO or HSO Output Sync Signal at TTL Level. Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin. CLAMP TTL output signals can be used to drive external circuitry to enable clamping of all video signals. -Bit Progressive Scan Input Port for Cr Data.

11 ADV79 to input video data in 3 -bit YCrCb progressive scan format to facilitate interfacing devices such as progressive scan systems. DETAILED DESCRIPTION OF FEATURES Clocking: Single 7 MHz Clock Required to Run the Device Oversampling with Internal 5 MHz PLL Square Pixel Operation Advanced Power Management Programmable Video Control Features: Digital Noise Reduction Black Burst Signal Generation Pedestal Level Hue, Brightness, Contrast, and Saturation Clamping Output Signal VBI (Vertical Blanking Interval) Subcarrier Frequency and Phase LUMA Delay CHROMA Delay Gamma Correction Luma And Chroma Filters Luma SSAF (Super Subalias Filter) Average Brightness Detection Field Counter Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Programmable Multimode Master/Slave Operation Macrovision Rev 7. CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support Teletext Iertion Port (PAL-WST) -Wire Serial MPU Interface (IC-Compatible and Fast IC) IC Registers Synchronized to VSYNC Six DACs are available on the ADV79, each of which is capable of providing.33 ma of current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video and YUV Video. All YUV formats (SMPTE/EBU N, MII or Betacam) are supported. The on-board SSAF (Super Subalias Filter) with extended luminance frequency respoe and sharp stopband attenuation enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An additional sharpness control feature allows high-frequency enhancement on the luminance signal. DNR MODE DNR NOISE SIGNAL PATH HSYNC VSYNC BLANK DNR YCrCb- Y TO YUV U MATRIX DNR Y AND GAMMA U CORRECTION V V P BRIGHTNESS AND ADD SYNC AND INTERPOLATOR SATURATION AND ADD BURST AND INTERPOLATOR INPUT FILTER BLOCK FILTER OUTPUT >THRESHOLD? Y DATA INPUT FILTER OUTPUT< THRESHOLD MAIN SIGNAL PATH ADV79 SCL SDA ALSB Cr Cr9 IC MPU PORT PROGRAMMABLE LUMA FILTER AND SHARPNESS FILTER PROGRAMMABLE CHROMA FILTER YUV-TO-RGB MATRIX AND YUV LEVEL BLOCK MODULATOR AND HUE REAL-TIME CIRCUIT SIN/COS DDS BLOCK CLKOUT SCRESET/RTC/TR DNR OUT Figure. Block Diagram for DNR Mode and DNR Sharpness Mode DEMUX PLL ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL NOISE SIGNAL PATH P5 CLKIN GAIN BLOCK SIZE CORING GAIN DATA BORDER AREA CORING GAIN BORDER BLOCK OFFSET CGMS/WSS AND CLOSED CAPTIONING TELETEXT INSERTION BLOCK TTX DNR OUT DNR SHARPNESS MODE RESET TTXREQ FILTER OUTPUT> THRESHOLD MAIN SIGNAL PATH CSO_HSO VIDEO TIMING GENERATOR FILTER OUTPUT <THRESHOLD? Y DATA INPUT The ADV79 is an integrated Digital Video Encoder that converts digital CCIR-/5 :: 8-bit or -bit component video data into a standard analog baseband television signal compatible with worldwide standards. Additionally, it is possible VSO/CLAMP SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL INPUT FILTER BLOCK GENERAL DESCRIPTION PAL_NTSC GAIN BLOCK SIZE CORING GAIN DATA BORDER AREA CORING GAIN BORDER BLOCK OFFSET Figure 5. Detailed Functional Block Diagram Cb Cb9 Y Y9 M U L T I P L E X E R I N T E R P O L A T O R I N T E R P O L A T O R -BIT DAC DAC A -BIT DAC DAC B -BIT DAC DAC C DAC BLOCK VREF RSET COMP -BIT DAC DAC D -BIT DAC DAC F -BIT DAC DAC E DAC BLOCK RSET COMP

12 ADV79 Digital Noise Reduction allows improved picture quality in removing low amplitude, high frequency noise. Figure shows the DNR functionality in the two modes available. Programmable gamma correction is also available. The figure below shows the respoe of different gamma values to a ramp signal. HSO/CSO and VSO TTL outputs are also available and are timed to the analog output video. 3 GAMMA-CORRECTED AMPLITUDE GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. 5 SIGNAL OUTPUTS The ADV79 also incorporates WSS and CGMS-A data control generation..3.5 The ADV79 modes are set up over a -wire serial bidirectional port (IC-compatible) with two slave addresses, and the device is register-compatible with the ADV77. 5 T PU IN AL.5 N G SI The ADV79 is packaged in an 8-lead LQFP package..8 5 DATA PATH DESCRIPTION 5 5 LOCATION For PAL B, D, G, H, I, M, N, and NTSCM, N modes, YCrCb :: data is input via the CCIR-5/-compatible Pixel Port at a 7 MHz Data Rate. The Pixel Data is demultiplexed to form three data paths. Y typically has a range of to 35, Cr and Cb typically have a range of 8 ; however, it is possible to input data from to 5 on both Y, Cb, and Cr. The ADV79 supports PAL (B, D, G, H, I, N, M) and NTSCM, N (with and without Pedestal) and PAL standards. 5 Figure 7. Signal Input (Ramp) and Selectable Gamma Output Curves The device is driven by a 7 MHz clock. Data can be output at 7 MHz or 5 MHz (on-board PLL) when oversampling is enabled. Also, the output filter requirements in oversampling and oversampling differ, as can be seen in Figure 8. Digital noise reduction can be applied to the Y signal. Programmable gamma correction can also be applied to the Y signal if required. FILTER REQUIREMENTS db The Y data can be manipulated for contrast control and a setup level can be added for brightness control. The Cr, Cb data can be scaled to achieve color saturation control. All settings become effective at the start of the next field when double buffering is enabled. FILTER REQUIREMENTS 3dB.75MHz 3.5MHz 7.MHz.5MHz 5.MHz Figure 8. Output Filter Requirements in Oversampling Mode ADV79 MPEG The Output Video Frames are synchronized with the incoming data Timing Reference Codes. Optionally, the Encoder accepts (and can generate) HSYNC, VSYNC, and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in master mode. PIXEL BUS 7MHz ENCODER CORE 5MHz PLL I N T E R P O L A T I O N The U and V signals are modulated by the appropriate Subcarrier Sine/Cosine waveforms and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. The resulting U and V signals are added together to make up the Chrominance signal. The Luma (Y) signal can be delayed by up to six clock cycles (at 7 MHz) and the Chroma signal can be delayed by up to eight clock cycles (at 7 MHz). D A C O U T P U T S The appropriate sync, blank, and burst levels are added to the YCrCb data. Macrovision antitaping, closed-captioning and teletext levels are also added to Y and the resultant data is interpolated to 5 MHz ( Oversampling Mode). The interpolated data is filtered and scaled by three digital FIR filters. 5MHz OUTPUT RATE The Luma and Chroma signals are added together to make up the Composite Video Signal. All timing signals are controlled. The YCrCb data is also used to generate RGB data with appropriate sync and blank levels. The YUV levels are scaled to output the suitable SMPTE/EBU N, MII, or Betacam levels. Figure 9. PLL and Oversampling Block Diagram The ADV79 also supports both PAL and NTSC square pixel operation. In this case the encoder requires a.55 MHz Clock for NTSC or 9.5 MHz Clock for PAL square pixel mode operation. All internal timing is generated on-chip. Each DAC can be individually powered off if not required. A complete description of DAC output configuratio is given in the Mode Register section. An advanced power management circuit enables optimal control of power coumption in normal operating modes or sleep modes. Video output levels are illustrated in Appendix 9.

13 ADV79 When to used to interface progressive scan systems, the ADV79 allows to input YCrCb signals in Progressive Scan format (3 -bit) before these signals are routed to the interpolation filters and the DACs. several different frequency respoes including five low-pass respoes, a CIF respoe, and a QCIF respoe, as can be seen in the following figures. All filter plots show the Oversampling respoes. INTERNAL FILTER RESPONSE In Extended Mode there is the option of respoes in the range from db to + db. The desired respoe can be chosen by the user by programming the correct value via the IC. The variation of frequency respoes can be seen in the Tables I and II. For more detailed filter plots refer to Analog Devices Application Note AN-5. The Y Filter supports several different frequency respoes including two low-pass respoes, two notch respoes, an Extended (SSAF) respoe with or without gain boost/attenuation, a CIF respoe, and a QCIF respoe. The UV filters support Table I. Luminance Internal Filter Specificatio ( Oversampling) Filter Type Low-Pass (NTSC) Low-Pass (PAL) Notch (NTSC) Notch (PAL) Extended (SSAF) CIF QCIF Filter Selection MR MR3 MR Passband Ripple (db) 3 db Bandwidth (MHz) Monotonic..8.3/.9/. 3./5./ NOTES Passband Ripple is defined as the fluctuatio from the db respoe in the passband, measured in (db). The passband is defined to have fc frequency limits for a low-pass filter, f and f infinity for a notch filter, where fc, f, f are the 3 db points. 3 db bandwidth refers to the 3 db cutoff frequency. Table II. Chrominance Internal Filter Specificatio ( Oversampling) Filter Type.3 MHz Low-Pass.5 MHz Low-Pass. MHz Low-Pass. MHz Low-Pass 3. MHz Low-Pass CIF QCIF Filter Selection MR7 MR MR5 Passband Ripple (db) 3 db Bandwidth (MHz).9 Monotonic Monotonic.8 Monotonic Monotonic Monotonic NOTES Passband Ripple is defined as the fluctuatio from the db respoe in the passband, measured in (db). The passband is defined to have fc frequency limits for a low-pass filter, f and f infinity for a notch filter, where fc, f, f are the 3 db points. 3 db bandwidth refers to the 3 db cutoff frequency. 3

14 MAGNITUDE db MAGNITUDE db ADV79 Typical Performance Characteristics FREQUENCY MHz FREQUENCY MHz 7 TPC. PAL Low-Pass Luma Filter 8 FREQUENCY MHz TPC 5. Extended Mode (SSAF) Luma Filter MAGNITUDE db MAGNITUDE db 5 8 FREQUENCY MHz TPC. PAL Notch Luma Filter MAGNITUDE db MAGNITUDE db TPC. NTSC Low-Pass Luma Filter FREQUENCY MHz TPC 3. NTSC Notch Luma Filter 3 FREQUENCY MHz 5 7 TPC. Extended SSAF Luma Filter and Programmable Gain/Attenuation Showing + db/ db Range

15 ADV79 MAGNITUDE db MAGNITUDE db FREQUENCY MHz TPC 7. Extended SSAF and Programmable Attenuation, Showing Range db/ db 8 FREQUENCY MHz TPC. Luma QCIF Filter 5 MAGNITUDE db MAGNITUDE db FREQUENCY MHz FREQUENCY MHz 7 TPC 9. Luma CIF Filter 8 FREQUENCY MHz TPC. Chroma.5 MHz Low-Pass Filter MAGNITUDE db MAGNITUDE db TPC 8. Extended SSAF and Programmable Gain, Showing Range db/+ db 8 FREQUENCY MHz TPC. Chroma. MHz Low-Pass Filter 5

16 MAGNITUDE db MAGNITUDE db ADV FREQUENCY MHz FREQUENCY MHz 5 8 FREQUENCY MHz TPC. Chroma CIF Filter MAGNITUDE db MAGNITUDE db TPC 3. Chroma.3 MHz Low-Pass Filter 7 TPC. Chroma MHz Low-Pass Filter 8 FREQUENCY MHz TPC 7. Chroma QCIF Filter MAGNITUDE db FREQUENCY MHz TPC 5. Chroma 3 MHz Low-Pass Filter

17 ADV79 FEATURES: FUNCTIONAL DESCRIPTION CSO, HSO, AND VSO OUTPUTS BLACK BURST OUTPUT The ADV79 supports three output timing signals, CSO (composite sync signal), HSO (Horizontal Sync Signal) and VSO (Vertical Sync Signal). These output TTL signals are aligned with the analog video outputs. See Figure for an example of these waveforms. (Mode Register 7.) It is possible to output a black burst signal from two DACs. This signal output is very useful for professional video equipment since it enables two video sources to be locked together. (Mode Register 9.) EXAMPLE:- NTSC DIGITAL DATA GENERATOR ADV OUTPUT VIDEO CVBS BLACK BURST OUTPUT CSO CVBS DIGITAL DATA GENERATOR HSO ADV79 VSO Figure. Possible Application for the Black Burst Output Signal Figure. CSO, HSO, VSO Timing Diagram COLOR BAR GENERATION BRIGHTNESS DETECT This feature is used to monitor the average brightness of the incoming Y video signal on a field by field basis. The information is read from the IC and based on this information the color saturation, contrast and brightness controls can be adjusted (for example to compeate for very dark pictures). (Brightness Detect Register.) The ADV79 can be configured to generate /7.5/75/7.5 color bars for NTSC or //75/ color bars for PAL. (Mode Register.) COLOR BURST SIGNAL The burst information can be switched on and off the composite and chroma video output. (Mode Register.) CHROMA/LUMA DELAY COLOR S The luminance data can be delayed by maximum of six clock cycles. Additionally the Chroma can be delayed by a maximum of eight clock cycles (one clock cycle at 7 MHz). (Timing Register and Mode Register 9.) The ADV79 allows the user to control the brightness, contrast, hue and saturation of the color. The control registers may be double-buffered, meaning that any modification to the registers will be done outside the active video region and, therefore, changes made will not be visible during active video. Contrast Control Contrast adjustment is achieved by scaling the Y input data by a factor programmed by the user. This factor allows the data to be scaled between % and 5%. (Contrast Control Register.) CHROMA DELAY Figure. Chroma Delay LUMA DELAY Figure. Luma Delay Brightness Control The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the Y data. For NTSC with pedestal, the setup can vary from IRE to.5 IRE. For NTSC without pedestal and PAL, the setup can vary from 7.5 IRE to +5 IRE. (Brightness Control Register.) Color Saturation CLAMP OUTPUT The ADV79 has a programmable clamp TTL output signal. This clamp signal is programmable to the front and back porch. The clamp signal can be varied by one to three clock cycles in a positive and negative direction from the default position. (Mode Register 5, Mode Register 7.) CLAMP O/P SIGNALS CVBS OUTPUT PIN MR57 = CLAMP OUTPUT PIN MR57 = Figure 3. Clamp Output Timing Color adjustment is achieved by scaling the Cr and Cb input data by a factor programmed by the user. This factor allows the data to be scaled between % and %. (U Scale Register and V Scale Register.) Hue Adjust Control The hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodified, i.e., only the phase between the video and the colorburst is modified and hence the hue is shifted. The ADV79 provides a range of ± in increments of (Hue Adjust Register.) CHROMINANCE The color information can be switched on and off the composite, chroma and color component video outputs. (Mode Register.) 7

18 ADV79 UNDERSHOOT LIMITER POWER-ON RESET A limiter is placed after the digital filters. This prevents any synchronization problems for TVs. The level of undershoot is programmable between.5 IRE, IRE, IRE when operating in Oversampling Mode. In Oversampling Mode the limits are 7.5 IRE and IRE. (Mode Register 9 and Timing Register.) After power-up, it is necessary to execute a RESET operation. A reset occurs on the falling edge of a high-to-low traition on the RESET pin. This initializes the pixel port such that the data on the pixel inputs pi is ignored. See Appendix 8 for the register settings after RESET is applied. PROGRESSIVE SCAN INPUT DIGITAL NOISE REDUCTION DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR Input Select). The absolute value of the filter output is compared to a programmable threshold value (DNR Threshold Control). There are two DNR modes available: DNR Mode and DNR Sharpness Mode. It is possible to input data to the ADV79 in progressive scan format. For this purpose the input pi Y/P8 Y7/P5, Y8 Y9, Cr Cr9 and Cb Cb9 accept -bit Y data, -bit Cb data and -bit Cr data. The data is clocked into the part at 7 MHz. The data is then filtered and sinc corrected in an Interpolation filter and then output to three video DACs at 5 MHz (to interface to a progressive scan monitor). In DNR Mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (Coring Gain Control) of this noise signal will be subtracted from the original signal. In DNR Sharpness Mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (Coring Gain Control) will be added to the original signal in order to boost high frequency components and to sharpen the video image. AMPLITUDE db 3 5 In MPEG systems it is common to process the video information in blocks of 8 8 pixels for MPEG systems, or pixels for MPEG systems ('Block Size Control'). DNR can be applied to the resulting block traition areas that are known to contain noise. Generally the block traition area contai two pixels. It is possible to define this area to contain four pixels (Border Area Control). 7 DOUBLE BUFFERING 3 AMPLITUDE db GAMMA CORRECTION In NTSC mode it is possible to have the pedestal signal generated on the output video signal. (Mode Register.) 5 Double buffering can be enabled or disabled on the following registers: Closed Captioning Registers, Brightness Control Register, V-Scale, U-Scale Contrast Control Register, Hue Adjust Register, Macrovision Registers, and the Gamma Curve Select bit. These registers are updated once per field on the falling edge of the VSYNC signal. Double Buffering improves the overall performance of the ADV79, since modificatio to register settings will not be made during active video, but take effect on the start of the active video. (Mode Register 8.) NTSC PEDESTAL 5 FREQUENCY MHz Figure 5. Plot of the Interpolation Filter for the Y Data It is also possible to compeate for variable block positioning or differences in YCrCb pixel timing with the use of the Block Offset Control. (Mode Register 8, DNR Registers.) Gamma correction may be performed on the luma data. The user has the choice to use either of two different gamma curves, A or B. At any one time one of these curves is operational if gamma correction is enabled. Gamma correction allows the mapping of the luma data to a user-defined function. (Mode Register 8, Gamma Correction Registers 3.) FREQUENCY MHz 5 3 Figure. Plot of the Interpolation Filter for the CrCb Data It is assumed that there is no color space conversion or any other such operation to be performed on the incoming data. Thus if these DAC outputs are to drive a TV, all relevant timing and synchronization data should be contained in the incoming digital Y data. An FPGA can be used to achieve this, The block diagram below shows a possible configuration for progressive scan mode using the ADV79. 8

19 ADV79 error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variatio. This effect is reduced by the use of a 3-bit DDS, which generates this SCH. ENCODER ADV79 5MHz PLL 7MHz MPEG PIXEL BUS PROGRESSIVE SCAN DECODER ENCODER CORE 3-BIT INTERFACE I N T E R P O L A T I O N D A C O U T P U T S Figure 7. Block Diagram Using the ADV79 in Progressive Scan Mode The progressive scan decoder deinterlaces the data from the MPEG decoder. This now mea that there are 55 video lines per field in NTSC mode and 5 video lines per field in PAL mode. The duration of the video line is now 3 µs. It is important to note that the data from the MPEG decoder is in :: format. The data output from the progressive scan decoder is in :: format. Thus it is assumed that some form of interpolation on the color component data is performed in the progressive scan decoder IC. (Mode Register 8.) REAL-TIME, SUBCARRIER RESET, AND TIMING RESET Together with the SCRESET/RTC/TR pin and Mode Register (Genlock Control), the ADV79 can be used in (a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or (c) RTC Mode. (a) A TIMING RESET is achieved in holding this pin high. In this state the horizontal and vertical counters will remain reset. On releasing this pin (set to low), the internal counters will commence counting again. The minimum time the pin has to be held high is 37 ( clock cycle at 7 MHz), otherwise the reset signal might not be recognized. (b) The SUBCARRIER PHASE will reset to that of Field at the start of the following field when a low to high traition occurs on this input pin. (c) In RTC MODE, the ADV79 can be used to lock to an external video source. The real-time control mode allows the ADV79 to automatically alter the subcarrier frequency to compeate for line length variatio. When the part is connected to a device that outputs a digital datastream in the RTC format (such as a ADV785 video decoder, see Figure ), the part will automatically change to the compeated subcarrier frequency on a line-by-line basis. This digital datastream is 7 bits wide and the subcarrier is contained in Bits to. Each bit is two clock cycles long. Hex should be written into all four Subcarrier Frequency registers when using this mode. (Mode Register.) Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV79 is configured in RTC mode. Under these conditio (utable video) the Subcarrier Phase Reset should be enabled but no reset applied. In this configuration the SCH Phase will never be reset; this mea that the output video will now track the utable input video. The Subcarrier Phase Reset when applied will reset the SCH phase to Field at the start of the next field (e.g., Subcarrier Phase Reset applied in Field 5 (PAL) on the start of the next field SCH phase will be reset to Field ). (Mode Register.) SLEEP MODE If, after RESET, the SCRESET/RTC/TR and NTSC_PAL pi are both set high, the ADV79 will power up in Sleep Mode to facilitate low power coumption before all registers have been initialized. If Power-up in Sleep Mode is disabled, Sleep Mode control passes to the Sleep Mode control in Mode Register (i.e., control via IC). (Mode Register and Mode Register.) SQUARE PIXEL MODE The ADV79 can be used to operate in square pixel mode. For NTSC operation an input clock of.55 MHz is required. Alternatively, for PAL operation, an input clock of 9.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. Square pixel mode is not available in Oversampling mode. (Mode Register.) VERTICAL BLANKING DATA INSERTION AND BLANK INPUT It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not have line sync or pre-/post-equalization pulses. This mode of operation is called Partial Blanking. It allows the iertion of any VBI data (Opened VBI) into the encoded output waveform, this data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS etc.). Alternatively the entire VBI may be blanked (no VBI data ierted) on these lines. VBI is available in all timing modes. It is possible to allow control over the BLANK signal using Timing Register. When the BLANK input is enabled (TR3 = and input pin tied low), the BLANK input can be used to input externally generated blank signals in Slave Mode,, or 3. When the BLANK input is disabled (TR3 = and input pin tied low or tied high) the BLANK input is not used and the ADV79 automatically blanks all normally blank lines as per CCIR-. (Timing Register.) SCH PHASE MODE The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase 9

20 ADV79 YUV LEVELS Betacam SMPTE MII Sync 8 mv 3 mv 3 mv 3dB.75MHz As the data path is branched at the output of the filters, the luma signal relating to the CVBS or S-Video Y/C output is unaltered. Only the Y output of the YCrCb outputs is scaled. This control allows color component levels to have a peak-peak amplitude of 7 mv, mv or the default values of 93 mv in NTSC and 7 mv in PAL. (Mode Register 5.) -BIT INTERFACE It is possible to input data in -bit format. In this case, the interface only operates if the data is accompanied by separate HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not available in Slave Mode since EAV/SAV timing codes are used. (Mode Register 8.) OVERSAMPLING AND INTERNAL PLL It is possible to operate all six DACs at 7 MHz ( Oversampling) or 5 MHz ( Oversampling). The ADV79 is supplied with a 7 MHz clock synced with the incoming data. Two optio are available: to run the device throughout at 7 MHz or to enable the PLL. In the latter case, even if the incoming data ru at 7 MHz, Oversampling and the internal PLL will output the data at 5 MHz. NOTE In Oversampling Mode the requirements for the optional output filters are different from those in Oversampling. (Mode Register, Mode Register.) See Appendix. MPEG PIXEL BUS 7MHz FILTER REQUIREMENTS Video 7 mv 7 mv 7 mv ENCODE ADV79 ENCODER CORE 5MHz PLL I N T E R P O L A T I O N FILTER REQUIREMENTS db This functionality allows the ADV79 to output SMPTE levels or Betacam levels on the Y output when configured in PAL or NTSC mode. 7.MHz.5MHz 5.MHz Figure 9. Output Filter Requirements in and Oversampling Mode VIDEO TIMING DESCRIPTION The ADV79 is intended to interface to off-the-shelf MPEG and MPEG Decoders. As a coequence, the ADV79 accepts :: YCrCb Pixel Data via a CCIR-5 Pixel Port and has several Video Timing Modes of operation that allow it to be configured as either System Master Video Timing Generator or a Slave to the System Video Timing Generator. The ADV79 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV79 calculates the width and placement of analog sync pulses, blanking levels, and color burst envelopes. Color bursts are disabled on appropriate lines and serration and equalization pulses are ierted where required. In addition the ADV79 supports a PAL or NTSC square pixel operation. The part requires an input pixel clock of.55 MHz for NTSC square pixel operation and an input pixel clock of 9.5 MHz for PAL square pixel operation. The internal horizontal line counters place the various video waveform sectio in the correct location for the new clock frequencies. The ADV79 has four distinct Master and four distinct Slave timing configuratio. Timing Control is established with the bidirectional HSYNC, BLANK and VSYNC pi. Timing Register can also be used to vary the timing pulsewidths and where they occur in relation to each other. (Mode Register, Timing Register,.) RESET SEQUENCE D A C O U T P U T S 3.5MHz 5MHz OUTPUT Figure 8. PLL and Oversampling Block Diagram When RESET becomes active the ADV79 reverts to the default output configuration (see Appendix 8 for register settings). The ADV79 internal timing is under the control of the logic level on the NTSC_PAL pin. When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV79. Output timing signals are still suppressed at this stage. DACs A, B, C are switched off and DACs D, E, F are switched on. When the user requires valid data, Pixel Data Valid Control is enabled (MR = ) to allow the valid pixel data to pass through the encoder. Digital output timing signals become active and the encoder timing is now under the control of the Timing Registers. If at this stage, the user wishes to select a different video standard to that on the NTSC_PAL pin, Standard IC Control should be enabled (MR5 = ) and the video standard required is selected by programming Mode Register (Output Video Standard Selection). Figure illustrates the RESET sequence timing.

21 ADV79 RESET DAC D, DAC E XXXXXXX XXXXXXX BLACK VALUE WITH SYNC VALID VIDEO DAC F XXXXXXX XXXXXXX BLACK VALUE VALID VIDEO DAC A, DAC B, DAC C XXXXXXX VALID VIDEO OFF MR PIXEL_DATA_VALID XXXXXXX DIGITAL TIMING XXXXXXX DIGITAL TIMING SIGNALS SUPPRESSED TIMING ACTIVE Figure. RESET Sequence Timing Diagram ADV79 CLOCK COMPOSITE VIDEO e.g., VCR OR CABLE LCC SCRESET/RTC/TR GLL GREEN/COMPOSITE/Y BLUE/LUMA/U VIDEO DECODER P7 P P9 P ADV785 RED/CHROMA/V GREEN/COMPOSITE/Y BLUE/LUMA/U RED/CHROMA/V H/L TRANSITION COUNT START BITS LOW RESERVED 8 3 BITS RESERVED FSCPLL INCREMENT SEQUENCE BIT 5 BITS RESET RESERVED BIT3 RESERVED RTC TIME SLOT: NOT USED IN ADV VALID SAMPLE INVALID SAMPLE 8/LINE LOCKED CLOCK NOTES: F SC PLL INCREMENT IS BITS LONG, VALUE LOADED INTO ADV79 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS : PLUS BITS :9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV79. SEQUENCE BIT PAL: = LINE NORMAL, = LINE INVERTED NTSC: = NO CHANGE 3RESET BIT RESET ADV79 s DDS Figure. RTC Timing and Connectio