Maintenance/ Discontinued

Transcription

1 CCD Delay Line Series MNS NTSC-Compatible CCD Video Signal Delay Element Overview The MNS is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O s, two CCD delay elements, a clamp bias circuit, resampling s, and booster circuits. The MNS samples the input using the supplied clock signal with a frequency MHz of twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of H (the horizontal scan period) each for the two lines. Features Single.0 V power supply Single chip combining luminance signal delay line and delay line for color signal converted to the low frequency. Low EMI levels from clock during driving Applications VCRs, Video cameras Structure and Operation The MNS consists of the operational s shown in the diagram. The shift register has the structure shown in the supplementary diagram. Shift register clock driver This generates two transfer clock signals, ø and ø, synchronized with the MHz input clock signal. It also generates the sampling clock signals øs and øs', resampling clock signal øsh, and reset clock signal ør based on the timing control. Input s These s alter the analog input signals from the VINC and pins on their way to the shift registers. One adds the bias voltage specified with the bias circuit to the analog signal from the VINC pin. The other applies an "L" level clamp voltage from the clamp circuit to the analog signal from the pin. Pin Assignment ( TOP VIEW ) SOP00-P-0A Analog shift registers These s sample the shift register input signals with the sampling clock, and convert the results to charges, and use transfer clocks ø and ø to transfer the results to the following. detection s These convert the signal charges from the final stage of the analog shift registers into voltage signals. s In the output stage of this s, the voltage signal is executed Sample-and-Hold by resampling, and is outputted at signal output pin of VOC (-pin) and VOY (-pin). Bias circuit This circuit applies a bias voltage to the analog signal from VINC (pin ) to optimize it for the shift register. This circuit applies an "L" level clamp to the analog signal from (pin ) to optimize it for the shift register. Booster circuits These generate reset drain voltages. SDB0007BEM VOC V DD V SS VOY 7 VINC XI V BB includes following four Product lifecycle stage.

2 MNS CCD Delay Line Series Block Diagram V SS V DD VINC XI 7 Bias circuit input input V BB CCD stages CCD. stages detection øs driver ø driver ø driver ør driver Timing adjustment Waveform amplifier adjustment øs' driver Substrate bias generator detection VOC VOY includes following four Product lifecycle stage.

3 CCD Delay Line Series MNS Pin Descriptions Pin No. Symbol Pin Name Remarks VOC Signal output (C) V DD Power supply V SS Ground VOY Signal output (Y) Signal input (Y) V BB Substrate connection Negative voltage pin 7 XI Clock input VINC Signal input (C) Operating Conditions Parameter Symbol min typ max Unit Power supply V DD V Input clock frequency f ck MHz Input clock amplitude (sine wave) v ck V P P Ambient temperature Ta 0 0 C Electrical Characteristics V DD =.0V, V ck =0.V P-P (sine wave), V in =0.V P-P (sine wave), f ck =7.909MHz, Ta= C Parameter Symbol Conditions min typ max Unit Power supply voltage I DD ma Signal bandwidth (Y signal) BWY db for 00 khz value.. Signal bandwidth (C signal) BWC db for 00 khz value.. Insertion gain (Y signal) IGY f sig =00kHz Insertion gain (C signal) IGC f sig =00kHz Total harmonic distortion THD f sig =00kHz.0. % Signal-to-noise ratio S/N Signal output (V p-p )/noise output (rms) db Clock leak NC 7. MHz components for both Y and C signals MHz db 0 0 db Crosstalk CT f sig =00kHz 0 db Delay (Y signal) τ DY. Delay (C signal) τ DC. VO pin output impedance Z OY Z OC Input bias voltage V BIN Applied to input from C signal input pin. V includes following four Product lifecycle stage. Input clamp voltage V CLIN Applied to input from Y signal input pin.70 V Output bias voltage V BO Applied to output from C signal output pin.70 V Output clamp voltage V CLO Applied to output from Y signal output pin.0 V Substrate voltage V BB.0 V µs kω

4 MNS CCD Delay Line Series Shift Register Configuration ør Booster circuit øsh Output amplifier Voltage generator øs' ø ø VDD VOY VSS includes following four Product lifecycle stage.

5 CCD Delay Line Series MNS Application Circuit Example 0µF + V SS 0.µF V DD 0.0µF VINC 000pF 0.7µF XI 7 Bias circuit input V BB 0.0µF CCD stages detection øs driver ø driver ø driver ør driver Timing adjustment Waveform amplifier adjustment øs' driver input CCD. stages Substrate bias generator detection Note: If the external capacitor attached to pin is a electrolytic capacitor, connect the negative pole to pin. 0Ω VOC SA 0Ω VOY SA includes following four Product lifecycle stage.

6 MNS CCD Delay Line Series Package Dimensions (Unit: mm) SOP00-P-0A.7 0.± ±0. 0..±0..±0. New Package Dimensions (Unit: mm) SOP00-P-0G (Lead-free package) ±0. Note) The package of this product will be changed to the following lead-free type (SOP00-P-0G). (0.0).7.0±0.0 Seating plane ± ±0.0.±0.0.0±0.0.7 max ±0. (.0) 0.0±0.0 Seating plane 0 to 0 includes following four Product lifecycle stage.

7 Request for your special attention and precautions in using the technical information and semiconductors described in this book () If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. () The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. () The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. Any applications other than the standard applications intended. () The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. () When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. () Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. includes following four Product lifecycle stage.