Samsung VTU11A0 Timing Controller

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Brooke Wiggins
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1 Samsung VTU11A Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: chipworks.com

2 Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. CAR DYZM Revision 1.0 Published: April 17, 2015

3 Overview Introduction Brief Design Overview Component Descriptions Device Summary Figures To view, please click on the appropriate bookmark in the panel on the left Package Markings Package X-Ray Die Markings Die Photograph Annotated Die Photograph Die Photograph Polysilicon Layer Extracted Areas Die Architecture Schematics Top Level Block Diagram Tx Slice Pair Parallel-to-Serial Converter with Pre-Emphasis Delays Ten-to-One Serializer Five-to-One Multiplexer Interface Buffer Differential Transmit Driver Differential Transmit Driver Pre-Drivers Pre-Drivers Main Driver with Impedance Control Main Driver with Impedance Control Main Driver with Impedance Control Main Driver with Impedance Control Pre-Emphasis Driver Pre-Emphasis Driver

4 2.2.3 Pre-Emphasis Driver Pre-Emphasis Driver Main Driver Pull-Up Main Driver Pull-Down Pre-Emphasis Driver Pull-Up Pre-Emphasis Driver Pull-Down Impedance Control Selector Impedance Control Selector Interface Buffer Inverting Buffer Array

5 Inverting Buffer Array Tx Slice Pair Bond Pads and ESD RC-Triggered Power Clamp Transmit Clocks Clock Divider Loop-Back De-Serializer Programmable Clock Delay Digital Unit Delay Loop-Back SIPO Output Latch Timer One-to-Five Deserializer Enable Logic Buffer Array Interface Buffer Phase-Locked Loop Reference Clock Selector and Divider Reference Clock Divider Phase-Frequency Detector High-Gain Charge Pump Voltage Follower Low-Gain Charge Pump Voltage Follower Op-Amp Loop Filter Summing Amplifier Ring VCO VCO Variable Delay Stage VCO Delay Cell (8X) VCO Delay Cell (4X) VCO Delay Cell (2X) VCO Delay Cell (1X) VCO Delay Cell (2X) VCO Output Buffers with Input Trip-Point Regulation Differential CMOS VCO Buffer VCO Buffer Error Amplifier VCO Cycle Counter

6 Buffer with Differential Slew Correction PLL Post-Divider and TX Clock Drivers Clock Divider Buffer with Differential Slew Correction Buffer with Differential Slew Correction Buffer with Differential Slew Correction Clock Multiplexer Buffer with Differential Slew Correction Clock Gate Clock Divider Buffer with Differential Slew Correction Four-Cycle Delay Phase Picker Programmable Clock Divider Clock Divider Registers Counter Logic Programmable Clock Divider Buffer with Differential Slew Correction Partial DPLL Ring VCO VCO Variable Delay Stage VCO Delay Cell (8X) VCO Delay Cell (4X) VCO Delay Cell (2X) VCO Delay Cell (1X) VCO Delay Cell (2X) VCO Phase Buffer Array VCO Buffer DPLL VCO Cycle Counter Ripple Counter DPLL Post-Scaler Dividers Clock Divider Clock Divider Core VCO Buffer

7 4.6.0 Multiplexer Array DPLL I-DAC Programmable RC-filter Transconductance Amplifier Failing Edge Delay Bias Generation and Impedance Calibration Bandgap Reference Reference DAC Two-to-Four Decoder Level Shifter Three-to-Eight Decoder Internally Referenced V-to-I Converter Externally Referenced V-to-I Converter Internally Referenced V-to-I Converter Pull-Down Impedance Calibration Current Switch Pull-Up Impedance Calibration NMOS Current Mirror NMOS Current Mirror PMOS Current Mirror Internal Voltage Regulator Current-to-Voltage Conversion PMOS Current Mirror Analog Test Access Test Access Decoder Miscellaneous PLL Control Logic Interface Buffer Three-Bit Ripple Counter Interface Buffer Interface Buffer Interface Buffer Interface Buffer

8 7.0.0 Control Logic Bond Pads and ESD Decoupling and Diodes Buffer Array Buffer Array Pass-Through Buffers Interface Buffer Unused Components Interface Buffer Unused Components Unused Components Interface Buffer Cell Library About Chipworks

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MediaTek MSD95C0H DTV SoC

MediaTek MSD95C0H DTV SoC MediaTek MSD95C0H Basic Functional Analysis 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com Basic Functional Analysis 2 Some of the information in this report