SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER

Transcription

1 Internal Look-Ahead Circuitry for Fast Counting Carry Output for N-Bit Cascading Fully Synchronous Operation for Counting Package Optio Include Plastic Small-Outline Packages and Standard Plastic 300-mil IPs description This synchronous, presettable, 4-bit binary counter features an internal carry look-ahead circuitry for application in high-speed counting desig. Synchronous operation is provided by 8 9 having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so itructed by the count-enable (ENP, ) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters; however, counting spikes may occur on the ripple-carry (CO) output. A buffered clock () input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This counter is fully programmable; that is, it may be preset to any number between 0 and 15. As presetting is synchronous, setting up a low level at the load () input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. The clear function for the SN74F161A is asynchronous and a low level at the clear (CL) input sets all four of the flip-flop outputs low regardless of the levels of the clock, load, or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applicatio without additional gating. Itrumental in accomplishing this function are two count-enable (ENP, ) inputs and a ripple-carry (CO) output. Both ENP and must be high to count, and if fed forward to enable CO. CO thus enabled will produce a high-level pulse while the count is 15 (HHHH). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Traitio at ENP or are allowed regardless of the level of the clock input. The SN74F161A features a fully independent clock circuit. Changes at control inputs (ENP,, or ) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditio meeting the setup and hold times. The SN74F161A is characterized for operation from 0 C to 70 C. CL A B C ENP GN O N PACKAGE (TOP VIEW) V CC CO Q A Q B Q C Q POUCTION ATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1993, Texas Itruments Incorporated POST OFFICE BOX ALLAS, TEXAS

2 logic symbol state diagram CL ENP CTIV16 CT = 0 M2 G3 G4 C5/2,3,4+ 3CT = CO A B C , QA QB QC Q This symbol is in accordance with ANSI/IEEE Std and IEC Publication POST OFFICE BOX ALLAS, TEXAS 75265

3 logic diagram (positive logic) CL ENP CO A 2 3 1, 3 14 QA B 4 1, 3 13 QB C 5 1, 3 12 QC 6 1, 3 11 Q POST OFFICE BOX ALLAS, TEXAS

4 logic symbol, each flip-flop TE 1, 3 Q1 Q1 Q2 Q2 logic diagram, each flip-flop (positive logic) TE (Toggle Enable) Q1 Q2 2 4 POST OFFICE BOX ALLAS, TEXAS 75265

5 typical clear, preset, count, and inhibit sequences Illustrated below is the following sequence: 1. Clear outputs to zero 2. Preset to binary twelve 3. Count to thirteen, fourteen, fifteen, zero, one, and two 4. Inhibit CL A ata Inputs B C ENP QA ata Outputs QB QC Q CO Async Clear Sync Clear Preset Count Inhibit POST OFFICE BOX ALLAS, TEXAS

6 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7 V Input voltage range, V I (see Note 1) V to 7 V Input current range ma to 5 ma Voltage range applied to any output in the high state V to V CC Current into any output in the low state ma Operating free-air temperature range C to 70 C Storage temperature range C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. recommended operating conditio MIN NOM MAX UNIT VCC Supply voltage V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IIK Input clamp current 18 ma IOH High-level output current 1 ma IOL Low-level output current 20 ma TA Operating free-air temperature 0 70 C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PAAMETE TEST CONITIONS MIN TYP MAX UNIT VIK VCC = 4.5 V, II = 18 ma 1.2 V VOH VCC = 4.5 V, IOH = 1 ma VCC = 4.75 V, IOH = 1 ma 2.7 VOL VCC = 4.5 V, IOL = 20 ma V II VCC = 5.5 V, VI = 7 V 0.1 ma IIH VCC = 5.5 V, VI = 2.7 V 20 µa ENP,, A, B, C, 0.6 IIL, VCC = 5.5 V, VI = 0.5 V 1.2 ma CL 0.6 IOS VCC = 5.5 V, VO = ma ICC VCC = 5.5 V ma All typical values are at VCC = 5 V, TA = 25 C. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V 2 6 POST OFFICE BOX ALLAS, TEXAS 75265

7 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) VCC = 5 V, TA = 25 C MIN MAX UNIT fclock Clock frequency MHz tw Pulse duration (counting) tsu Setup time MIN MAX high or low (loading) 5 5 High 4 4 Low 6 7 CL low 5 5 ata before High or low 5 5 before ENP and before th Hold time after High Low High Low 5 5 ata after High or low 2 2 High 2 2 Low 0 0 ENP and after High or low 0 0 tsu Inactive-state setup time, CL high before 6 6 Inactive-state state setup time is also referred to as recovery time. switching characteristics (see Note 2) PAAMETE FOM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pf, L = 500 Ω, TA = 25 C VCC = 4.5 V to 5.5 V, CL = 50 pf, L = 500 Ω, TA = MIN to MAX MIN TYP MAX MIN MAX fmax MHz tplh tplh tplh tplh ( high) ( low) CL Any Q Any Q CO CO Any Q CO For conditio shown as MIN or MAX, use the appropriate value specified under recommended operating conditio. NOTE 2: Load circuits and waveforms are shown in Section 1. UNIT POST OFFICE BOX ALLAS, TEXAS

8 2 8 POST OFFICE BOX ALLAS, TEXAS 75265

9 IMPOTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CETAIN APPLICATIONS USING SEMICONUCTO POUCTS MAY INVOLVE POTIAL ISKS OF EATH, PESONAL INJUY, O SEVEE POPETY O ENVIONMAL AMAGE ( CITICAL APPLICATIONS ). TI SEMICONUCTO POUCTS AE NOT ESIGNE, AUTHOIZE, O WAANTE TO BE SUITABLE FO USE IN LIFE-SUPPOT EVICES O SYSTEMS O OTHE CITICAL APPLICATIONS. INCLUSION OF TI POUCTS IN SUCH APPLICATIONS IS UNESTOO TO BE FULLY AT THE CUSTOME S ISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Itruments Incorporated