# Experiment # 4 Counters and Logic Analyzer

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1 EE20L - Introduction to Digital Circuits Experiment # 4. Synopsis: Experiment # 4 Counters and Logic Analyzer In this lab we will build an up-counter and a down-counter using 74LS76A - Flip Flops. The counter output will be observed on the Oscilloscope and the Logic Analyzer. The objective of this lab is to understand the operation of the counter, the differences between an Oscilloscope and a Logic Analyzer, and how to setup the Logic Analyzer (Agilent Logic Analyzer model: 664A) to measure the desired signals. 2. Logic Analyzer Theory and Description: 2. What is a Logic Analyzer? A Logic Analyzer (shown in figure ) is a tool very similar to an Oscilloscope. It measures multiple signals and displays the output vs. time on the screen. One main difference between an oscilloscope and a logic analyzer is that an oscilloscope can precisely display the voltages of the different signals (example: 3.85V, 4.25V). A logic analyzer can not do this. It displays the signals in digital form (either a or a 0). So whether the signal is at 3.85V or 4.25V, it will be recorded as simply (HIGH). This may seem less useful, but is actually an advantage. Since the logic analyzer displays s and 0 s, it is much easier to display more signals at once and debug a problem in a digital system. A logic analyzer can usually display many more signals than an oscilloscope can. Most scopes display 2 to 4 signals while logic analyzers can usually display or record at least 32 signals at once. The logic analyzer we have in the lab has two pods (group of connections) each containing 6 pins to connect to your circuit. You can see that this would be very helpful for debugging a system with many digital signals. Another difference which was hinted at above is the ability to store signals. A logic analyzer can usually store all of the signals it monitors in its signal storage memory. A traditional oscilloscope can not typically store what happened in the past. (A digitizing oscilloscope can store signals). So a traditional oscilloscope needs the signals to be repetitive for it to display the signal in a stable manner. Unlike a traditional oscilloscope, a logic analyzer stores signals and does not require signals to be repetitive. This can be an advantage in many situations where signals are non-repetitive. Many digital systems will wait for a start signal, do the needed computation and go to the DONE state and may not behave like a simple repetitive counter. A logic analyzer is suitable in debugging such systems. ee20l_counters.fm [Revised: 7/23/07] /5

2 EE20L - Introduction to Digital Circuits Experiment # 4 Figure : Front panel of Agilent 664A Logic Analyzer A very important concept to learn is when to use the correct tool. The following sections will give a few guidelines for choosing the right one. 2.2 When to use an Oscilloscope? An oscilloscope is normally used when you need to see small voltage changes in a signal. A logic analyzer cannot do this because it only measures a signal digitally (either or 0). When you wish to see the actual (analog) behavior of a signal such as raise time, fall time, overshoot, ringing, noise, signal deterioration, you use an oscilloscope. Another situation where a scope is needed is for very fast signals. A scope can precisely measure the time between two signals and usually at a higher resolution than a logic analyzer. 2.3 When to use a Logic Analyzer? A logic analyzer is normally used when you need to see many signals at the same time. A scope just cannot do this well. In debugging mother-board of a computer, you may want to see all address signals, all data signals, and several control signals needing 80 to 28 channels! Another advantage of using a logic analyzer is that it sees signals as other digital components in the system would. If a voltage appears to be a signal on a scope it might not be interpreted as a by the digital hardware if the voltage is not high enough. A logic analyzer will see the signal just like the digital hardware would and show these kinds of problems. ee20l_counters.fm [Revised: 7/23/07] 2/5

3 EE20L - Introduction to Digital Circuits Experiment # 4 A third advantage of a logic analyzer is the ability to do complicated triggering. A logic analyzer has the ability to look for a certain pattern of signals and then watch what happens after the pattern in encountered. A scope can only trigger on a raising edge or falling edge of one signal so this is not possible. In digital systems, you may frequently need to watch for a certain pattern of signals to debug a specific problem. May be you want to capture the signal activity when a printer is accessed just after a page-feed-escape-control-sequence was sent to the printer. A logic analyzer works best for this as you will see in the second part of the lab. 2.4 Analysis modes of the Logic Analyzer There are normally two main analysis modes in a logic analyzer. They are Timing Analysis and State Analysis. Timing Analysis is similar to a digital oscilloscope. The vertical axis is the signal ( or 0) and the horizontal axis is time. For a given time step, which can be setup by us, it will measure all of the signal values at each step. Each time step will be represented by one position on the x-axis. A logic analyzer can usually store many time measurements. After it is done measuring, the signals will be displayed on the screen. The trigger point is shown in the middle of the screen. The logic analyzer keeps filling up the storage memory with signal information on a continuous basis (treating the memory as a circular buffer) while waiting for the trigger point. After the trigger point, it (the logic analyzer) fills one half of the memory so that we can see signal activity before and after the trigger. One part of timing analysis that is different from a digital scope is the triggering. On a scope the signal is displayed immediately after the trigger occurs. A logic analyzer continuously captures the data and stops after the trigger signal is contained in the data. The data on both sides of this signal (before and after) is available for review as stated before. State Analysis is a little bit different. In the Timing Analysis mode, the analyzer records the value of each signal at regular time intervals. The frequency at which this scanning takes place is determined by the logic analyzer s internal clock frequency (in our analyzer this could be 25 or 250 Mhz). In case of State Analysis, signal values are measured and recorded based on an external clock. This external clock is usually the system clock used in the design that is being debugged. So, basically, in State Analysis mode, the logic analyzer samples data on the clock but records only those samples which satisfy some specified criterion. Of course, this gives us lower timing resolution of events, but in many situations this summarized view of what s happening in the system is very useful. An example of where state analysis could be useful is microprocessor-based system design. Suppose, you want to know the sequence of memory accesses the system went through. Typically, a microprocessor does not request data from memory on every clock. So, essentially, you want to take measurements every time the address strobe signal is activated. So, you may specify the capture criterion as: Collect one sample on the falling edge of microprocessor clock when the address strobe signal is active. The address strobe signal goes high only once during one memory access and hence you collect only one sample. ee20l_counters.fm [Revised: 7/23/07] 3/5

5 EE20L - Introduction to Digital Circuits Experiment # 4 Waveform: This shows all of the signals you labeled and the results (before and after) after the trigger. This is normally the menu you will be on when you press the run button to see the results. The following buttons help you edit the menu s above or start the measurements. Arrow eys: These should be self-explanatory if you have used a computer before. Select: This buttons selects a highlighted item for changing. Done: Use this button to confirm when you are done changing something in a menu Rotary nob: This knob can control multiple items and is usually used when there is a list to scroll through. Run: This button puts the logic analyzer in measurement mode where it waits for the appropriate trigger before taking the measurements. If the signals are not changing fast enough, it may take some time for the analyzer to fill-up its memory. Stop: This stops the logic analyzer from taking further measurements. You may want to use this if the analyzer is taking too much time to fill-up the buffer memory and you wish to abort and see what it has gathered so far. ee20l_counters.fm [Revised: 7/23/07] 5/5

6 EE20L - Introduction to Digital Circuits Experiment # 4 3. Prelab: 3. : Using your outstanding memory (!?) of EE0, write the function table of a - flip flop and describe what will happen when you tie and both to Vcc. (4+pts) When and are both tied to VCC, : 3. 3: Refer to the data sheet of 74LS76A flip flop and determine whether it is a positive edge triggered flip flop or negative edge triggered flip flop. (5 pts) What are the three main differences between an oscilloscope and a logic analyzer? (2pts) Oscilloscope Logic Analyzer 3. 4: 3. 5: In the state analysis mode, what should the CLOC input (from the Logic Analyzer s pod) be connected to? (5 pts) Which menus would we go to for each of the following operations?(3 pts) Operation Menu To load a format file from the disk To switch from timing analysis to state analysis mode To look at the signals that we are investigating (in a graphical way) ee20l_counters.fm [Revised: 7/23/07] 6/5

7 EE20L - Introduction to Digital Circuits Experiment # 4 4. Procedure: Part : 4-bit ripple counter design using flip-flops Here we are building a 4-bit ripple counter (which counts up only and rolls over) using four Flip-flops (two 74LS76A chips). We display the count on 4 singular LEDs. 4. Using the 74LS76A flip-flops connect the circuit as shown in Figure 3. The pin out of the 74LS76A is given on the side. Notice that the flip flops need to be in toggle mode for the circuit to work properly. The clear (CLR) pins from each flip-flop should be connected together and then to a switch as shown. This CLR signal is active low so connecting opening the switch disables the clear function. to start with keep the switch closed. After you switch-on power, confirm that the counter outputs are all zero. When you open the switch, the counter starts counting. CL PRE CLR VCC 2CL 2PRE 2CLR LS76 GND A B C D CLOC +5V CLR Figure 3: Schematics for a 4-bit counter 4.2 We want you to experiment both sourcing mode and sinking mode of connecting LEDs. Connect A and B to LEDs in sourcing mode and, C and D to LEDs in sinking mode as shown in Figure 4. The current-limiting resistance in series with each LED is 330 ohms. +5V A 330Ω C 330Ω B +5V 330Ω D 330Ω Figure 4: Connection for the LEDs 4.3 We want to clock the above counter using 40Hz clock. Generate a 0 to +5V square wave at 40kHz and verify it on the oscilloscope. 4.4 After verifying the clock signal, connect it (the output of the function generator) to the clock input on your counter circuit. Open the switch controlling the CLR signal All LEDs should appear ON if your circuit is working properly. Note: Actually the LEDs are flickering really fast which makes them appear to be ON continuously. ee20l_counters.fm [Revised: 7/23/07] 7/5

8 EE20L - Introduction to Digital Circuits Experiment # Now adjust the input clock frequency from 40kHz to about Hz on the function generator. You should now see the four LEDs going through the binary counting sequence 0000 to. 4.6 Connect the MSB (Most Significant Bit) D to the Oscilloscope on CH. Set the triggering slope to falling edge. Now connect each of the other four signals C, B, A, and CLOC to CH2 of the scope, one at a time in that order. You should see that each of the signals is 2x as fast as the one before it. Verify that your signals match the waveform shown in figure 5 below. CLOC A B C D Figure 5: 4-bit counter waveform Part 2: Logic Analyzer Next, we are going to capture the output of the counter using the Logic Analyzer. Logic Analyzer in Timing Analyzer mode: 4.7 Connect each of the outputs of the counter (A, B, C and D) to the logic analyzer via pins through 4 of POD 2, as shown in figure 6. Connect A to pin, B to pin 2 and so on. Connect the clock CL also to a pin (pin 0 as shown here) like any other signal. (Here, in Timing Analyzer mode, you do NOT need to connect the clock signal of your circuit to the pin labeled as CL on the pod.) Finally, connect your circuit s ground to the GND pin (black wire) of the logic analyzer. This way, your circuit and the logic analyzer shall have a common ground as a common reference. CLOC from the function generator at 00 Hz 4-bit counter CL A B C D CLR POD 2 Logic Analyzer Figure 6: Logic analyzer pod connection 4.8 Most of the setup of the logic analyzer has been done for you. Load the format file (lab4_ta._a) (TA = Timing Analyzer; just a name to remember) by doing the following steps: Turn on the logic analyzer with the boot-disk in its 3.5 floppy drive and wait for the logic analyzer to boot up. Now remove the boot disk and insert the disk with configuration files. When it boots up, it will be in the config menu. It will say so at the top. Make sure that the analyzer is in the Timing Analyzer mode. ee20l_counters.fm [Revised: 7/23/07] 8/5

9 EE20L - Introduction to Digital Circuits Experiment # 4 Press the SYSTEM button to switch to the system menu.use the rotary knob to select the file named lab4_ta._a. Verify that the operation selector shows load. If it does not say load use the arrow keys to highlight the operation selector. Press the SELECT button and use the arrow keys to select LOAD. Press DONE when you are finished. Now, use the arrow keys to highlight the EXECUTE button and press the SELECT key. The settings for the logic analyzer will now be loaded. 4.9 You should look through the other five menus by pressing the different buttons and look at the settings you just loaded. Specifically, you should look at the TRIGGER menu. 4.0 Go to the FORMAT menu. Here you can see that two of the labels, D and C, have been setup for you. You need to setup the logic analyzer for B and A. Completed FORMAT is shown in figure 7. Figure 7: Complete Timing Format Because you want the information after clear, you can configure the Timing Trace specification menu so that the Analyzer shows the trace point after CLEAR = and A = B = C = D = 0 at the positive edge on A. ee20l_counters.fm [Revised: 7/23/07] 9/5

10 EE20L - Introduction to Digital Circuits Experiment # 4 Figure 8: Timing Trace Specification After the format setup is complete, go to the WAVEFORM menu. Close the clear switch to keep the counter cleared. Press the RUN key and the logic analyzer will wait for the trigger. Open the clear switch. Soon, the logic analyzer will display the captured waveform which will look similar the one shown in figure 9 below.. Figure 9: 4-bit counter waveform ee20l_counters.fm [Revised: 7/23/07] 0/5

11 EE20L - Introduction to Digital Circuits Experiment # 4 By adjusting the time/division setting and delay setting of the waveform menu, you can change the TIME scale magnification and scroll the display to make it appear as below. Figure 0: 4-bit counter waveform Logic Analyzer in State Analyzer mode: In some state machine analysis, it may be desirable to obtain a listing of states rather than waveforms. For example, in a microprocessor-based system debugging, you may want to know the sequence of memory accesses performed by the processor with out unnecessary details. The Agilent logic analyzers have a sophisticated state specification mechanism to capture just the right information you are looking for. 4. The logic analyzer can be configured as a state analyzer in the configuration menu. 4.2 Counter connections: The clock of the POD shall now be connected to the clock of the counter. 4.3 State Trace specification: Here, note that on negative transition of the clock the counter changes count. Hence it is appropriate to sample the counter state at the positive edge of the clock when the count is stable. Note that we specified ^ in the state format specification, which means that the logic analyzer should sample the data at the positive edge of the clock when the count is stable. CLOC from the function generator at 00 Hz 4-bit counter CL A B C D CLR Clock POD 2 Logic Analyzer Figure : Logic analyzer pod connection ee20l_counters.fm [Revised: 7/23/07] /5

12 EE20L - Introduction to Digital Circuits Experiment # 4 Figure : State Format Specification Figure 2: State Trigger Specification ee20l_counters.fm [Revised: 7/23/07] 2/5

13 EE20L - Introduction to Digital Circuits Experiment # The above trace specification captures one complete count sequence (no more, no less). Figure 3: State Listing ee20l_counters.fm [Revised: 7/23/07] 3/5

14 EE20L - Introduction to Digital Circuits Experiment # 4 5. Lab Report: Name: Date: Lab Session: TA s Signature: For TAs: Prelab (out of 30): Hardware (out of 20): Waveform on Oscilloscope (out of 20): Waveform on Logic Analyzer (out of 20): State Listing on Logic Analyzer (out of 20): Report (out of 40): Comments: 5. : Draw the complete circuit (including LEDs, resistors, etc.) as you wired for the counter. Label properly and write the pin number for each input/output. (0pts) Labeling convention: U.4 = Component U pin 4 First 74LS76A = U Second 74LS76A = U2 +5V U.4 U : What will you need to change in the circuit to make the counter a down counter instead of an up counter? Note: Please use outputs only. Do not use outputs. (5 pts) ee20l_counters.fm [Revised: 7/23/07] 4/5

15 EE20L - Introduction to Digital Circuits Experiment # : Given below is an incomplete design for an up/down 3-bit counter. When the control line (up/down) is HIGH, the counter should count up (000, 00,..., ), else it should count down (, 0,..., 000). The desired behavior of the up/down counter is shown in figure 8. Complete the design by adding necessary circuitry and explain how the counter will work. Note: If you need to make different connections to the clock input of a FF, you can use a circuit equivalent to a 2-to- mux (two AND gates and an OR gate). (5 pts) up/down A B C Explanation: CLOC up/down A B C Figure 8: Waveform for the up/down counter 5. 4: Suppose you are building a 6-bit counter (output [5:0]). If your TA asks you to display 9 and on the dual channel oscilloscope, would you trigger the scope with 9 or or any one of them? Explain (0 pts). ee20l_counters.fm [Revised: 7/23/07] 5/5

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