High-Frequency IC Design & Test Webinar Part 2 (Test) Inphi Corporation June 25, 2003

Transcription

1 High-Frequency IC Design & Test Webinar Part 2 (Test) Inphi Corporation June 25, 2003

2 Introduction! Why this webinar is important Attendees will learn innovative techniques for high-frequency and high-speed design. This seminar will give engineers access to experts who will share techniques applicable for design and test.! What to expect This webinar focuses on best practices for high-frequency and high-speed design and test. Development engineers will present techniques for creating leading-edge products. All presentations cover actual product development and test results.! Who should attend Engineers developing instrumentation, military, microwave, or optical network equipment components, modules, or subsystems. The common thread is high-frequency and broadband design at 0 5 GHz and up to GHz, and the drive for significant performance improvements. Inphi Proprietary / Page 2

3 Logistics! If you experience any technical difficulties, call WebEx technical support (866) toll free (916) toll! Brief Q&A session to follow each presentation Please submit questions online using the Q&A tab If you have additional questions following the event, please send an to To download the presentation after the event, please visit and follow the instructions on the home page Inphi Proprietary / Page 3

4 Outline! Test Equipment Needs and Limitations Dr. Kevin Nary, VP Engineering! Jitter Measurements for 10 Gbps PMD ICs Dr. Steffen Nielsen, Principal Design Engineer Dr. Paul van der Wagt, Principal Design Engineer! Frequency Domain Measurements for High-Speed PMD ICs Dr. Carl Pobanz, Principal Design Engineer Inphi Proprietary / Page 4 June 25, 2003 Page 4

5 Test Equipment Needs and Limitations Dr. Kevin Nary, VP of Engineering

6 Overview! Characterization of broadband (1 60 GHz) ICs Devices under test (what are we characterizing) Equipment requirements Cables, connectors! Understanding the test set Equipment limitations Calibration! A real world example Sampling head differences, bandwidth limits, models Inphi Proprietary / Page 6 June 25, 2003 Page 6

7 What Are We Testing?! Optical components 10 & 40 Gbps modulator drivers, transimpedance amplifiers, NRZ-to-RZ converters, multiplexers, demultiplexers! Very high speed logic circuits Type D and T flip-flops, dividers, fanout buffers, encoders, XOR/NOR/NAND gates, etc.! Microwave components Prescalers, VCOs, active splitters! Process technologies Fine-line CMOS, SiGe BiCMOS, GaAs phemt, InP, etc.; GHz transistor F t s Inphi Proprietary / Page 7

8 Packaged Devices 10 Gbps GaAs phemt Modulator Driver 43 Gbps GaAs phemt Modulator Driver 50 Gbps InP HBT D Flip-Flop 50 Gbps InP HBT 4:1 MUX Evaluation Board 25 Gbps D Flip-Flop Inphi Proprietary / Page 8

9 Wafer-Level Characterization! Automated wafer probe with RF probes enables rapid characterization of designs at speed over temperature Inphi Proprietary / Page 9

10 Equipment Needs! Time domain characterization Signal sources: synthesizers, pattern generators High-speed sampling scopes Anritsu MG3690A Synthesizer Inphi Proprietary / Page 10

11 Equipment Needs (con t.)! Time domain characterization Bit error rate testers (BERTs) Anritsu ME7760A 43.5 Gbps Agilent ParBERT with 4868A mux and 4869B demux BER test system 4-channel, 12.5 Gbps error detector 4-to-1, 43 Gbps mux 1-to-4, 43 Gbps demux 4 X 12.5 Gbps Pattern Generator Inphi Proprietary / Page 11

12 Equipment Needs (con t.)! Frequency domain Network analyzers Spectrum analyzer Phase noise analyzer Agilent PSA Series Spectrum Analyzer Anritsu ME7808A 40 MHZ to 110 GHz Vector Network Analyzer Inphi Proprietary / Page 12

13 Cables & Connectors! Understand bandwidth, loss characteristics of cables, connectors, probes... Cable attenuation skin effect and dielectric loss Attenuation (db/m) Attenuation versus frequency of good 3.8 mm coax 85 C 25 C DC Inphi Proprietary / Page Frequency (GHz)

14 Cables & Connectors (con t.)! Connector and cable bandwidths Coax connectors and cables support higher order electromagnetic modes at frequencies dependant on their geometry and dielectric Bandwidth of good 3.8 mm cable with different connectors N SMA GPPO K V 2.4 mm 3.5 mm TE mode cutoff frequency F c = 2c π ε r (D+d) DC Frequency (GHz) Inphi Proprietary / Page 14

15 Cables & Connectors (con t.)! Understand bandwidth, loss characteristics of cables, connectors, probes Example: TE cutoff frequency of SMA connector 0 Response of 5.5 mm cable with SMA connector db S11 S Frequency (GHz) Inphi Proprietary / Page 15

16 Real World Example! Characterization of 10 Gbps modulator driver Wafers come back from the fab you get everything set up, turn on the supplies and test equipment, and get the ugly-looking eye shown here. What s going on? Inphi Proprietary / Page 16

17 10 Gbps Modulator Driver Test Set! What does the test setup look like? Test setup for wafer level test of 10 Gbps modulator driver Pattern Generator 3.5 mm connector 2.4 mm connector Probes 2.4 mm to 3.5 mm adaptor Oscilloscope Wafer 25 cable with 3.5 mm connectors DC block 36 cable with 3.5 mm connectors Inphi Proprietary / Page 17

18 Equipment Differences! Characterize the sampling heads Vendor A Vendor B 10 Gbps pattern through cables, connectors, probes, 50 Ω through substrate to sampling head Inphi Proprietary / Page 18

19 Test Set Limitations! Calibrate all components 10 Gbps pattern generator connected directly to sampling head 10 Gbps pattern through cables, connectors, probes, 50 Ω through substrate Inphi Proprietary / Page 19

20 Modeling the Test Set! Correlation requires simulating the circuit with electrical models of the test set! Agilent EEsof ADS model for the test set SCOPE SCOPE Inphi Proprietary / Page 20

21 Modeling the Test Set! Electrical models for sources, probes and scope GSG Probe Data & Clock Sources Sampling Head Inphi Proprietary / Page 21

22 Sampling Head: Model vs. Measured! Correlate measured and simulated results for each component in the test set Sources, sampling head Measured (10 Gbps) Simulated (10 Gbps) Inphi Proprietary / Page 22

23 Test Set: Model vs. Measured! Good correlation between measured and simulated results of the test enables correlation of DUT Measured (2 Gbps) Simulated (2 Gbps) Inphi Proprietary / Page 23

24 Summary! Know the characteristics and limitations of your cables, connectors, and probes! Know the limitations of your equipment! Model and correlate all equipment used in time domain characterization so that you can correlate measurement and simulation of the DUT Inphi Proprietary / Page 24 June 25, 2003 Page 24

25 Jitter Measurements for 10 Gbps PMD ICs Dr. Steffen Nielsen, Principal Design Engineer Dr. Paul van der Wagt, Principal Design Engineer

26 Overview! Equipment limitations at 10 Gbps! Jitter basics Jitter spec in data sheets Jitter components Jitter and scope eyes! Measuring random jitter! Measuring deterministic jitter Shortcut Edge-by-edge method DCD Example! Summary Inphi Proprietary / Page 26

27 Equipment Limitations at 10 Gbps! Advanced jitter analysis equipment not available at present Lack of sufficiently fast real-time sampling scopes (roughly 40 Gbps would be needed)! GHz equivalent time sampling scope (DCA) readily available let s try to use that! Equipment impacts measurement accuracy use the best you have Inphi Proprietary / Page 27

28 Jitter Spec in Data Sheets! Added jitter is key parameter for PMD ICs Some spec total output jitter " Only valid if you have a jitter-free input (a clocked driver is close) Must be separated into random jitter (RJ) and deterministic jitter (DJ) components to correctly predict system margins Pattern must be stated for DJ spec Inphi Proprietary / Page 28

29 Jitter Components! Random jitter (RJ) Unbounded value, rms unit Thermal noise, shot noise! Deterministic jitter (DJ) Has a pattern-dependent probability density Bounded value, peak-to-peak unit Intersymbol interference (ISI), coupling, duty cycle distortion (DCD), supply noise! Some deterministic jitter can look random depending on the measurement technique used (e.g. DJ uncorrelated to trigger) Inphi Proprietary / Page 29

30 Jitter & Scope Eyes! Jitter is convolution of DJ and RJ components! DJ also has a probability density (though bound)! DJ often buried in a pseudo-gaussian distribution (no distinct double peaks) No double peaks does NOT mean no DJ! Inphi Proprietary / Page 30

31 Jitter & Scope Eyes (con t.)! Why DJ generally isn t the distance between the peaks DJ! DJ extends beyond peaks! Inphi Proprietary / Page 31

32 Measuring Added Jitter Using DCA PPG DUT DCA! Measure DUT output as well as input Eliminates source / setup DJ and potential DCA time base wander problem Use a low jitter input whenever possible in order to get accurate added jitter numbers Clocked DUTs: measure CLK instead of DUT input data Inphi Proprietary / Page 32

33 Added Random Jitter! 1010 pattern, trigger on either edge! Measure rms value: RJ DUT = RJ 2 OUT RJ 2 IN! Triggering on one edge prevents DCD effects Inphi Proprietary / Page 33

34 Added Deterministic Jitter! DJ transfer input # output is unknown?! Thus one cannot assume that DJ DUT = DJ OUT DJ IN Inphi Proprietary / Page 34

35 Estimating DJ! Bounds on added DJ can be found from input and output eyes alone (sum and difference are extremes)! Measure input and output DJ (eye mode, few samples to avoid outer RJ tails in result, peak-to-peak measurement) 1.7 ps 5.4 ps Above example results in 3.7 ps DJ 7.1 ps (a clean input is important here) This method does not yield the exact added DJ value! Inphi Proprietary / Page 35

36 Edge-by-Edge Method! Pattern trigger, use averaging (more is better), max horizontal resolution (e.g. Maxim app note)! Measure bit-aligned input & output simultaneously to eliminate DCA time base wander Problem: DCA accuracy with large time span Gbps, 4050 points # 3 ps resolution Inphi Proprietary / Page 36

37 Edge-by-Edge Method (con t.)! Walk through entire pattern in high time resolution mode, e.g. 2 bits span 100 fs resolution Problems Very time consuming when averaging Limits pattern length to < 1000 bits in reality Inphi Proprietary / Page 37

38 Edge-by-Edge Method (con t.)! Measure delay between all falling input / output edge pairs define fall = tpdf max tpdf min! Measure delay between all rising input / output edge pairs define rise = tpdr max tpdr min! DJ pp = max { fall, rise }! Method does not include DCD in DJ number This automatically separates DCD from correlated DJ! Uncorrelated DJ not captured Inphi Proprietary / Page 38

39 DCD Method! 1010 pattern, trigger on either edge! Averaging on (eliminates RJ & uncorrelated DJ)! Measure narrow pulse width! Calculate peak-to-peak jitter by DJ DCD, pp = 1/B PW 1 / B PW Inphi Proprietary / Page 39

40 Example: 1015EA Electro-Absorption Driver! PRBS Gbps, 4050 points! Added RJ = 240 fs rms! Added DJ outer bounds: 3.7 ps DJ 7.1 ps! Added DJ accurate measurement DJ = 5.4 ps with averaging = 16 (time 5 min) DJ = 4.6 ps with averaging = 64 (time 20 min) Inphi Proprietary / Page 40

41 Conclusions! For 10 Gbps and beyond, measuring added deterministic jitter accurately is difficult but important! High accuracy is time consuming and not well suited for production test! With a very clean input, the outer bounds of added DJ can be estimated quickly with reasonable accuracy Inphi Proprietary / Page 41

42 Frequency Domain Measurements for High-Speed PMD Integrated Circuits Dr. Carl Pobanz, Principal Design Engineer

43 Frequency Domain Measurements! Discussion will focus on network analysis for 10 & 40 Gb/s lightwave physical media dependent (PMD) ICs Data amplifiers, modulator drivers, TIAs! PMD ICs for telecom / datacom are time domain components why consider frequency domain at all? Time Domain Rise / Fall Time Jitter Overshoot Frequency Domain Amplitude Bandwidth Gain Phase Noise Return Loss Group Delay Inphi Proprietary / Page 43

44 Frequency Domain Network Analysis! Vector network analyzers (VNAs)! Truly calibrated in-situ measurements at high frequencies (> 1 GHz) Remove all effects of attenuation, dispersion, reflections in cables and test fixtures. Can define and translate reference planes. Very difficult to do in time domain no commercial instrumentation available (prototype: Agilent LSNA Large Signal Network Analyzer 1 )! Impedances are naturally handled in freq domain (e.g. Smith chart)! Limitations for PMD ICs Assumes linear time-invariant circuits under small-signal excitation " Digital circuits, limiting / switching drivers are neither... Mapping measured parameters to time domain is often non trivial " Bandwidth # rise time, group delay # deterministic jitter, etc. " Not always a useful exercise Inphi Proprietary / Page 44 1 J. Scott, et al., 2002 IEEE MTT Symposium

45 Network Analysis: Differential Circuits! Differential PMD integrated circuits 16 mixed mode S-parameters, complete analysis requires 4-port VNA Balanced DUT may be measured one mode at a time with 2-port VNA " Requires 180 hybrid balun " Band limited frequency range typically 3 octaves max " Must fabricate calibration standards can use TRL " Mode conversion is not allowed, symmetry is critical DUT Common / Even Mode (Σ) Differential / Odd Mode ( ) Inphi Proprietary / Page 45

46 Differential PMD Circuits (con t.)! Transmission Symmetric differential ICs # high common mode rejection (CMR) Measure single-ended gain, add +6 db for differential output! Reflection Differential & common mode impedances with 2-port VNA technique Example: not so good CML input stage port 1 port GND Differential mode 50 Ω each side to ground Common mode 450 Ω each side to ground 2-port VNA Γ DIFF = (S 11 + S 22 ) (S 21 + S 12 ) 2 Γ CM = (S 11 + S 22 ) + (S 21 + S 12 ) 2 Inphi Proprietary / Page 46

47 Typical Spectrum of Data Signals 40 Gbps NRZ PRBS spectrum in PMD Circuits t r = 2 ps (0.1 UI) t r = 10 ps (0.4 UI) 40 GHz 80 GHz 40 GHz 80 GHz Discrete tones related to PRBS sequence length f n = n f clk / (2 m 1) or data frame rate Inphi Proprietary / Page 47 0 Hz 1.22 MHz 40 Gbps Data Lowest Tone PRBS 315 MHz PRBS 1.2 MHz SONET OC khz PRBS 18.6 Hz

48 Effect of Low Frequency Cutoff on NRZ Data 8 khz cutoff 50 khz cutoff 20 µs/div 20 µs/div! LF cutoff removes lowest discrete tones in data spectrum Causes droop on long consecutive bit runs Another view: negative tones added that upset baseline level Baseline ripple occurs at these tone frequencies! DC blocking capacitors Typically 0.1 µf in 50 Ω system, f low = 16 khz # Cutoff causes deterministic jitter, fuzz on eye rails Inphi Proprietary / Page 48

49 Modulator Drivers / Limiting Amplifiers! Two major architectures Microwave distributed / traveling wave amplifiers (TWAs) Switching drivers based on differential pair circuits! Typical VNA measurements Gain (S 21 ) " Not always measurable or useful Return loss (S 11, S 22 ) " Output impedance is time varying in switched circuits Inphi Proprietary / Page 49

50 Bandwidth vs. Rise Time in Linear Circuits Linear, first-order system with time constant τ 3 db bandwidth f o = 1 2π τ Rise time t r = τ HI % ln ( ) LO % f o t r = 1 2π HI % ln ( ) LO % Bandwidth rise time product # 350 GHz-ps (10 90%) # 220 GHz-ps (20 80%) # Relationship also holds empirically for higher-order systems with damped (monotonic) step response, typ. < 5% error for < 5% overshoot Ref: M. S. Ghausi, Principles and Design of Linear Active Circuits, Ch. 16, 1965 Inphi Proprietary / Page 50

51 Bandwidth vs. Rise Time: Quasi Linear Amplifier Example: Inphi 2010DZ Dual MZ Modulator Driver (GaAs phemt) typical on wafer 10 Gbps measured on wafer 18 GHz small-signal BW 3-dB 12 ps rise time (20 80%) Typically 3 db into compression # weakly limiting Bessel-type response / flat group delay # very low jitter Inphi Proprietary / Page 51

52 Bandwidth vs. Rise Time: Limiting Amplifier Example: Inphi 1310SZ MZ Modulator Driver (InP DHBT) S21 (db) typical on-wafer FREQUENCY (GHz) 6.5 GHz small-signal BW with < 25 ps rise time # Linear estimate 220 GHz-ps / 6.5 GHz = 34 ps!? # Operates in a fully switched, nonlinear mode Gbps measured on wafer Inphi Proprietary / Page 52

53 Bandwidth vs. Rise Time in Limiting Amplifiers Switching / limiting decreases rise time INPUT 100 mv p-p OUTPUT 1 V p-p OUTPUT RISE TIME INPUT RISE TIME Fundamentally nonlinear Effective bandwidth increased by harmonic generation # Bandwidth rise time relation falls apart Inphi Proprietary / Page 53

54 Measuring S 21 of a Limiting Amplifier = Trouble expected measured Eye diagram, jitter looks fine on an oscilloscope What s going on? Inphi Proprietary / Page 54

55 Measuring S 21 of a Limiting Amplifier! Limiting fixes b 2 amplitude, ratioed measurement fails Display tracks reciprocal of source power a 1 variation vs. frequency Strange, jagged S 21 response Usually occurs at low frequency (where source power is highest)! Measurement is bogus! Need to reduce and/or level VNA source power Then will data be meaningful? Typical VNA test set (Agilent 8510C) Unleveled source power a 1 Inphi Proprietary / Page 55

56 Bandwidth of Limiting PMD Amplifier/Driver! Small-signal S 21 can be measured on a VNA with low source power! A large-signal S 21 can be measured with VNA + source leveling Is this useful? " Large-signal swept tone is NOT representative of data signal " Random NRZ data has sinc 2 (f) type power spectral density " Data signal compresses amplifier more at low frequencies " Effective data bandwidth is greater than what VNA will measure! Rise time is the true measure of speed 25 S21 (db) small-signal input # 0.7 V p-p 10 Gbps equivalent sinc 2 (f) input # BW 3-dB = 15 GHz BW 3-dB = 20 GHz Large-signal S-parameter (LSSP) simulation of 10 Gbps driver using Agilent ADS Inphi Proprietary / Page 56 FREQUENCY (GHz)

57 Driver Output Return Loss! Output impedance is time varying with data signal! Can measure S 22 with output state 1 (V high ), 0 (V low ) or balanced Mostly in 1 or 0 state during operation, but spec sheets show balanced 0 state is typically worst case " FET / HEMT driven into triode region (output conductance ) " Bipolar / HBT driven into quasi-saturation (output capacitance ) BAL 0 1 Typical output return loss of 10 Gbps switching driver (3 states) Inphi Proprietary / Page 57

58 Conclusions! Frequency domain measurements for PMD ICs are useful even for time domain circuits! These measurements provide valuable insight into both single-ended and differential devices! Be aware of limitations with nonlinear / switching circuits Inphi Proprietary / Page 58

59 Reference Material

60 Presenter Biographies Dr. Kevin Nary, Vice President of Engineering. Dr. Kevin Nary has nearly 20 years of engineering experience with multiple corporations and organizations. Dr. Nary began his career at Westinghouse performing IC failure analysis and then joined Harris Semiconductor, where he assessed and improved Si bipolar and MOS IC reliability. During his graduate study, he designed a 26 GHz variable modulus prescaler for Hewlett Packard and a 3 GHz MESFET automatic gain control amplifier. More recently, he was President and CEO of Celerix, an IC design house, and manager of integrated circuit development at W.L. Gore and Associates. Dr. Nary holds a Ph.D. in electrical engineering from the University of California, Santa Barbara, an M.S. in applied physics from John Hopkins University, and a.b.s. in physics from the College of William and Mary. Inphi Proprietary / Page 60

61 Presenter Biographies (con t.) Dr. Steffen Nielsen, Principal Design Engineer. Dr. Nielsen has applied his extensive experience in high-speed mixed-signal analog circuit design at such companies as Ericsson, Conexant, and Vitesse. His circuit designs include 40 Gbps InP HBTs, clock and data recovery circuits and demultiplexers, limiting amplifiers, and laser drivers. Dr. Nielsen has also designed a variety of 10.7 Gbps 0.13µm CMOS circuits, including output drivers and VCOs. In 12.5 Gb/s SiGe BiCMOS, he has designed CML cell libraries, including output drivers and VCOs, limiting amplifiers, multiphase LC-VCO, and 16:1 multiplexers. Dr. Nielsen received his Ph.D. from the Technical University of Denmark, where he wrote a thesis entitled Multi-Gigabit ASIC Design focused on demonstrating 10 Gbps clock and data recovery circuits in standard silicon bipolar technology. Inphi Proprietary / Page 61

62 Presenter Biographies (con t.) Dr. Paul van der Wagt, Principal Design Engineer. Dr. van der Wagt has 15 years of experience in high-speed IC design and device modeling. At Inphi, he has developed high-speed logic ICs with clock rates up to 50 Gbps. Previously, he was a senior scientist at Rockwell Scientific, where he designed world-record bandwidth track-and-hold circuits for commercial use. From 1995 to 1998, Dr. van der Wagt designed and fabricated quantum device circuits for ultra high speed analog-to-digital converters and low-power memory at Texas Instruments Central Research Labs. He holds 12 patents, has authored or coauthored more than 30 papers, and is a senior member of the IEEE. Dr. van der Wagt holds M.S. and Ph.D. degrees in Applied Physics from Stanford University in addition to two M.S. degrees from Twente University, The Netherlands. Inphi Proprietary / Page 62

63 Presenter Biographies (con t.) Dr. Carl Pobanz, Principal Design Engineer. Dr. Pobanz is an authority in high-frequency integrated circuit design. At Inphi, he has designed broadband driver ICs for 10 and 40 Gbps optical systems. Throughout his career, Dr. Pobanz has developed HEMT low-noise amplifiers for Ka-band space applications, InP-based LNAs, multipliers, mixers, and power amplifier MMICs for GHz systems. Published designs include millimeter-wave IC amplifiers with record high frequency and low noise performance. Dr. Pobanz came to Inphi from Broadcom, where he contributed to the design of 10 Gbps Ethernet SERDES and satellite TV tuner integrated circuits in CMOS. Dr. Pobanz received his B.S., M.S., and Ph.D in electrical engineering from the University of California, Los Angeles. Inphi Proprietary / Page 63