Maintenance/ Discontinued

Transcription

1 CCD Linear Image Seor MN Bit High-Respoivity CCD Linear Image Seor Overview The MN3646 is a 88-pixel high seitivity CCD linear image seor combining photo-sites using low dark output floating photodiodes and CCD analog shift registers for read out. It provides large output at a high S/N ratio for visible light inputs over a wide range of wavelength. Features 88 floating photodiodes and n-channel buried type CCD shift registers for read out are integrated in a single chip. Operates on +5 single power supply and can driven by 5 CM logic. Use of photodiodes with a new structure has made the dark output voltage very low. Has a smooth spectral respoe that is close to the seitivity of the human eye in the entire visible region. Large signal output of typically m at saturation can be obtained. Since a compeation output pin () is provided in addition to the signal output pin (), it is possible to obtain a signal with a high S/N ratio by carrying out differential amplification of the and outputs. Block Diagram SSA DD OD RD 9 RD power supply voltage rise circuit SG SSD C B B B3 B B3 D D D Pin Assignments D4 D5 D (Top iew) WDIP-G-47 3 DD OD RD SSA Application Barcode readers Measurement of position and dimeio of objects. includes following four Product lifecycle stage. Reset pulse voltage rise circuit B to B3 : Black reference pixels D to D 6 : Dummy invalid pixels SSD SG

2 MN3646 CCD Linear Image Seor Absolute Maximum Ratings (Ta=5 C, SSA=SSD=) Parameter Symbol Rating Unit Power supply voltage DD.3 to +8. OD.3 to +8. Input pin voltage Output pin voltage Operating temperature range Storage temperature range I O Topr Tstg.3 to to +8. to to + C C Operating Conditio oltage conditio (Ta= to +6 C, SSA=SSD=) Internal digital circuit power supply voltage DD 5. DD=OD CCD output circuit power supply voltage OD 5. CCD shift register clock High level CCD shift register clock Low level Shift gate clock High level Shift gate clock Low level Reset gate clock High level Reset gate clock Low level Boot gate clock High level Boot gate clock Low level H L SH SL RH RL BH BL Timing conditio (Ta= to +6 C) Shift register clock frequency f C f C =/T, f R=/T=data rate 4 5 khz Reset clock frequency fr. Note 8 5 khz Shift register clock rise time t r 6 Shift regisster clock fall time t f 6 Shift clock rise time t Sr 5 Shift clock fall time t Sf 5 Shift clock set up time t Ss Note Shift clock pulse width tsw 5 µs Shift clock hold time Reset clock rise time Reset clock fall time Reset clock set up time Reset clock pulse width Reset clock hold time Boost clock rise time t Sh trr trf trs trw trh tbr µs Boost clock fall time tbf 5 Boosst clock set up time tbs 3 Note 3 Reseet active period trbw Boost clock hold time tbh includes following four Product lifecycle stage. Note ) Since the dark output of the CCD shift register region increases and the dynamic range decreases as the shift register clock frequency fc becomes lower, use the device in the range of fc at which the required dynamic range can be obtained. Note ) Care should be taken because making the shift clock pulse width tsw smaller has the tendency to increase the lag (= the image left over from the signal scanned during the previous period). Note 3) A step will be present in the reset pulse waveform if the boost clock set up time tbs becomes too long.

3 CCD Linear Image Seor MN3646 Electrical Characteristics Clock input capacitance Shift register clock input capacitance C pf Shift gate clock input capacitance C S 5 pf f =MHz Reset gate clock input capacitance C R 5 3 pf Boost gate clock input capacitance C B 3 pf DC characteristics (Ta= to +6 C, SSA=SSD=) Digital power supply current IDD DD= OD =+5.5. ma Analog power supply current IOD f R=5kHz.5 3. ma Optical Characteristics <Ipection conditio> Ta=5 C, DD = OD =5, H = SH = RH = BH =5 (pulse), f C =5kHz, f R =5kHz, T int (accumulation time)=ms Light source: Red-color LED (Peak wavelength: 66nm±nm) Optical system: A slit with an aperture dimeio of mm mm is used at a distance of mm from the seor (equivalent to F=). Load resistance = k Ohms These specificatio apply to the 88 valid pixels excluding the dummy pixels D to D6. Respoivity R 7 5 /lx s Photo respoe non-uniformity Odd/even bit non-uniformity Saturation output voltage Saturation exposure Dark signal output voltage Dark signal output non-uniformity Shift register total trafer efficiency Output impedance Dynamic range Signal output pin DC level Compeation output pin DC level Signal and compeation output pin DC level difference PRNU O/E SAT SE DRK NU STTE ZO DR Note Note Note 3 Note 3 Dark condition, see Note 4 Dark condition, see Note 4 Note 5 Note 6 Note 6 Note % % m mlx s m m % kω m Note ) The photo respoe non-uniformity (PRNU) is defined by the following equation, where X ave is the average output voltage of the 88 valid pixels and x is the absolute value of the difference between X ave and the voltage of the maximum (or minimum) output pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. PRNU= x (%) X ave The incident light inteity shall be 5% of the standard saturation light inteity. Note ) The odd/even bit non-uniformity (O/E) is defined by the following equation, where X ave is the average output voltage of the 88 valid pixels and Xn is the output voltage of the n th pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. 879 includes following four Product lifecycle stage. O/E= Xn Xn+ n= (%) 879 X ave In other words, this is the value obtained by dividing the average of the output difference between the odd and even pixels by the average output voltage of all the valid pixels. The incident light inteity shall be 5% of the standard saturation light inteity.

4 MN3646 CCD Linear Image Seor Optical Characteristics (continued) Note 3) The Saturation output voltage ( SAT ) is defined as the output voltage at the point when the linearity of the photoelectric characteristics cannot be maintained as the incident light inteity is increased. (The light inteity of exposure at this point is called the saturation exposure.) Note 4) The dark signal output voltage ( DRK ) is defined as the average output voltage of the 88 pixels in the dark condition at Ta=5 C and T int =ms. Normally, the dark output voltage doubles for every 8 to C rise in Ta, and is proportional to T int. The dark signal output non-uniformity (NU) is defined as the difference between the maximum output voltage among all the valid pixels and DRK in the dark condition at Ta=5 C and T int =ms. DRK NU Note 5) The dynamic range is defined by the following equation. Since the dark signal voltage is proportional to the accumulation time, the dynamic range becomes wider when the accumulation time is shorter. Note 6) The signal output pin DC level ( ) and the compeation output pin DC level ( ) are the voltage values shown in the following figure. SS DR= Pin Descriptio SAT DRK Reset feed through level SS Pin No. Symbol Pin name Condition SSD Signal output Compeation output Digital ground Reset clock Boost clock Ground pin for the internal digital circuit. 9 SG Trafer clock (Phase ) Shift clock 3 Trafer clock (Phase ) RD Reset drain Apply capacitance of 3,3pF externally. OD DD Analog power supply Digital power supply Analog ground Ground pin for the internal analog circuit. SSA Note ) It is possible to expect improvement in the S/N ratio by connecting separately the analog power supply pi (OD, SSA) and the digital power supply pi (DD, SSD) respectively to the analog side pattern and the digital side pattern on the circuit board for driving the CCD. Note ) Connect all pi externally to SSA. includes following four Product lifecycle stage.

5 CCD Linear Image Seor MN3646 Cotruction of the Image Seor The MN3646 can be made up of the three sectio ofa) photo detector region, b) CCD trafer region (shift register), and c) output region. a) Photo detector region The photoelectric conversion device coists of a 7µm floating photodiode and a 3µm channel stopper for each pixel, and 88 of these devices are linearly arranged side by side at a pitch of µm. The photo detector's windows are µm µm rectangle and light incident on areas other than these windows is optically shut out. The photo detector is provided with 3 optically shielded pixels (black reference pixels) which serve as the black reference. b) CCD Trafer region (shift register) The light output that has been photoelectrically converted is Timing Diagram () I/O timing SG Blank feed (for 6 pixels) Integration Time (Tint.) B B B B B D D D D 4 D 5 D 6 Black reference pixel signal (for 3 pixels) alid pixel signal (for 88 pixels) Invalid pixel signal (for 3 pixels) traferred to the CCD trafer for each odd and even pixel at the timing of the shift clock ( SG ). The optical signal electric charge traferred to this analog shift register is successively traferred out and guided to the output region. A buried type CCD that can be driven by a two phase clock (, ) is used for the analog shift register. c) Output region The signal charge that is traferred to the output region is sent to the detector where impedance traformation is done using two source follower stages. The DC level component and the clock noise component not containing optical signals are output from the pin. By carrying out differential amplification of the two outputs and externally, it is possible to obtain an output signal with a high S/N ratio by reducing the clock noise, etc Invalid pixel signal (for 3 pixels) Note) Repeat the trafer pulses ( ) for more than 46 periods. includes following four Product lifecycle stage.

6 MN3646 CCD Linear Image Seor () Drive timing Signal output voltage (m) 3 t Sr t Sf 9% t Cr t Cf SG t Ss t SW t Sh Graphs and Characteristics 4 Characteristics under standard operating condition Light source: Red LED 3 Exposure (lx s) 9% % 9% 9% Relative respoivity (%) t Rr t Rs % t t Rw trf % 9% % t Bs t Bh 9% T 9% % t Bf t Rh t RBw t Br Signal output voltage Reference level Photoelectric Conversion Characteristics Spectral Respoe Characteristics Under standard operating condition Wavelength (nm) includes following four Product lifecycle stage.

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