High-Speed Digital Interface 4.0 (PCIe, SAS) Insight and Test Solutions. Francis Liu Senior Project Manager Keysight Technologies

Transcription

1 High-Speed Digital Interface 4.0 (PCIe, SAS) Insight and Test Solutions Francis Liu Senior Project Manager Keysight Technologies Page 1

2 Agenda PCIe 4.0 Ecosystem and Timeline PCIe 4.0 TX Testing and Tools RX Testing and Link/EQ PCIe Gen5 Keysight 2018 Page 2

3 PCIe Ecosystem PCISIG Board of Directors Intel, AMD, IBM, Synopsys, Qualcomm, Dell, HP, NVIDIA, Lenovo Electrical Work Group Protocol Work Group Card Electromechanic al Work Group Serial Enabling Work Group Deliverables: Group Chairs: Electrical Spec AMD, Intel Protocol Spec AMD, Intel CEM Spec Intel Test Specification & Plugfests Intel, Synopsys PCI Express 4.0 Keysight 2018 Page 3

4 PCI Express Specifications and Scope Select the specifications that relate to your need Base Specification Contains all the system knowledge Can directly be applied to Chip Test Card Electromechanical (CEM) Spec Applies to Add-In Cards and Mother Boards Mitigates card manufacturer s need to study the base specification Increases reproducibility through PCI-SIG supplied test tools CBB and CLB (compliance base and load board) Phy Test Specification Defines compliance tests of CEM spec in detail Keysight 2018 Page 4

5 PCIe 4.0 New Features Based on PCIe v0.7 BASE specification New data rate:16gt/s Requires an output stages capable of providing pre-shoot and de-emphasis with fast enough risetimes. Link Equalization protocol similar to PCIe 3.0 TxEQ P0-P10 RxEQ CTLE (2 pole 1 zero) + 2tap DFE Max Channel Length 8GHz & 1 connector Re-timers used for longer channels or for channels with >1 connector RX clocking architectures: CC and IR CC -> Common RefClock -> synchronous RX and TX w/ or w/o SSC IR -> Independent RefClock -> asynchronous RX and TX w/ or w/o SSC Initial LinkEQ speed selection: 2.5GT/s -> 8GT/s with link equalization if successful -> Then transitions to 16GT/s with another round of link equalization TX Jitter Analysis: Similar to PCIe 3.0 Lane Margining added. Keysight 2018 Page 5

6 PCI Express 4.0 Keysight Total Solution Physical layer interconnect design Physical layertransmitter test Physical layerreceiver test ADS design software V-Series, Z-Series Real-Time Oscilloscopes M8020A J-BERT High Perfformance, Protocol Aware BERT 86100D DCA-X/TDR N5393F PCI Express 4.0 TX Electrical compliance software N5990A automated compliance and device characterization test software E5071C ENA option TDR 86100CU-400 PLL and Jitter Spectrum Measurement SW Verify PCIe 4.0 Compliant Channels Verify Return Loss Compliance DSA V-series & Z-Series Real-Time Oscilloscopes Automated RX Test software - Accurate, Efficient - Comprehensive RX Testing Keysight 2018 Page 6

7 CEM 4.0 and Compliance Testing CEM 4.0 currently at v0.7. V0.7 (Latest doc Oct 2, 2017) PCIe 4.0 Compliance Requirements CEM Spec completion at v0.7 (v0.9 optimal) Completion of Test Specifications Config Test Spec Link Transaction Test Spec System Firmware (BIOS) Test Spec Electrical Test Spec Retimer Test Spec Availability of Gen4 Compliance Test Fixtures for Purchase Preliminary PCIe 4.0 Test Fixtures tested at April & Aug 2017 Workshops Estimated Schedule First Gen4 FYI testing commenced April 2017 Official FYI Testing to begin in 2018 Official Integrators list to follow. Keysight 2018 Page 7

8 PCIe 4.0 v0.9 Finalizes TX Scope Bandwidth Requirement Gen4 De-embed limit Gen4 Scope BW limit Keysight 2018 Page 8

9 PCI Express 4.0 TX Measurement Basic Test Setup BASE Spec (v0.7) Keysight Z-Series Real Time Oscilloscope PCIe 4.0 ASIC/IC Custom Breakout Board S-Parameters of Replica Ch. Used to de-embed to pin or Ref CTLE can be used (12dB). Keysight 2018 Page 9

10 N5393F/G New Features Supports PCIe 4.0 BASE TX Testing at 2.5G, 5G, 8G and 16GT/s (v0.7 BASE) Supports PCIe 4.0 Reference Clock tests (2.5G, 5G, 8G, 16G) Supports U.2 (SFF-8639) CEM tests for endpoints and root complexes (2.5G, 5G, 8G). Automated DUT control using an 81150/60A Pulse Generator ARB. Enhanced Switch Matrix supporting arbitrary lane mapping New Workshop Compliance Mode for rapid PCISIG official compliance testing. Keysight 2018 Page 10

11 Keysight PCIe 4.0 (Gen4) TX N5393F Test Application New Test Plan Setup Select Speeds of Gen4 Device to Test Select Standard Version to Test Automatic DUT control for toggle signal Keysight 2018 Page 11

12 Keysight PCIe 4.0 (Gen4) TX N5393F Test Application Select a complete Gen4 TX test plan. Keysight 2018 Page 12

13 Keysight PCIe 4.0 (Gen4) TX N5393F Test Application Use InfiniiSim for de-embedding with optional N5465A Select InfiniiSim under Tools Choose your de-embed transfer function Fine-tune your de-embed filter (bandwidth, etc) Keysight 2018 Page 13

14 Keysight PCIe 4.0 (Gen4) TX N5393F Test Application For use with PCIe 3.0 and below. Use and 81150A or 81160A to Generate the CBB Compliance Toggle signal to toggle your DUT between the different compliance states. Control DUT automatically to switch compliance toggle modes Workshop compliance mode is used for PCISIG compliance testing and uses Sigtest to test your DUT as well as to create PCISIG Compliance test reports. You specify what directory to use for your Workshop Compliance Mode (Sigtest generated) HTML reports along with data files Keysight 2018 Page 14

15 Transmitter Test at 16 GT/s Implications for testing 2.5GT/s -3.5dB 5GT/s -3.5dB -6 db 8GT/s De-emphasis Presets P0-P10 (11) De-emphasis, preshoot, boost for each preset Signal Quality for at least 1 preset must pass 16 GT/s De-emphasis Presets P0-P10 (11) De-emphasis, preshoot, boost for each preset Signal Quality for at least 1 preset must pass X16 lanes (592 test cases possible) Keysight 2018 Page 15

16 Keysight PCIe 4.0 (Gen4) TX N5393F Test Application Connection Options Choose from available switch matrix options for multi-lane testing If you don t have a switch, you can test using all four scope channels to test two lanes with one setup. Select Lanes to map to your switch network setup Lanes to test can be chosen arbitrarily. Keysight 2018 Page 16

17 Keysight PCIe 4.0 (Gen4) TX N5393F Test Application Test Automation and Connection Example 81150A used for DUT control (toggle pulse to switch compliance states) Scope configured for Root Complex Testing Root Complex DUT being tested for PCISIG Compliance Keysight U3020A Switch Matrix Keysight 2018 Page 17

18 CEM TX Test Setups AIC and Motherboard Test Proposals Add-in Card TX Test Motherboard TX Test Note: This TX test proposal utilizes an external variable ISI board to ensure consistent insertion loss of the test setup. Keysight 2018 Page 18

19 CEM TX Test Setups Scope BW is set to 25GHz for CEM compliance Scope BW is set to 25GHz for CEM compliance Cabling from CBB4 to ISI Channel Keysight 2018 Page 19

20 CEM TX Test Setups CBB4 Fixture Toggle Button Toggle Circuit Output TX Output for DUT RX Lanes Keysight 2018 Page 20

21 CEM TX Test Setups CLB4 x4-x8 Fixture Toggle Button TX Output for X8 Toggle Circuit TX Output for X4 Keysight 2018 Page 21

22 CEM TX Test Setups ISI Fixture ISI Pairs Keysight 2018 Page 22

23 CEM TX Test Setups AIC and Motherboard Test Channels Serial # Configuration Full Channel Description System Tx AIC Tx System Tx AIC Tx System Tx AIC Tx System DUT -> CLB Tx -> SMP Cable -> ISI Pair 0 -> SMP/SMA Adaptor -> SMA Cable AIC DUT -> CBB Tx -> SMP Cable -> ISI Pair 16 -> SMP/SMA Adaptor -> SMA Cable System DUT -> CLB Tx -> SMP Cable -> ISI Pair 0 -> SMP/SMA Adaptor -> SMA Cable AIC DUT -> CBB Tx -> SMP Cable -> ISI Pair 16 -> SMP/SMA Adaptor -> SMA Cable System DUT -> CLB Tx -> SMP Cable -> ISI Pair 0 -> SMP/SMA Adaptor -> SMA Cable AIC DUT -> CBB Tx -> SMP Cable -> ISI Pair 16 -> SMP/SMA Adaptor -> SMA Cable Keysight 2018 Page 23

24 CEM TX Test Setups AIC and Motherboard Test Channels Loss Calculation Serial # of CEM Kit Short Trace Long Trace Loss/inch SMA Female to SMP Female Cable Coaxial Launch 2x CBB Tx <-> CLB Rx Mated CEM Connector Loss CBB Tx Loss CLB Tx Loss AIC Tx CBB ISI (Desired) CBB ISI (Measured) CBB ISI Pair Pair 16 Pair 16 Pair 16 System Tx CLB ISI (Desired) CLB ISI (Measured) CLB ISI Pair Pair 0 Pair 0 Pair 0 Keysight 2018 Page 24

25 CEM AIC TX Test Setup DUT Cabling from CBB4 to ISI Channel Compliance Toggle Physical ISI Chanel to achieve -17dB Keysight 2018 Page 25

26 Receiver Testing at16gbps >16Gbps BERT Link Equalization Jitter and De-emphasis PCIe GT/s RX Testing Page 26

27 Blub AIC Test System Test EQ starts EQ complete Dynamic Link Equalization Handshake 8G The four phases of the Link Equalization Protocol RcvrLock Phase 0 Phase 1 Phase 2 UPSTREAM PORT Add-In Card J-BERT M8020A TS1, [P2] EC = 00b, PV = P2 TS1, [P2] EC = 01b, PV = P2, Use_Preset = 0 TS1, [P2] EC = 10b, PV = P3, Use_Preset = 1 TS1, [P2] EC = 10b, PV = P4, Use_Preset = 1 BER < Phase 3 TS1, [P2] EC = 11b, PV = P2, Use_Preset = 0 TS1, [P6] EC = 11b, PV = P6, Use_Preset = 0 TS1, [P7] EC = 11b, PV = P7, Use_Preset = 0 RcvrLock TS1, [P7] EC = 00b, PV = P7 EQTS2 PV = P1 DOWNSTREAM PORT J-BERT M8020A System TS1, [P1] EC = 01b, PV = P1, Use_Preset = 0 TS1, [P1] EC = 10b, PV = P1, Use_Preset = 0 TS1, [P3] EC = 10b, PV = P3, Use_Preset = 0 TS1, [P4] EC = 10b, PV = P4, Use_Preset = 0 TS1, [P4] EC = 11b, PV = P6, Use_Preset = 1 TS1, [P4] EC = 11b, PV = P7, Use_Preset = 1 TS1, [P4] EC = 00b, PV = P4, Use_Preset = 0 RcvrLock Phase 1 Phase 2 Phase 3 BER < RcvrLock PV EC Phase 0: 2.5 Gb/s Downstream port tells upstream port which initial preset to use after the speed change will have been done. Phase 1: 8 Gb/s Link partners settle on 8 GT/s speed. Exchange FS/LF values. Phase 2: 8 Gb/s Add-in Card sets up the deemphasis of the System Board s transmitter. Phase 3: 8 Gb/s System Board sets up the deemphasis of the Add-in Card s transmitter. Preset Value Equalization Control Keysight 2018 Page 27

28 Blub AIC Test System Test EQ starts EQ complete Dynamic Link Equalization Handshake 16G The four phases of the Link Equalization Protocol RcvrLock Phase 0 Phase 1 Phase 2 UPSTREAM PORT Add-In Card J-BERT M8020A TS1, [P2] EC = 00b, PV = P2 TS1, [P2] EC = 01b, PV = P2, Use_Preset = 0 TS1, [P2] EC = 10b, PV = P3, Use_Preset = 1 TS1, [P2] EC = 10b, PV = P4, Use_Preset = 1 BER < Phase 3 TS1, [P2] EC = 11b, PV = P2, Use_Preset = 0 TS1, [P6] EC = 11b, PV = P6, Use_Preset = 0 TS1, [P7] EC = 11b, PV = P7, Use_Preset = 0 RcvrLock TS1, [P7] EC = 00b, PV = P7 EQTS2 PV = P1 DOWNSTREAM PORT J-BERT M8020A System TS1, [P1] EC = 01b, PV = P1, Use_Preset = 0 TS1, [P1] EC = 10b, PV = P1, Use_Preset = 0 TS1, [P3] EC = 10b, PV = P3, Use_Preset = 0 TS1, [P4] EC = 10b, PV = P4, Use_Preset = 0 TS1, [P4] EC = 11b, PV = P6, Use_Preset = 1 TS1, [P4] EC = 11b, PV = P7, Use_Preset = 1 TS1, [P4] EC = 00b, PV = P4, Use_Preset = 0 RcvrLock Phase 1 Phase 2 Phase 3 BER < RcvrLock PV EC Phase 0: 2.5 Gb/s Downstream port tells upstream port which initial preset to use after the speed change will have been done. Phase 1: 8 Gb/s Link partners settle on 8 GT/s speed. Exchange FS/LF values. Phase 2: 8 Gb/s Add-in Card sets up the deemphasis of the System Board s transmitter. Phase 3: 8 Gb/s System Board sets up the deemphasis of the Add-in Card s transmitter. Preset Value Equalization Control IF SUCCESSFUL Phase 1: 16 Gb/s Link partners settle on 16 GT/s speed. Exchange FS/LF values. Phase 2: 16 Gb/s Add-in Card sets up the deemphasis of the System Board s transmitter. Phase 3: 16 Gb/s System Board sets up the deemphasis of the Add-in Card s transmitter. Keysight 2018 Page 28

29 J-BERT M8020A Setup PCIe 4.0 LTSSM Log Example for End Point Change Requests to BERT BERT Tx Equalization Accept Speed Preset PreCursor MainCursor PostCursor FullSwing LowFrequency True Gen3 P True Gen3 P True Gen3 P True Gen3 P True Gen3 P True Gen3 P True Gen3 P True Gen3 P True Gen3 P True Gen3 P True Gen3 P False Gen True Gen3 P True Gen3 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P True Gen4 P False Gen True Gen4 P PCIe GT/s RX Testing Page 29

30 J-BERT M8020A Setup PCIe 4.0 Data Output - Data Output with integrated de-emphasis - Pre-defined preset registers allow easy and quick switching between presets - Pre-shoot and de-emphasis values can be changed by user allowing compensation and calibration at connection point PCIe GT/s RX Testing Page 30

31 J-BERT M8020A Setup PCIe 4.0 Data Output Internally Generated ISI (optional on M8020A) PCIe GT/s RX Testing Page 31

32 J-BERT M8020A Setup PCIe 4.0 Impairments - LF-PJ & HF-PJ1 for jitter tolerance measurement - rssc for CC RX testing - Internally generated ISI, HF-PJ2 and DM-SI for RX eye calibration - RJ and CM-SI are fixed impairments PCIe GT/s RX Testing Page 32

33 J-BERT M8020A Setup PCIe 4.0 RX Test Setup - Data input with integrated CDR and CTLE PCIe 16Gb/s and USB 10Gb/s settings available for M8041A with SN >= DE or >= MY PCIe GT/s RX Testing Page 33

34 PCIe 4.0 RX Tests Test Automation Support for CC as well as IR End point as well as root complex 2.5 GT/s, 5 GT/s, 8 GT/s and 16 GT/s PCIe 4.0 support for the N5990A products is planned for Jan PCIe GT/s RX Testing Page 34

35 PCIe GT/s CEM Test Setup Calibration Setup for 16 GT/s RX - CBB 4.0 as well as CLB 4.0 need to be combined with ISI trace boards - CEM calibration procedure is very similar to base spec calibration but SIGTEST instead of SEASIM is mandatory - J-BERT M8020A successfully tested most of the 16 GT/s AICs and systems at PCIe WS Many AICs and systems could be trained to loopback using the new LTSSM PCIe GT/s RX Testing Page 35

36 CEM RX Test Setups AIC and Motherboard Test Channels Serial # Configuration Full Channel Description System (27dB Channel BERT -> SMA Cable -> SMA/SMP Adaptor -> ISI Pair 0 -> SMP Cable -> CLB Rx Lane 0 -> CBB Tx Lane 0 -> SMP Cable -> ISI Pair 16 -> SMP/SMA Adaptor -> SMA Cable -> Scope (5dB embed 10 System (28dB Channel BERT -> SMA Cable -> SMA/SMP Adaptor -> ISI Pair 3 -> SMP Cable -> CLB Rx Lane 0 -> CBB Tx Lane 0 -> SMP Cable -> ISI Pair 16 -> SMP/SMA Adaptor -> SMA Cable -> Scope (5dB embed System (30dB Channel BERT -> SMA Cable -> SMA/SMP Adaptor -> ISI Pair 7 -> SMP Cable -> CLB Rx Lane 0 -> CBB Tx Lane 0 -> SMP Cable -> ISI Pair 16 -> SMP/SMA Adaptor -> SMA Cable -> Scope (5dB embed 10 AIC (27dB Channel) AIC (28dB Channel) AIC (30dB Channel) BERT -> SMA Cable -> SMA/SMP Adaptor -> ISI Pair 25 -> SMP Cable -> CBB Rx Lane 0 -> CLB Tx Lane 0 -> SMP Cable -> ISI Pair 0 -> SMP/SMA Adaptor -> SMA Cable -> Scope (3dB embedding) BERT -> SMA Cable -> SMA/SMP Adaptor -> ISI Pair 27 -> SMP Cable -> CBB Rx Lane 0 -> CLB Tx Lane 0 -> SMP Cable -> ISI Pair 0 -> SMP/SMA Adaptor -> SMA Cable -> Scope (3dB embedding) BERT -> SMA Cable -> SMA/SMP Adaptor -> ISI Pair 31 -> SMP Cable -> CBB Rx Lane 0 -> CLB Tx Lane 0 -> SMP Cable -> ISI Pair 0 -> SMP/SMA Adaptor -> SMA Cable -> Scope (3dB embedding) Keysight 2018 Page 36

37 CEM RX Test Setups AIC and Motherboard Test Channels Loss Calculation Serial # of CEM Kit Short Trace Long Trace Loss/inch SMA Female to SMP Female Cabl Coaxial Launch 2x CBB Tx <-> CLB Rx Mated CEM Connector Loss CBB Tx Loss CLB Tx Loss System Rx CAL CBB ISI (Desired) CBB ISI (Measured) CBB ISI Pair Pair 16 Pair 15 Pair 16 27dB (Measured) dB CLB ISI Pair Pair 0 Pair 0 Pair 0 28dB (Measured) dB CLB ISI Pair Pair 3 Pair 3 Pair 2 30dB (Measured) dB CLB ISI Pair Pair 7 Pair 7 Pair 6 AIC Rx CAL CLB ISI (Desired) CLB ISI (Measured) CLB ISI Pair Pair 0 Pair 0 Pair 0 27dB (Measured) dB CLB ISI Pair Pair 25 Pair 24 Pair 25 28dB (Measured) dB CLB ISI Pair Pair 27 Pair 26 Pair 27 30dB (Measured) dB CLB ISI Pair Pair 31 Pair 30 Pair 31 Keysight 2018 Page 37

38 PCIe 4.0 RX Stress Signal Calibration 16 GT/s Receiver Stress Signal Calibration Setup 1 N5990A Test Automation SW for PCIe V diff, pre-shoot and de-emphasis calibration RJ calibration SJ calibration PCIe GT/s RX Testing Page 38

39 39 PCIe 4.0 RX Stress Signal Calibration 16 GT/s Receiver Stress Signal Calibration Setup 2 N5990A Test Automation SW for PCIe PCIe Base Specification 4.0 requires a CEM connector to part of the test channel! to Real Time Scope for calibration PCIe 4.0 Base Spec requires a CEM connector to be part of the test channel Channel calibration with preset selection to get as close to target eye height and eye width as possible. J-BERT M8020A s internal ISI can be used to calibrate channel. Preset is selected on optimal RX eye area DM-SI and CM-SI are calibrated through the channel Compliance eye calibration is done by adjusting DM-SI, SJ or V diff If SJ was changed from 100 mui during the compliance eye calibration, the SJ portion >100 mui is applied as a secondary SJ 210 MHz during the RX test. This allows to follow the jitter tolerance compliance curve PCIe GT/s RX Testing Page 39

40 Workshop 104 Gen4 RX Testing Suite Keysight 2018 Page 40

41 PCIe 4.0 RX Stress Signal Calibration Compliance Eye Calibration Channel determined by the channel calibration is applied DM-SI, SJ and V diff are adjusted to find correct combination for a compliant eye of the reference RX PCIe GT/s RX Testing Page 41

42 PCIe Gen5 Preliminary Goals Signaling rate: 32GT/s NRZ (no PAM4) Channel loss target is: 16GHz (Nyquist) BER target is 10e-12 TX Presets P0-P10 to remain the same Backward compatibility with previous PCIe Gen1/2/3/4 Same approach for TX and RX testing used for Gen4 Similar method for TX testing via de-embedding of breakout board traces Similar method for calibrating the eye width and eye height as used with PCIe 4.0 (ISI based, fixed RJ) Same TX Voltage parameters as Gen4 Keysight 2018 Page 42

43 Conclusions 1. Gen4 v1.0 is released (BASE) 2. Official statement on scope BW required for TX and RX calibration is in the v0.9 spec. The official requirement is a minimum scope bandwidth of 25GHz due to the need to match edge BW of JBERT during calibration. This also is required for TX testing. 3. PCIe 4.0 to include lane margining. 4. Receiver Calibration Channel is to have a CEM connector EIEOS changes to 16 1 s and 16 0 s at v PCIe 4.0 informal FYI testing (CEM) began with the August 2017 workshops in Milpitas. 6. Tools for full PCIe 4.0 TX and RX BASE testing are available today. Keysight 2018 Page 43

44 Addressing New Serial Attached SCSI 4 (SAS-4) Transmitter and Receiver Test Challenges Thorsten Goetzelmann RX Test Marketing Engineer Min-Jie Chong Product Manager and Planner Page 44

45 Agenda SAS-4 Updates and Roadmap Probing and Test Fixtures Transmitter Test Solution Receiver Test Solution Summary Keysight SAS4 TX and RX Solutions Page 45

46 Latest SAS Technology Roadmap Source: 1 st plugfest 2 nd plugfest Notes: This roadmap shows the availability of prototypes and end-user products for each generation of SAS Schedule for 24Gb/s SAS is based on an understanding of the status of the SAS-4 standard and a general knowledge of industry product development Plugfest is an event where industry participants test their prototype products to confirm interoperability First 24Gb/s SAS Plugfest is expected to occur about mid-2018 End-user products typically become available approximately months after the first Plugfest 24Gb/s SAS end-user products are anticipated mid-2019 to early 2020 Keysight SAS4 TX and RX Solutions Page 46

47 SAS-4 Specification SAS 24G Specifications 22.5 Gb/s (GBaud) 128b/150b coding (128b/130b + 20 FEC bits) 20 Forward Error Correction (FEC) bits - Based on reduced Reed-Solomon coding, purposely designed for low latency requirement in SAS-4 Doubles effective throughput of SAS-3 12Gb/s 22.5 Gb/s specs leveraged from OIF-CEI 3.1 (CEI-25G-LR) spec, Feb Deviation from how earlier SAS standards was tested - No reference transmitter and receiver definition - No SAS EYEOPENING or WDP scripts planned - TX and RX methodology changes Keysight SAS4 TX and RX Solutions Page 47

48 Agenda Keysight Application Support Program SAS-4 Updates and Roadmap Probing and Test Fixtures Transmitter Test Solution Receiver Test Solution Summary Keysight SAS4 TX and RX Solutions Page 48

49 SAS-4 Test Fixture Requirement New recommendation for test fixture insertion loss in Annex K for 22.5 Gb/s testing. Test fixture has to meet the tolerance of the following insertion loss plot: Top limit Bottom limit Nominal Purposes: More accurately test the 22.5 Gb/s signal without the effect of the test fixtures, especially with the reduced margin. Avoid marginal designs passing using better test fixtures. Keysight SAS4 TX and RX Solutions Page 49

50 Wilder SFF-8482 Insertion Loss Device connector test fixture Wilder device fixtures have better insertion loss than the top and bottom limit of the spec recommendation. Embedding of the loss will be required to bring the insertion loss inside the top and bottom limit. Keysight SAS4 TX and RX Solutions Page 50

51 Wilder Mini-SAS HD Insertion Loss Expander or Host connector test fixture Wilder expander or host fixtures have better insertion loss than the top and bottom limit of the spec recommendation. Embedding of the loss will be required to bring the insertion loss inside the top and bottom limit. Keysight SAS4 TX and RX Solutions Page 51

52 Embedding Test Fixtures Insertion Loss to Meet Spec Add loss through embedding in oscilloscope + = Test fixture insertion loss Add loss with scope Meet spec User can embed loss using Keysight oscilloscope s Infiniisim tool to meet spec through: Applying the typical insertion loss profile of the test fixtures User can characterize test fixtures using VNA, and loading the insertion loss profile into the application for higher accuracy New SAS-4 application supports typical and custom loss embedding. Keysight SAS4 TX and RX Solutions Page 52

53 Agenda Keysight Application Support Program SAS-4 Updates and Roadmap Probing and Test Fixtures Transmitter Test Solution Receiver Test Solution Summary Keysight SAS4 TX and RX Solutions Page 53

54 Scope Bandwidth Recommendation SAS-4 spec requires the test equipment used for receiver stressed test to transmit minimum and maximum rise/fall time (20-80%) of 13.3 ps and 18.2 ps. Minimum oscilloscope bandwidth can be calculated from the minimum rise time spec. Minimum oscilloscope bandwidth = 0.4 / Minimum Rise Time (20-80%) = 0.4 / 13.3 ps = 30 GHz SAS-4 Infiniium spec recommends a minimum of 33 GHz oscilloscope bandwidth for transmitter test, a little bit higher than bandwidth equation. Connector Channels Oscilloscope Bandwidth Sample Rate Type (Max BW) Model Below are the Keysight oscilloscopes that meet the requirement: DSAZ504A 50 GHz 1.85 mm GSa/s DSAZ334A 33 GHz 3.5 mm 4 80 GSa/s DSAV334A 33 GHz 3.5 mm 2 80 GSa/s Keysight SAS4 TX and RX Solutions Page 54

55 N5412E SAS Gb/s Transmitter Application The application covers 4 sections of transmitter validation requirements: 1. SSC requirements 2. Signal quality (voltage, rise/fall time, jitter, common mode) New! 3. Coefficient requests and circuit response (TX EQ) 4. OOB signaling The new N5412E SAS-4 Transmitter Test Application will be released in September Keysight SAS4 TX and RX Solutions Page 55

56 Transmitter 22.5 Gb/s Spread Spectrum Clocking Tests Max SSC Modulation Deviation Min SSC Modulation Frequency SSC Modulation Deviation SATA SSC Down-spreading SAS SSC Down-spreading SAS SSC Center-spreading SAS 12G SSC Down-spreading SAS 12G SSC Center-spreading SAS 22.5G SSC Down-spreading SAS 22.5G SSC Center-spreading SAS 22.5G/12G SATA SSC Down-spreading SSC Modulation Frequency 30-33kHz Max: +300ppm, Min: -5300ppm Max: 0ppm, Min: -2300ppm Max: +2300, Min: -2300ppm Max: 0ppm, Min: -1000ppm Max: +1000ppm, Min: -1000ppm Max: 0ppm, Min: -500ppm Max: 500ppm, Min -500ppm Not supported SSC Delta Frequency Delta Time (Informative) SAS DFDT = [ F(t) F(t-0.27us) ] / 0.27us ( < 850ppm ) TIE filtered with 2 nd order Butterworth with 3.7 +/- 0.2MHz Keysight SAS4 TX and RX Solutions Page 56

57 Transmitter 22.5 Gb/s Amplitude Tests Test patterns D30.3 (LFTP), PRBS 15 PRBS 15 PRBS 15 Vpp max (1200 mv) is measured at connector using direct measurement Vpp min (850 mv) is measured at package using direction measurement, de-embedding or SAS_EYEOPENING* script * Keysight has modified the SAS3_EYEOPENING to support Vpp min measurement in the N5412E SAS-4 transmitter test application. Keysight SAS4 TX and RX Solutions Page 57

58 Transmitter 22.5 Gb/s Jitter Tests Test patterns PRBS 15 PRBS 9 HTFP (D10.2) PRBS 15 T_UUGJ = RJ pp (BER 1E-12, 14*RJ rms ) T_UBHPJ = Bounded Uncorrelated Jitter (BUJ) or Deterministic Jitter (DJ) minus Data Dependent Jitter (DDJ) All jitter specs are measured with no equalization (EQ) mode except T_DCD. T_DCD shall be measured with EQ and no EQ modes. T_TJ shall be measured with both SSC enabled and disabled. Keysight SAS4 TX and RX Solutions Page 58

59 TX EQ Coefficient Requests Voltage Level Requirements Resolution of the TX Equalization voltage step is vendor implementation. Requirement for each TX Equalization step to be within the voltage change requirements provided in the table. Keysight has modified the SAS3_EYEOPENING to support TX EQ measurements in the N5412E SAS-4 test application. Keysight SAS4 TX and RX Solutions Page 59

60 DFE Taps Setting and Optimization Opening the eye at receiver after DFE Manual tap setup (up to 40 taps) Automatically optimize the tap values given constraints (up to 40 taps) Keysight SAS4 TX and RX Solutions Page 60

61 DFE Results with Scope Equalization SW (N5461A) 5-tap DFE for various data rates Unequalized 3 Gb/s Unequalized 6 Gb/s Unequalized 12 Gb/s Unequalized 22.5 Gb/s Equalized 3 Gb/s Equalized 6 Gb/s Equalized 12 Gb/s Equalized 22.5 Gb/s Keysight SAS4 TX and RX Solutions Page 61

62 OOB Signaling Test Same for 1.5, 3, 6, 12 and 22.5 Gb/s OOB connection diagram Supported pattern generators: M8020A JBERT N4903B JBERT 81134A PG Test and results: Keysight SAS4 TX and RX Solutions Page 62

63 Agenda Keysight Application Support Program SAS-4 Updates and Roadmap Probing and Test Fixtures Transmitter Test Solution Receiver Test Solution Summary Keysight SAS4 TX and RX Solutions Page 63

64 SAS-3 RX Test Solution To support SAS-3 RX testing: J-BERT M8020A system with 2 pattern generators and one error detector All jitter sources, including ISI for channel loss tuning are built-in Multi-tap de-emphasis is built-in CDR as well as CTLE are built-in TxEQ negotiation for SAS-3 N5990A-105 SAS RX Calibration and Test SW N5990A-305 SAS Link Training Suite internal ISI generation in combination with fixed ISI trace allows loss tuning DUT: SAS Drive Wilder Technologies test fixture 2 nd PG is used as aggressor channel Scope is used for calibration and trouble shooting Keysight SAS4 TX and RX Solutions Page 64

65 SAS-4 RX Test Solution SAS-4 Test Setup To support SAS-4 RX testing: J-BERT M8020A system with 2 pattern generators and one error detector All jitter sources Multi-tap de-emphasis is built-in CDR as well as CTLE are built-in TxEQ negotiation for SAS-4 AWG used as common mode random interference source SAS RX Calibration and Test SW SAS Link Training Suite ISI trac e Wilder Technologies test fixture DUT Keysight SAS4 TX and RX Solutions Page 65

66 SAS-4 RX Stress Signal SAS-4 Leverages OIF-CEI-03.1 CEI-25G-LR SAS-4 leverages CEI-25G-LR specification from OIF-CEI-03.1 SAS-4 uses a combination of worst case transmitter plus worst case channel approach to define the receiver stress signal Jitter terminology is different compared to SAS-3 UUGJ Uncorrelated Unbounded Gaussian Jitter - RJ HPJ High Probability Jitter - DJ UBHPJ Uncorrelated Bounded High Probability Jitter - BUJ Bounded Uncorrelated (to data) Jitter - UBHPJ = HPJ - DDJ CBHPJ Correlated Bounded High Probability Jitter - Correlated to data also referred to as DDJ Data Dependent Jitter DCD Duty Cycle Distortion - Also referred to as even / odd jitter - DCD is part of DDJ or CBHPJ. Unlike SAS-4 CEI-25G-LR includes it in the UBHPJ budget. Keysight SAS4 TX and RX Solutions Page 66

67 SAS-4 RX Stress Signal Jitter Component to Jitter Source Mapping Jitter Component TJ HPJ CBHPJ or DDJ UBHPJ DCD ISI ABUJ PJ UUGJ M8020A Jitter Source Clk/2 ISI BUJ LF-PJ HF-PJ RJ All Jitter Sources are built into the J-BERT M8020A system Common mode noise is injected using the M8062A CM-SI injection circuit and using a M8195A AWG as common mode noise source Keysight SAS4 TX and RX Solutions Page 67

68 SAS-4 RX Stress Signal Where to find required jitter sources in M8070A GUI DCD SJ mask UUGJ TxEQ ISI Used as tuning element in combination with a fixed trace Keysight SAS4 TX and RX Solutions Page 68

69 SAS-4 RX Stress Signal Calibration Steps 1. Amplitude and TxEQ (preshoot and de-emphasis) calibration 2. RJ calibration J-BERT M8020A RJ source. DCD and SJ are not applied 3. SJ calibration DCD and RJ are not applied. J-BERT M8020A factory calibration for LF-PJ and HF-PJ sources is sufficiently accurate. 4. DCD calibration J-BERT M8020A clk/2 with applied SJ and RJ until target ber is reached 5. Common mode noise calibration Keysight SAS4 TX and RX Solutions Page 69

70 SAS-4 RX Stressed Signal Test Channel Chapter of the SAS-4 rev 09 specification includes an example with a channel budget split with 1/6 of the budget attributed to the transmitter device as well as the receiver device leaving 2/3 of the budget for passive channel. For above example the RX test channel to the SAS connection to the DUT would be 5/6 of the overall channel budget Using a combination of a fixed ISI trace plus the internal ISI emulation capabilities of the J-BERT M8020A allows for a variable test channel without the need to reconnect for Margin testing, or Testing for different channel budget allocations Keysight SAS4 TX and RX Solutions Page 70

71 SAS-4 Receiver Test RX under test trains J-BERT M8020A TX Option M8062A-0S6 SAS-3/-4 Transmitter Equalization Training enables RX under test to train J-BERT s TX as required by the SAS-4 stressed RX test procedure. Coefficient change requests are logged. DUT time outs need to be turned off for the negotiation. Keysight SAS4 TX and RX Solutions Page 71

72 SAS-4 Receiver Test Confirm BER before FEC or after FEC Decoding? SAS-4 mandates a test pattern of PRBS 2^31-1 The test pattern is not 128B/150B encoded and does not contain any FEC bits or ALIGNs Target BER is 10^-9 for the raw BER (no FEC applied) If a 128B150B encoded pattern with FEC bits would be used for testing and if the BER after FEC decoding would need to be verified the target BER would be 10^-15 which would take 10^6 times longer to confirm! it takes 1.5 days without receiving a single error to confirm a ber of 10^-15 per test point. To do a pass / fail test on a JTOL curve with 10 test frequencies would take 15 days! Keysight SAS4 TX and RX Solutions Page 72

73 SAS-3 / SAS-4 Link Training N5990A-305 SAS Link Training Suite + M80xxA-0S6 TxEQ Neg. The N5990A-305 SAS Link Training Suite assists in creating the static pattern sequence necessary to get the DUT to the beginning of the TxEQ negotiation The M8041A/51A-0S6 & M8062A- 0S6 SAS Tx EQ Negotiation option enable the J-BERT to react to the coefficient update requests from the DUT Once the coefficient training is finished the user can initiate the required DUT modes for the receiver test Keysight SAS4 TX and RX Solutions Page 73

74 SAS-3 / SAS-4 Calibration and Test Automation The N5990A-105 SAS Receiver Calibration and Test library automates guides the user through setup changes and performs the necessary receive stress signal calibration automatically Supports SAS-3 and SAS-4 N5990A-010 Test Sequencer is required Keysight SAS4 TX and RX Solutions Page 74

75 Summary 1. Keysight is a key contributor in SAS and SATA standards, and understand the test requirements. 2. New test and interoperability challenges exist at 22.5 Gb/s and speed beyond. New design techniques (backchannel, equalization) are making testing more difficult. 3. Automated N5412E SAS-4 transmitter test application and other tools such as N8833A crosstalk analysis app to debug issues. 4. Comprehensive receiver test solution with automated calibration, transmitter equalization negotiation and stressed signal generation. Keysight SAS4 TX and RX Solutions Page 75

76 SAS, PCI Express 4.0 Keysight Total Solution Physical layer interconnect design Physical layertransmitter test Physical layerreceiver test ADS design software V-Series, Z-Series Real-Time Oscilloscopes M8020A J-BERT High Perfformance, Protocol Aware BERT 86100D DCA-X/TDR N5393F PCI Express 4.0 TX Electrical compliance software N5990A automated compliance and device characterization test software E5071C ENA option TDR 86100CU-400 PLL and Jitter Spectrum Measurement SW Verify PCIe 4.0 Compliant Channels Verify Return Loss Compliance DSA V-series & Z-Series Real-Time Oscilloscopes Automated RX Test software - Accurate, Efficient - Comprehensive RX Testing Keysight 2018 Page 76