Lecture 3: Circuits & Layout

Transcription

1 Lecture 3: Circuits & Lyout Slides courtesy of eming Chen Slides sed on the initil set from vid Hrris CMOS VLSI esign

2 Outline CMOS Gte esign Pss Trnsistors CMOS Ltches & Flip-Flops Stndrd Cell Lyouts Stick igrms Reding: 1.4,

3 Complementry CMOS Complementry CMOS logic gtes nmos pull-down network pmos pull-up network.k.. sttic CMOS inputs pmos pull-up network output Pull-up OFF Pull-down OFF Z (flot) 1 Pull-up ON nmos pull-down network Pull-down ON 0 X (crowr) 3

4 Series nd Prllel nmos: 1 = ON pmos: 0 = ON g1 g Series: oth must e ON Prllel: either cn e ON () g1 g2 OFF OFF OFF ON () ON OFF OFF OFF g1 g (c) OFF ON ON ON g1 g (d) ON ON ON OFF 4

5 Conduction Complement Complementry CMOS gtes lwys produce 0 or 1 Ex: NN gte Series nmos: =0 when oth inputs re 1 Thus =1 when either input is 0 Requires prllel pmos Rule of Conduction Complements B Pull-up network is complement of pull-down Prllel -> series, series -> prllel 5

6 CMOS Gte esign ctivity: Sketch 4-input CMOS NOR gte B C 6

7 Compound Gtes Compound gtes cn do ny inverting function Ex: B C (N-N-OR-INVERT, OI22) C C B B () () (c) B C (d) C B C B B C B C (f) (e) 7

8 B C Exmple: O3I B C B C 8

9 Signl Strength Strength of signl How close it pproximtes idel voltge source V nd GN rils re strongest 1 nd 0 nmos pss strong 0 But degrded or wek 1 pmos pss strong 1 But degrded or wek 0 Thus nmos re est for pull-down network 9

10 Pss Trnsistors Trnsistors cn e used s switches s g d s s g = 0 g = 1 d d Input g = 1 Output 0 strong 0 g = 1 1 degrded 1 g s g = 0 d Input g = 0 Output 0 degrded 0 s d s g = 1 d 1 g = 0 strong 1 10

11 Trnsmission Gtes Pss trnsistors produce degrded outputs Trnsmission gtes pss oth 0 nd 1 well g g g = 0, g = 1 g = 1, g = 0 Input Output g = 1, g = 0 0 strong 0 g = 1, g = 0 1 strong 1 upper lower g g g g g g 11

12 Tristtes Tristte uffer produces Z when not enled EN EN 0 0 Z 0 1 Z EN EN 12

13 Nonrestoring Tristte Trnsmission gte cts s tristte uffer Only two trnsistors But nonrestoring Noise on is pssed on to EN EN 13

14 Tristte Inverter Tristte inverter produces restored output Violtes conduction complement rule Becuse we wnt Z output EN EN EN = 0 = 'Z' EN = 1 = 14

15 Multiplexers 2:1 multiplexer chooses etween two inputs S 1 0 S 0 X X X X 1 15

16 Gte-Level Mux esign S S 1 0 (too mny trnsistors) How mny trnsistors re needed? 20 1 S 0 1 S

17 Trnsmission Gte Mux Nonrestoring mux uses two trnsmission gtes Only 4 trnsistors S 0 S 1 S 17

18 Inverting Mux Inverting multiplexer Use compound OI22 Or pir of tristte inverters Essentilly the sme thing Noninverting multiplexer dds n inverter 0 S S S 1 S 0 S S 1 S S S 18

19 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristtes S1S0 S1S0 S1S0 S1S0 0 S0 S

20 Ltch When = 1, ltch is trnsprent flows through to like uffer When = 0, the ltch is opque holds its old vlue independent of.k.. trnsprent ltch or level-sensitive ltch Ltch 20

21 Ltch esign Multiplexer chooses or old

22 Ltch Opertion = 1 = 0 22

23 Flip-flop When rises, is copied to t ll other times, holds its vlue.k.. positive edge-triggered flip-flop, mster-slve flip-flop Flop 23

24 Flip-flop esign Built from mster nd slve ltches M Ltch M Ltch 24

25 Flip-flop Opertion M = 0 M = 1 25

26 Rce Condition Bck-to-ck flops cn mlfunction from clock skew Second flip-flop fires lte Sees first flip-flop chnge nd cptures its result Clled hold-time filure or rce condition Flop 1 Flop

27 Nonoverlpping Clocks Nonoverlpping clocks cn prevent rces s long s nonoverlp exceeds clock skew Industry mnges skew more crefully 2 1 M

28 Gte Lyout Lyout cn e very time consuming esign gtes to fit together nicely Build lirry of stndrd cells Stndrd cell design methodology V nd GN should ut (stndrd height) djcent gtes should stisfy design rules nmos t ottom nd pmos t top ll gtes include well nd sustrte contcts 28

29 Exmple: Inverter 29

30 Exmple: NN3 Horizontl N-diffusion nd p-diffusion strips Verticl polysilicon gtes Metl1 V ril t top Metl1 GN ril t ottom 32 l y 40 l 30

31 Stick igrms Stick digrms help pln lyout quickly Need not e to scle rw with color pencils or dry-erse mrkers V V B C metl1 c poly ndiff pdiff contct GN INV GN NN3 31

32 Wiring Trcks wiring trck is the spce required for wire 4 l width, 4 l spcing from neighor = 8 l pitch Trnsistors lso consume one wiring trck 32

33 Well spcing Wells must surround trnsistors y 6 l Implies 12 l etween opposite trnsistor flvors Leves room for one wire trck 33

34 re Estimtion Estimte re y counting wiring trcks Multiply y 8 to express in l 40 l 32 l 34

35 Exmple: O3I Sketch stick digrm for O3I nd estimte re B C V B C 6 trcks = 48 l GN 5 trcks = 40 l 35

36 Summry MOS Trnsistors re stck of gte, oxide, silicon Cn e viewed s electriclly controlled switches Build logic gtes out of switches rw msks to specify lyout of trnsistors Next lecture: simple MIPS Microprocessor Reding: ECE425 CMOS VLSI esign Slide 36