Section III: Complex system design

Transcription

1 Section III: omplex system design EG 36/56; EE 45/65 igital System esign r. Travis oom, ssociate Professor epartment of omputer Science and Engineering Wright State University ealing with omplexity ata unit (atapath) design Registers RTL language atapath onstruction ontrol unit (ontroller) design SM harts Implementation issues PLs ROM VLSI esign Outline EG 36/56 - EE 45/65 Section III - 2 ealing with omplexity Practical synchronous sequential circuits are too complex to design at the flip-flop level. simple -bit PU capable of storing only four values (in four GPRs) has at least 4 x = 32 -bit state devices! If the PU had only inputs it would still require a 2 32 by 2 truth table to represent the device. Each of these billion or so entries would have to contain a 32-bit next state. Storing bit entries would require 4 T! K (kilo) 2 24 M (mega) G (giga) x 9 T (tera) 2 4. x 2 Simplification would require a 4-variable K-map! How do we manage complex design? EG 36/56 - EE 45/65 Section III - 3

2 EG 36/56 - EE 45/65 Section III - 4 omplex System esign Practical sequential designs, like combinational designs, require a hierarchical approach Use well defined building blocks omplex blocks made of simpler blocks (hierarchy) Examples: Registers, counters ssociate a high-level of behavior with those blocks (abstraction) esign methodologies based on abstractions can more easily encompass complexity ommon function blocks: registers and counters ORER a sequence of high-level behaviors that (when executed in the proper order) solves the overall problem Like computer programming! ecomposing a esign: ontrol and ata ontrol Signals ontrol Inputs ontrol Unit Status Signals atapath ata Outputs ontrol Outputs ata Inputs omplex designs are generally broken down into to high-level abstractions. The datapath is home to one or more datapath components that provide higher-level functionality (viewable at the register transfer level) The control unit controls the sequence in which the datapath functions are performed in order to perform the system task EG 36/56 - EE 45/65 Section III - 5 ealing with omplexity ata unit (atapath) design Registers RTL language atapath onstruction ontrol unit (ontroller) design SM harts Implementation issues PLs ROM VLSI esign Outline EG 36/56 - EE 45/65 Section III - 6

3 EG 36/56 - EE 45/65 Section III - 7 atapath components Gates and flip-flops are good building blocks for simple designs We need more sophisticated building blocks for complex systems Register-transfer level (RTL) components (aka atapath components) include medium scale devices such as: Registers ounters LUs Multiplexers omparators etc 2 MSI uad/hex Registers 74LS75 / 2 / LS /3 74LS74 4 / ll four flip-flops use the same clock! 4 / EG 36/56 - EE 45/65 Section III - Octal Register with Parallel Load Enable Load /Load b-mux Why don t we gate the clock? EG 36/56 - EE 45/65 Section III - 9

4 EG 36/56 - EE 45/65 Section III - Shift Registers Multi-bit register that moves data sideways left/right ( bit/clock ) Shift Left (or Shift own) is towards MS 3 2 LSI 3 2 LSI Shift Right (or Shift Up) is towards LS 3 2 RSI 3 2 RSI Often used to rearrange bits or Multiply/ivide by 2 Modes: Hold Load Shift Right Shift Left i-directional Universal Shift Registers 74x94 9 S S 7 LIN RIN uad i-directional Universal (4-bit) PIPO Mode Next state Function S S * * * * Hold Shift right/up RIN Shift left/down LIN Load R L (SI) (LS) (MS) lock symbol > SRG n S S LSI n n (SO) RSI EG 36/56 - EE 45/65 Section III - / () () Universal SR Schematic S S 74x94 RIGHT LEFT LIN (7) SL HO (6) L SR (2) S () S RIN (9) (3) (2) (5) EG 36/56 - EE 45/65 Section III - 2

5 EG 36/56 - EE 45/65 Section III - 3 /OE Octal Tri-state Register/Latch 74LS374 OE 74LS OE 74LS Shift Register pplications State Registers Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position Very effective for finite memory machines Serial Interconnection of Systems keep interconnection cost low with serial interconnect it Serial Operations it serial operations can be performed quickly through device iteration Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power, etc). sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation EG 36/56 - EE 45/65 Section III - 4 Transmitter Shift Register pplications LOK Receiver ontrol ircuits /SYN ontrol ircuits Parallel ata from -to- converter Parallelto-serial converter ST Serial-toparallel converter Parallel ata to -to- converter IGITL TELEPHONY LOK - bit per clock tick = 2.4 MHz /SYN - synchronization of start of frame ST - serial data stream EG 36/56 - EE 45/65 Section III - 5

6 EG 36/56 - EE 45/65 Section III - 6 Shift Register pplications x7 x6 x5 x TL > Sequential Implementation of: Z[7..] = X[7..] + Y[7..] y7 y6 y5 y > LER_ V in F out S > z7 z6 z5... z ounters ounters are registers with extra functions locked sequential circuit with single-cycle state diagram Modulo-m counter = divide-by-m counter Sm S S3 S2 Most ommon: n-bit binary counter, where m = 2 n n flip-flops, counts 2 n - EG 36/56 - EE 45/65 Section III - 7 ounting ommon output codes for mod- and decimal counters State inary Gray Excess-3 Ring Twisted-tail EG 36/56 - EE 45/65 Section III -

7 EG 36/56 - EE 45/65 Section III - 9 synchronous/ripple ounter T bit divide-by-2 T T 2 2 bit divide-by-4 3 bit divide-by- Uses Minimal Logic! Tpd = n x Tpd,tff Setup = Tsetup,tff T 3 4 bit divide-by-6 Synchronous ounters ll clock inputs connected to common signal So all flip-flop outputs change simultaneously t after Synchronous ounters are/have Faster More omplex Logic (more expensive ) Most Frequently Used Type of ounter Two types of synchronous counters Serial Parallel Easy to combine iteratively to build bigger counters ombined counters have serial aspects. If the devices are parallel, then the overall device is mixed mode. EG 36/56 - EE 45/65 Section III - 2 Synchronous Serial ounter Flip-flops enabled when all lower flipflops =. Enable propagates serially limits speed Requires (n-) Δ t < T ll outputs change simultaneously t after NTEN Δ t Δ t EN >T EN >T EN >T 2 Tpd = Tpd,tff Tsetup = (n-)δt + Tsetup,tff Δ t EN 3 Equation? elay? >T EG 36/56 - EE 45/65 Section III - 2

8 EG 36/56 - EE 45/65 Section III - 22 Synchronous Parallel ounter NTEN EN >T Single-level enable logic per flip-flop Fastest and most complex type of counter Requires Δ t < T ll outputs change simultaneously t after Tpd = Tpd,tff Tsetup = Tpd,bigestN + Tsetup,Tff Equation? elay? EN >T EN >T 2 EN 3 >T bit 4 Synchronous Parallel ounter ommon lock Synchronous lear Synchronous Load ount Enable = ENP ENT Load ata Inputs (746 is the same, but with an asynchronous clear) 74X63 > L ENP ENT RO LS MS RO = Ripple arry Out, when ount = and ENT = EG 36/56 - EE 45/65 Section III State Table Inputs urrent State Next State / /L ENT ENP * * * * X X X X X X lear Load Hold Hold ount... X X X X X X X X X X X X X X X X EG 36/56 - EE 45/65 Section III - 24

9 EG 36/56 - EE 45/65 Section III Up/own ounter 74X69 UP/N = = up RO = 5 UP/N = = down RO = > UP/N L ENP ENT RO up down up Ex:,,2,,,5,4, 5,,,2 RO RO pplication - Free Running Modulo-6 ounter LOK +5 V R 74X63 > L ENP ENT RO 2 3 EG 36/56 - EE 45/65 Section III - 26 Modulo- ounter [5,6,,, 5, 5, 6,...] +5 V LOK > L ENP ENT 74X63 RO When ount=5 Load 5 () ny Modulus 2 6 possible 2 3 NT5 RO /NT5 EG 36/56 - EE 45/65 Section III - 27

10 EG 36/56 - EE 45/65 Section III - 2 Modulo- ounter [,,2,,,,,,...] +5 V LOK 74X63 > L ENP ENT RO When ount= lear ecode ount xx ( 5) ascaded 7463s for -bit ounter Up to Modulo-256 LOK /RESET /LO NTEN X63 > L ENP ENT > L ENP ENT RO 74X63 RO RO EG 36/56 - EE 45/65 Section III bit, -state Johnson ounter +5 V lso known as twisted-ringcounter Moebius counter 2n states with n flip-flops NOT self-correcting LOK /RESET R S S LIN 74X94 Wired as a shift-left shift register 2 3 RIN 74X4 EG 36/56 - EE 45/65 Section III - 3

11 EG 36/56 - EE 45/65 Section III - 3 esign ecomposition digital system is a sequential circuit with specified behavior. microprocessor is a digital system. Specifying large digital systems with state tables may be exceptionally difficult, due to the number of states involved. s in computer programming, most digital systems are designed using a modular, hierarchical approach. The system is partitioned into modular subsystems. Each subsystem performs a well defined function with specified interface. Interconnection the various subsystems though data and control signals results in a digital system. esign ecomposition Most digital systems are partitioned into two top-level modules: ata Unit (or atapath): performs data-processing operations. ontrol Unit: determines the sequence of these operations. atapaths are sequential systems. the system state is defined by the contents of the registers. the functionality is the set of defined operations that can be performed on the contents of the registers. Elementary operations are usually, but not always, performed in parallel on a string of bits in one clock tick. microoperation is an elementary operation performed on data stored in the datapath. They fall into four general categories: Transfer microoperations: transfer binary data from one register (or data input/memory) to another. rithmetic microoperations: perform arithmetic on data in registers. Logic microoperations: perform bit manipulations on data in registers. Shift microoperations: shift data in registers. EG 36/56 - EE 45/65 Section III - 32 Register-Transfer Level esign n approach to specify, analyze, and design systems too complex to use the state-table based approaches commonly utilized in simple designs. The Register-Transfer Level (RTL) approach is characterized by: digital system is viewed as divided into a data subsystem and a control subsystem. The state of the data subsystem consists of the contents of the registers. The function of the system is performed as a sequence of register transfers. register transfer is a transformation performed on the datum while the datum is transferred from one register to another. The sequence of register transfers is controlled by the control subsystem. The operation of the device can be designed as a sequence of register transfers can be designed using state diagrams, SM charts, etc. Each transfer must correspond to a sequence of microoperations. The control unit implements the RTL design through microoperations. EG 36/56 - EE 45/65 Section III - 33

12 EG 36/56 - EE 45/65 Section III - 34 RTL Languages () The notation for register transfers are sufficiently complete to describe any digital system at the register-transfer level. known as register-transfer languages. Registers are denoted by uppercase letters (sometimes followed by numbers) that indicate the function of the register e.g. R, R, R, P, MR, et al. The individual bits can be denoted using parenthesis and bit numbers or labels e.g. R(), R(7:), P(L), P(H) ata transfer is denoted in symbolic form by the means of the replacement operator. e.g. R2 R RTL Languages (2) Normally we want a given transfer to occur not for every clock pulse, but only for specific values of the control signals. RTL conditional statements: e.g. If (K = ) Then (R2 R) ontrol function notation (olon, :) e.g. K: R2 R ll RTL statements occur in response to a clock tick. comma is used to separate two or more register transfers that are executed at the same time. semi-colon is used for an instruction with different control e.g. rake: R2 R, R4 R3; not(rake): R R2 EG 36/56 - EE 45/65 Section III - 35 RTL Languages (3) Register to Memory Transfers are denoted using square brackets surrounding the memory address. e.g. R M[R] (Read operation) e.g. M[R] SR (Write operation) EG 36/56 - EE 45/65 Section III - 36

13 EG 36/56 - EE 45/65 Section III - 37 RTL Languages (4) Examples of rithmetic Microoperations Examples of Logic Microoperations esigning a datapath esign a device with two -bit inputs and, one -bit input STRT, one -bit output, and one -bit output ONE. The device begins idle (with output ONE = ). When STRT is asserted (for one clock tick) the unsigned binary inputs and are and held constant until the device asserts ONE. The device must calculate the approximate length of the hypotenuse of a right triangle with sides and. When the final answer is available on output, the device will assert ONE for one clock tick. If the answer cannot be computed, assert ERR. > STRT ONE ERR = sqrt ( ) EG 36/56 - EE 45/65 Section III - 3 esigning a datapath Euler formula for Square Root pproximation: Let x = max ( a, b ) Let y = min ( a, b ) Sqrt (a^2 + b^2) ~= max (x,(.75x+.5y)) What sort of functions do you need to process the data? EG 36/56 - EE 45/65 Section III - 39

14 EG 36/56 - EE 45/65 Section III - 4 esigning a datapath SR ircuit Model Let x = max (a, b) and y = min (a, b) Sqrt (a^2 + b^2) ~= max (x,(.75x+.5y)) ontrol unit Rx max (, ) Ry min (, ) Ry Ry >> # shift right ; *.5 Rt Rx >> 3 # shift right 3 (/ th ) Rt Rx Rt # x /x = x*.75 Rt Ry + Rt Rc max (Rx, Rt) Rc atapath Registers: c, x, y, t Functions: min, max, +, -, shift esigning a datapath ontrol unit Rx max (, ) Ry min (, ) Ry Ry >> Rt Rx >> 3 Rt Rx Rt Rt Ry + Rt Rc max (Rx, Rt) Rc RcIN RxIN RyIN RtIN RcL RG RxL RG RyL RG RtL RG > > > > Rc Rx Ry Rt MX Rx MUX Min MX2 Rt MUX Max MX Ry Rx MUX LU+- Overflow LU Rt SR,3 MXS Ry Rx MUX b-shifter MXF MUX RcIN, RxIN, RyIN, RtIN EG 36/56 - EE 45/65 Section III - 4 esigning a datapath ontrol unit Rx max (, ) Ry min (, ) Ry Ry >> Rt Rx >> 3 Rt Rx Rt Rt Ry + Rt Rc max (Rx, Rt) Rc ata Inputs ontrol Signals atapath LRx, LRy, LRt, LRc MX, MX2 MX, LU+- MXS, SR,3 Overflow ata Outputs Status Signals 2 MXF EG 36/56 - EE 45/65 Section III - 42

15 EG 36/56 - EE 45/65 Section III - 43 Outline ealing with omplexity ata unit (atapath) design Registers RTL language atapath onstruction ontrol unit (ontroller) design SM harts Implementation issues PLs ROM VLSI esign Interaction between ata and ontrol Units ontrol Signals ontrol Inputs ontrol Unit Status Signals atapath ata Outputs ontrol Outputs ata Inputs ontrol Signals - signals that activate data-processing functions. To activate a sequence of such operations, the control unit sends the proper sequence of control signals to the datapath. Status Signals - signals that describe aspects of the state of the datapath. The control unit uses these signals in determining the specific sequence of operations to be performed. Other Signals - allow the control unit and datapath to interact with other parts of the system, such as memory and input-output logic. EG 36/56 - EE 45/65 Section III - 44 The ontrol Unit The control unit generates the signals for sequencing the operations in the datapath sequential circuit with states that dictate the control signals for the system Using status conditions and control inputs, the sequential control unit determines the next state in which additional microoperations are activated. Hardwired ontrol The control unit is implemented to provide a particular digital function Microprogrammed ontrol LTER! EG 36/56 - EE 45/65 Section III - 45

16 EG 36/56 - EE 45/65 Section III - 46 ontrol Unit esign ontrol unit Next State StartOverflow = PS RTL ILE ILE ILE S S S S2 S2 S2 S2 Rx max (, ) S2 S3 S3 S3 S3 Ry min (, ) S3 S4 S4 S4 S4 Ry Ry >> S4 S5 S5 S5 S5 Rt Rx >> 3 S5 S6 S6 S6 S6 Rt Rx Rt S6 S7 ERR S7 ERR Rt Ry + Rt S7 S S S s Rc max (Rx, Rt) Start S ILE ILE ILE ILE Rc; one ERR ILE ILE ILE ILE ERR Overflow Lx one SM for ontrol ontrol unit Rx max (, ) Ry min (, ) Ry Ry >> Rt Rx >> 3 Rt Rx Rt Rt Ry + Rt Rc max (Rx, Rt) Rc; ONE Rx max (,) Ry max (,) Ry Ry >> Rt Rx >> 3... LRx, MX=, M2=, MXF= LRy, MX= M2=, MXF= LRy, MXS=, SR,3 = LRt, MXS=, SR,3 =... EG 36/56 - EE 45/65 Section III - 47 lgorithmic State Machines lgorithmic State Machine (SM) hart Special flowchart used to define digital hardware algorithms escribes a sequence of events etermines the actions which occur in the states in response to the clock pulse in response to changes in the inputs SM harts contain three basic elements: State boxes Rectangles, labeled with the state name and assignment, containing a register operation and/or the names of Moore outputs asserted in that state. ecision boxes iamonds containing a conditional input expression and exits and. onditional output boxes Ovals containing Mealy outputs asserted for the conditions leading to the box. EG 36/56 - EE 45/65 Section III - 4

17 EG 36/56 - EE 45/65 Section III - 49 SM elements State box state entry path state name state code Moore output list conditional output list state exit path onditional (Mealy) output box from decision-box exit path condition false exit path ecision box condition OR condition true exit path condition exit path SM Timing Each state box has a corresponding SM lock that includes all decision and conditional output boxes reached from that state Each SM lock has exactly one state box, all paths leaving the SM lock lead directly to a different state box. The current state box represents the current state. The current inputs decide a path through the decision boxes. Unlike state diagrams, ambiguity is easily avoided in SM charts. onditional outputs along the path occur immediately in response to changes in the inputs values. The next state box is not entered until a clock tick occurs. The Moore outputs in the state box and any conditional (Mealy) outputs in the new SM lock are asserted immediately. SM boxes may also include Register Transfer directives! ny changes (conditional or otherwise) to a sequential device wait until the next positive clock edge. EG 36/56 - EE 45/65 Section III - 5 SM Example: 4-bit binary counter STTE = STTE = Z= Z -or- Z= Z Z=2 Z,Z Z=3 EG 36/56 - EE 45/65 Section III - 5

18 EG 36/56 - EE 45/65 Section III - 52 SM Example: 4-bit counter with enable STTE = Z= Z=2 EN Z= EN Z=3 EN EN SM Example: Modulo-4 counter (Mealy) STTE = (one hot) EN EN MX Mealy output EG 36/56 - EE 45/65 Section III - 53 SM Example: s s ounter ount # of s on X & Y inputs output Z if count = multiple of 4 (, 4,... ) If ( X Y ) 2 s ( Inc by 2 ) Else if ( X+Y ) s ( Inc by ) Else s ( No Inc ) EG 36/56 - EE 45/65 Section III - 54

19 EG 36/56 - EE 45/65 Section III - 55 STTE = 2 SM chart for s s ounter S S S2 S3 Z X Y X Y X Y X Y X +Y X +Y X +Y X +Y onvert SM chart to Transition List Needs an extra step to find transition expressions Trace all possible paths, from any state to all destination states Transition expression to any given next state (= one line of the transition list) is product (N) of all conditions along path: ( condition) if branch taken (condition) if branch taken EG 36/56 - EE 45/65 Section III - 56 Example: s s ounter (XY) (X+Y) S Z X Y X +Y (XY) (XY) (X+Y) PS INPUT NS (XY) (XY) (X+Y) (XY) (X+Y) EG 36/56 - EE 45/65 Section III - 57

20 EG 36/56 - EE 45/65 Section III - 5 Example: s s ounter INPUT ** (XY) (XY) (X+Y) (XY) (X+Y) (XY) (XY) (X+Y) (XY) (X+Y) (XY) (XY) (X+Y) (XY) (X+Y) (XY) (XY) (X+Y) (XY) (X+Y) * = (XY) + (XY) + (XY) (X+Y) + (XY) (X+Y) + (XY) (X+Y) + (XY) (X+Y) 2* = (XY) (X+Y) + (XY) + (XY) (X+Y) + (XY) (X+Y) + (XY) + (XY) (X+Y) + ealing with omplexity ata unit (atapath) design Registers RTL language atapath onstruction ontrol unit (ontroller) design SM harts Implementation issues PLs ROM VLSI esign Outline EG 36/56 - EE 45/65 Section III - 59 Programmable Logic efinitions igital integrated circuit (MSI, LSI, VLSI) manufactured as a standard off-the-shelf component containing regular array of logic gates and flip-flops whose logic functions are determined by the application design engineer and implemented locally Many types of programmable logic sometimes generically called PLs (Programmable Logic evices) PL or PL PROM FPG ombinational output input PL EG 36/56 - EE 45/65 Section III - 6

21 EG 36/56 - EE 45/65 Section III - 6 Programmable Logic efinitions PL Programmable Logic rray first PLs simple programmable N/OR array programmed by blowing fuses by hand or by mask Programmable Logic PL Programmable rray Logic similar to a PL, but the ORarray is fixed most commonly used PL may include input/output flipflops GL Generic rray Logic can be configured to emulate the N/OR, flip-flop, and output structure of a variety of combinational and sequential PL devices EG 36/56 - EE 45/65 Section III - 62 Read-Only Memory (ROM) combinational circuit with n inputs and b outputs: ddress inputs (n-,..., ) n 2 n x b b ata ROM outputs (b-,..., ) Programmable values determined by user Nonvolatile contents retained without power Uniform (Random) ccess delay is uniform for all addresses EG 36/56 - EE 45/65 Section III - 63

22 EG 36/56 - EE 45/65 Section III - 64 Read-Only Memory (ROM) Two views: ROM stores 2 n words of b bits each, or ROM stores an n-input, b-output truth table n= 2 b= 4 Example: 3 2 Stores 4 4-bit words, or stores 4 functions of 2 input variables Using ROMs for ombinational Logic 3-input, 4-output combinational logic function: Inputs Outputs I I POL 4 ROM Y Y Y2 Y3 Function: 2-to-4 ecoder with Polarity ontrol 2 = Polarity ( = active Low, = active High), = I, I (2-bit input ) 3... = Y3...Y (4-bit decoded output) EG 36/56 - EE 45/65 Section III - 65 Internal Structure of 4 44 iode ROM +5 V R3 R2 R R 2 to 4 ecoder /w /w /w2 of n Word Lines /w3 iode No iode it Lines 2 3 Why use diodes? Why not replace them with wires? EG 36/56 - EE 45/65 Section III - 66

23 EG 36/56 - EE 45/65 Section III - 67 Types Of ROMs () Mask ROM onnections made by the semiconductor vendor Expensive setup cost Several weeks for delivery High volume only ipolar or MOS technology Word Line it Line PROM Programmable ROM onnections made by equipment manufacturer Vaporize (blow) fusible links with PROM programmer using high voltage/current pulses ipolar technology One-time programmable Internal Structure of Transistor ROM Replace diodes with MOS transistors hange decoder to active-high outputs +5 V w3 R3 R2 R R Transistor No transistor /3 /2 / / EG 36/56 - EE 45/65 Section III - 6 EPROM and EEPROM Structure V Floating gate Nonfloating gate ctive-high word lines ctive-low bit lines EG 36/56 - EE 45/65 Section III - 69

24 EG 36/56 - EE 45/65 Section III - 7 Types of ROMs (2) EPROM Erasable Programmable ROM harge trapped on extra floating gate of MOS transistors Exposure to UV light removes charge -2 minutes uartz Lid = expensive package Limited number of erasures (-) it Line Word Line EEPROM (E 2 ROM) Electrically Erasable ROM Floating gates charged/discharged electrically Not RM! (relatively slow charge/discharge) limited number of charge/discharge cycles (,) Types of ROMs (3) Flash Memory Electronically erasable in blocks, erase cycles Simpler and denser than EEPROM Often used for firmware EG 36/56 - EE 45/65 Section III - 7 ROM Type Summary Type Technology Read ycle Write ycle omments Mask ROM NMOS, MOS Mask ROM ipolar PROM ipolar EPROM NMOS, MOS EEPROM NMOS FLSH MOS 2-2 ns < ns < ns 25-2 ns 5-2 ns 25-2 ns 4 weeks Write once; low power 4 weeks Write once; high power; low density Write once; high power; no mask 5 minutes charge 5 minutes Reusable; low power; no mask charge μs/byte, writes/location limit μs/block, erase cycles EG 36/56 - EE 45/65 Section III - 72

25 EG 36/56 - EE 45/65 Section III - 73 This ecoder needs 64 6-input gates! onsider a 64 x ROM +5 V /w 5 6-to-64 ecoder /w /w63 64 x iode rray Very tall, narrow chip () Even worse for larger chips! How can we make it more square? 64 x ROM with 2-imensional 2 ecoding +5 V to ecoder /w /w /w7 x iode rray 2 7 to mux ecoder and mux = 3-input gates + 4-input gates lmost square chip! EG 36/56 - EE 45/65 Section III K x ROM with 2-2 ecoding 9 9 to 52 ecoder rray 7 2 to Mux 2 to Mux 2 to Mux 7 Is this a square chip? 2- ecoding / oincident selection 64k x = 2 6 * 2 3 = 2 9 square root (2 9 ) ~= 2 9 EG 36/56 - EE 45/65 Section III - 75

26 EG 36/56 - EE 45/65 Section III - 76 Internal 2 n x b ROM ontrol Structure m- Row decoder Power on Power on Storage array m m+ n- /S /OE Power on olumn multiplexer b- b-2 Programmable Logic dvantages esign flexibility etter design automation Higher density, fewer packages (compared to SSI-MSI) Less expensive Lower power Higher performance Programming Technologies Interconnections usually made by pass transistors controlled by memory bits of some type: ntifuse - permanent connections made electrically EPROM - charged floating gate, UV erasable EEPROM - charged floating gate, electrically erasable Flash Memory - charged floating gate, electrically erasable Programmed using - Hardware escription Languages EG 36/56 - EE 45/65 Section III - 77 Modern (VLSI) esign The VLSI chips that are used in most modern designs come in three varieties: ustom pproach: VLSI chips, or some of their parts, are designed by hand. Full ustom Vs. Standard ell - Using standard cell designs (same height, variable width) and routing channels simplifies the design process Highest ensity, Highest Manufacturing ost Semicustom pproach: The VLSI chips employ gate arrays and technology mapping. Gate array: a partially prefabricated I that incorporates a large number of identical gates (usually 3-input NN or NOR gates) that are laid out in a regular two-dimensional array. Technology mapping: The process of designing a logic function as a network of available devices. Lower ensity (-25% more gates than an equivalent custom design). Inexpensive: Requires only metal deposition (define interconnections), economy of scale. EG 36/56 - EE 45/65 Section III - 7

27 EG 36/56 - EE 45/65 Section III - 79 Modern (VLSI) esign The VLSI chips that are used in most modern designs come in three varieties: VLSI PLs Field Programmable Gate rrays (FPGs) VLSI modules that can be programmed to implement a digital system consisting of tens of thousands of gates. LSI PLs implement two-level combinational and sequential networks, FPGs allow the realization of multilevel networks and complex systems on a single chip! Highly reprogrammable! Low cost May produce slower network May require a larger silicon area