Outline. CPE/EE 422/522 Advanced Logic Design L03. Review: Clocked D Flip-Flop with Rising-edge Trigger. Sequential Networks

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1 Outline PE/EE 422/522 Advanced Logic Design L3 Electrical and omputer Engineering University of Alabama in Huntsville What we know ombinational Networks Analysis, Synthesis, Simplification, Buiing Blocks, PALs, PLAs, ROMs Sequential Networks: Basic Buiing Blocks What we do not know Design: Mealy, Moore Sequential Network Timing Setup and ho times Max clock frequency 3/6/23 UAH-PE/EE 422/522 AM 2 Sequential Networks Have memory (state) Present state depends not only on the current input, but also on all previous inputs (history) Future state depends on the current input and state Review: locked D Flip-Flop with Rising-edge Trigger X = x x 2... x n Q = Q Q 2... Q k x x 2 x n Z ( t ) = + Q ( t ) = Z = z z 2... z m Q F ( X ( t ), Q ( t )) G ( X ( t ), Q ( t 3/6/23 UAH-PE/EE 422/522 AM 3 )) z z 2 z m Flip-flops are commonly used as storage devices: D-FF, JK-FF, T-FF Next state The next state in response to the rising edge of the clock is equal to the D input before the rising edge 3/6/23 UAH-PE/EE 422/522 AM 4 Review: locked JK Flip-Flop Review: locked T Flip-Flop Next state JK = => no state change occurs JK = => the flip-flop is set to, independent of the current state JK = => the flip-flop is always reset to JK = => the flip-flop changes the state Q + = Q 3/6/23 UAH-PE/EE 422/522 AM 5 Next state T = => the flip-flop changes the state Q + = Q T = => no state change 3/6/23 UAH-PE/EE 422/522 AM 6

2 Review: S-R Latch, Transparent D-Latch Mealy Sequential Networks General model of Mealy Sequential Network () X inputs are changed to a new value (2) After a delay, the Z outputs and next state appear at the output of M (3) The next state is clocked into the state register and the state changes 3/6/23 UAH-PE/EE 422/522 AM 7 3/6/23 UAH-PE/EE 422/522 AM 8 x An Example: 842 BD to Excess3 BD ode onverter Q z t3 X (inputs) t2 t t t3 Z (outputs) t2 t t State Graph and Table for ode onverter 3/6/23 UAH-PE/EE 422/522 AM 9 3/6/23 UAH-PE/EE 422/522 AM State Assignment Rules Transition Table 3/6/23 UAH-PE/EE 422/522 AM 3/6/23 UAH-PE/EE 422/522 AM 2 2

K-maps Realization 3/6/23 UAH-PE/EE 422/522 AM 3 3/6/23 UAH-PE/EE 422/522 AM 4 ode converter X = _ => Z = _ Sequential Network Timing hanges in X are not synchronized with active clock edge =>

3 K-maps Realization 3/6/23 UAH-PE/EE 422/522 AM 3 3/6/23 UAH-PE/EE 422/522 AM 4 ode converter X = _ => Z = _ Sequential Network Timing hanges in X are not synchronized with active clock edge => glitches (false output), e.g. at tb Sequential Network Timing (cont d) Timing diagram assuming a propagation delay of ns for each flip-flop and gate (State has been replaced with the state of three flip-flops) 3/6/23 UAH-PE/EE 422/522 AM 5 3/6/23 UAH-PE/EE 422/522 AM 6 Setup and Ho Times For a real D-FF D input must be stable for a certain amount of time before the active edge of clock cycle => Setup time D input must be stable for a certain amount of time after the active edge of the clock => Ho time Propagation time: from the time the clock changes to the time the output changes tc max tp max tck tc max Maximum lock Frequency - Max propagation delay through the combinational network - Max propagation delay from the time the clock changes to the flip-flop output changes { = max(tplh, tphl)} - lock period + t p max tck tsu t ck t c max + t p max + t su Example: t p max = 5 ns, t su t gate = 5 ns = 5 ns, t ck f max = 2 * = 5 = = 2 MHz 5 ns ns Manufacturers provide minimum tsu, th, and maximum tplh, tphl 3/6/23 UAH-PE/EE 422/522 AM 7 3/6/23 UAH-PE/EE 422/522 AM 8 3

4 Ho Time Violation Occur if the change in Q fed back through the combinational network and cause D to change too soon after the clock edge Ho time is satisfied if: t p min + t c min What about X? t h Make sure that input changes propagate to the flip-flops inputs such that setup time is satisfied. t x t cx max + t su Make sure that X does not change too soon after the clock. If X changes at time ty after the active edge, ho time is satisfied if ty th tcx min 3/6/23 UAH-PE/EE 422/522 AM 9 Moore Sequential Networks x x 2 x n Outputs depend only on present state! Z ( t ) = + Q ( t ) = X = x x 2... x n Q = Q Q 2... Q k Z = z z 2... z m Q F( Q ( t )) G ( X ( t ), Q ( t 3/6/23 UAH-PE/EE 422/522 AM 2 )) z z 2 z m Inputs(X) General Model of Moore Sequential Machine Outputs depend only on present state! ombinational Network Next State lock State Register ombinational Network State(Q) X = x x 2... x n + Q ( t ) = G ( X ( t ), Q ( t )) Q = Q Q 2... Q k Z ( t ) = F( Q ( t )) Z = z z 2... z m Outputs(Z) ode onverter: Moore Machine S S Start S 3/6/23 UAH-PE/EE 422/522 AM 2 3/6/23 UAH-PE/EE 422/522 AM 22 ode onverter: Moore Machine Moore Machine: State Table Start S S S Do we need state S? How many states does Moore machine have? How many states does Mealy machine have? PS S S S X= S S S S NS X= S S - Z S Start S S Note: state S cou be eliminated (S == ), if was start state! 3/6/23 UAH-PE/EE 422/522 AM 23 3/6/23 UAH-PE/EE 422/522 AM 24 4

5 Moore Machine Timing State Assignments X = _ => Z = _ Guidelines to reduce the amount of combinational logic PS NS X= X= Z S S Moore Mealy Rule I: (S,, S), (, ), (, ) Rule II: (S, ), (, ), (, ), (, ), (, ), (, S) Rule III: (S,,,,, ) (S,,,, S) QQ2 S S -. S - Q3Q4 s S S S S S S S S - S 3/6/23 UAH-PE/EE 422/522 AM 25 3/6/23 UAH-PE/EE 422/522 AM 26 Moore Machine: Another Example Moore Network for NRZ-to-Manchester A onverter for Serial Data Transmission: NRZ-to-Manchester oding schemes for serial data transmission NRZ: nonreturn-to-zero NRZI: nonreturn-to-zero-inverted in input sequence the bit transmitted is the same as the previous bit; in input sequence transmit the complement of the previous bit RZ: return-to-zero for full bit time; for the first half, for the second half Manchester 3/6/23 UAH-PE/EE 422/522 AM 27 3/6/23 UAH-PE/EE 422/522 AM 28 Moore Network for NRZ-to-Manchester Synchronous Design Use a clock to synchronize the operation of all flip-flops, registers, and counters in the system all changes occur immediately following the active clock edge clock period must be long enough so that all changes flip-flops, registers, counters will have time to stabilize before the next active clock edge Typical design: ontrol section + Data Section Sequential machine to generate control signals to control the operation of data section Data registers Arithmetic Units ounters Buses, Muxes, 3/6/23 UAH-PE/EE 422/522 AM 29 3/6/23 UAH-PE/EE 422/522 AM 3 5

+ Data section // s= n*(n+a) // R=n, R2=a // R=s Design flowchart for SMUL operation Design ontrol section S S F B B B + BR A + B An Example LD(BR) DE(BR) 6 dec LD(R) RD(R) 6 BR rd rd LD(L) L(L)

6 + Data section // s= n*(n+a) // R=n, R2=a // R=s Design flowchart for SMUL operation Design ontrol section S S F B B B + BR A + B An Example LD(BR) DE(BR) 6 dec LD(R) RD(R) 6 BR rd rd LD(L) L(L) RD(BR) 6 R cl 6 6 L A 6 F 5.. ALU F 6 R2 6 6 B LD(R2) rd RD(R2) S S 6 Timing hart for System with Falling-edge Devices LD(A) A rd cl RD(A) L(A) 3/6/23 UAH-PE/EE 422/522 AM 3 3/6/23 UAH-PE/EE 422/522 AM 32 Timing hart for System with Rising-edge Devices Method Principles of Synchronous Design All clock inputs to flip-flops, registers, counters, etc., are driven directly from the system clock or from the clock ANDed with a control signal Result All state changes occur immediately following the active edge of the clock signal Advantage All switching transients, switching noise, etc., occur between the clock pulses and have no effect on system performance 3/6/23 UAH-PE/EE 422/522 AM 33 3/6/23 UAH-PE/EE 422/522 AM 34 Asynchronous Design Disadvantage - More difficult Problems Race conditions: final state depends on the order in which variables change Hazards Special design techniques are needed to cope with races and hazards Advantages = Disadvantages of Synchronous Design In high-speed synchronous design propagation delay in wiring is significant => clock signal must be carefully routed so that it reaches all devices at essentially same time Inputs are not synchronous with the clock need for synchronizers lock cycle is determined by the worst-case delay Read To Do Textbook chapters.6,.7,.8,.,.,.2 3/6/23 UAH-PE/EE 422/522 AM 35 3/6/23 UAH-PE/EE 422/522 AM 36 6

Outline. CPE/EE 422/522 Advanced Logic Design L04. Review: 8421 BCD to Excess3 BCD Code Converter. Review: Mealy Sequential Networks

Outline. CPE/EE 422/522 Advanced Logic Design L04. Review: 8421 BCD to Excess3 BCD Code Converter. Review: Mealy Sequential Networks Outline PE/EE 422/522 Advanced Logic Design L4 Electrical and omputer Engineering University of Alabama in Huntsville What we know ombinational Networks Analysis, Synthesis, Simplification, Hazards, Building