Introduction to Mechatronics. Fall Instructor: Professor Charles Ume. Analog to Digital Converter

Transcription

1 ME6405 Introduction to Mechatronics Fall 2006 Instructor: Professor Charles Ume Analog to Digital Converter

2 Analog and Digital Signals Analog signals have infinite states available mercury thermometer needle speedometer Digital signals have two states - on () or off (0) lights (on or off) door (open or closed) ADC digitizes an analog signal by converting data with infinite states to a series of pulses. The amplitudes of these pulses can only achieve a finite number of states.

3 What is an Analog to Digital Converter? Converts analog signals into binary words Clock signal Input analog signal Sample and hold A/D Conversion analog signal segment Output Equally spaced Digital signal

4 A/D Conversion Process A/D conversion is a two step process: Quantizing: breaking down analog value is a set of finite states. Encoding: assigning a digital word or number to each state.

5 Quantizing Output States Discretized Voltage Ranges (V) Takes 0-0v signals and separates it into set of discrete states with.25v increments

6 Quantizing The number of possible states that the converter can output is: N=2 n where n is number of bits Example: For a 3 bit A/D converter, N=2 3 =8. Number of decision points: = N-=8-=7 Analog quantization size: Q=(V max -V min )/N = (0V 0V)/8 =.25V

7 Encoding Output States Output Binary Encoded Equivalent

8 Accuracy ADC accuracy can be improved by: increasing the resolution which improves the accuracy in measuring the amplitude of the analog signal. increasing the sampling rate which increases the maximum frequency that can be measured.

9 Resolution 9 8 Low 9 8 High Signal Value Resolution = 2.50 v Signal Value Resolution =.25 v 0 Time 0 Time Resolution = analog quantization size (Q) 2 bit converter 3 bit converter 0v/2 2 =2.50v 0v/2 3 =.25v

10 Sampling Rate Signal Value Low Hz 5 2 Hz Signal Value High 0 Time 0 Time Sampling rate - Frequency which ADC evaluates analog signal

11 Sampling Rate - Aliasing Rule of thumb Nyquist criterion: Use a sampling frequency at least twice as high as the maximum frequency in the signal to avoid aliasing.

12 Accuracy Resolution = 2.50 V Sampling rate = Hz Resolution =.25 V Sampling rate = 2 Hz Signal Value Time Signal Value Time Both sampling rate and resolution can be increased to obtain better accuracy.

13 Types of A/D Converters Flash (Parallel) Converters Dual Slope Converters Voltage-to-Frequency Converters Successive-Approximation Converters

14 Flash (Parallel) Converter Comparator (Logic high) (Logic low) An n-bit flash converter uses 2 n - comparators

15 Flash (Parallel) Converter 0v Vin 8.75v 7.50v 6.25v 5.00v 3.75v 2.50v.25v resistor Octal to Binary Encoder Digital Code Output Example: If Vin = 6.00 V, then the first 4 comparators from the bottom will return a logic high signal while the top three will return a low signal. Octal 4 = Binary v Comparator

16 Flash (Parallel) Converter Advantages Very Fast Disadvantages Lower resolution (many comparators are required for higher resolution: 8 bit = 255 comparators) Higher cost

17 Dual-Slope Converter R C CTRL allows capacitor (C) to charge with rate given by Vin/RC for time T 0 (N 0 clock cycles). Then CTRL switched and allows capacitor to discharge for time T (N clock cycles) at a rate given by Vref/RC. Vref/N =Vin/N 0 Vin/RC Vref/RC Vref and N 0 are known and N is measured, so: Vin=(N /N 0 )Vref

18 Dual-Slope Converter Advantages Higher resolution Higher accuracy Lower cost Good noise immunity Disadvantages Slow

19 Voltage-to-Frequency Converters Converter takes in a voltage (Vin) and returns a series of pulses. Frequency of pulses is proportional to Vin.

20 Voltage-to-Frequency Converters Advantages Excellent noise reduction Disadvantages Slow Generally limited to 0 bits or less

21 Successive Approximation Converter Guess the answer, use a D/A to convert it to an analog voltage and compare it to the voltage being measured adjust your guess accordingly Similar to the ordering weighing (on a scale) of an unknown quantity on a precision balance, using a set of weights, such as g, 0.5g, 0.25g, etc. Control Logic Set Bit Result Clear Bit Comparator + - Digital to Analog Converter V IN Digital Output V REFH V REFL

22 Successive Approximation Converter Reliable Capable of high speed Conversion time is clock rate times number of bits. Example: For 8-bit conversion with 2-MHz clock rate: Conversion time = (clock period) x (#bits being converted) Conversion time= (0.5 micro-sec) x (8-bits) = 4µs

23 Summary of Converter Types Converter Type Speed Resolution Noise Immunity Cost Voltage/Frequency slow 4-24 good medium Dual Slope slow 2-8 good low Successive Approximation medium 0-6 little low Flash (Parallel) fast 4-8 little high *Resolution given in bits.

24 Successive Approximation Example 0-bit resolution or V of V ref V in =0.6V V ref =V Find the digital value of V in Bit Voltage

25 Successive Approximation Example MSB (bit 9) Divide V ref by 2 =.5V Compare V ref /2 with V in If V in is greater, turn MSB* ON If V in is less than V ref /2, turn MSB off Ie compare V in =0.6V and V= 0.5V Since 0.6 > 0.5 MSB = (turned on) (cont.)

26 Successive Approximation Example (cont.) Calculate the state of MSB- (bit 8) Compare V in =0.6V and V=V ref /2 + V ref /4 = = 0.75V Since 0.6 < 0.75 MSB- =0 (turned off) Calculate the state of MSB-2 (bit 7) Go back to the last voltage value that caused it to be turned on (in this case 0.5V) and add V ref /8 to it and compare with V in. Compare V in and (0.5 + (V ref /8)=0.625) Since 0.6 < MSB-2 =0 (turned off) 0 0

27 Successive Approximation Example (cont.) Calculate the state of MSB-3 (bit 6) Go back to the last voltage value that caused it to be turned on (in this case 0.5V) and add V ref /6 to it and compare with V in. Compare V in and (0.5 + (V ref /6)=0.5625) Since 0.6 > MSB-3 = (turned on) MSB MSB- MSB-2 MSB-3 0 0

28 Successive Approximation Example Digital Results: (cont.) MSB MSB- MSB-2 MSB-3 LSB Results: = V 0.8 Voltage Bit

29 A/D Conversion with the HC 6 channel/bit input Pin: VRL = 0 volts VRH = 5 volts Port E (analog input) Digital input on PE Analog Multiplexer A/D Converter CCF Result Register Interface ADR - result ADR2 - result 2 ADR3 - result 3 ADR4 - result 4

30 A/D Conversion within the HC Some additional notes: 0V <= analog input <= 5V Charge pump allows VRH max 6-7V VRL and VRH convert to $00 and $FF Digital input of Port E pins not recommended during A/D sample time

31 A/D Conversion with the HC What s the magic in the chip? HC Contains a sample and hold circuit, DAC, comparator, and SAR Sample and hold circuit samples and holds analog signal DAC generates a series of reference signals to be compared to the input signal Comparator compares sampled signal with reference signals. Result of comparison stored in SAR. When conversions are complete, the contents are dumped to appropriate result register George George W. W. Woodruff School School of of Mechanical Engineering, Georgia Georgia Tech Tech

32 A/D Conversion with the HC E Clock cycles: Conversion Sequence Write to ADCTL Sample (2) Bit 7 (4) 6 (2)_ (2)0 (2) End (2) Successive approximation st, ADR 2 nd, ADR2 3 rd, ADR3 4 th, ADR4 CCF total

33 A/D Conversion with the HC ADR#: ¼ of result registers SAR feeds. ADR behavior is governed by the ADCTL. CCF is the conversion complete flag, indicating the end of the A/D process. Internal RC oscillator may substitute for system E clock when E-clock frequency is below 750 khz

34 A/D Conversion with the HC Options Register ($039) ADPU CSEL IRQE DLY CME CR CR0 Bit: ADPU = A/D power up CSEL = Clock Select IRQE = Config. IRQ DLY = Enable start-up delay CME = Clock Monitor Bit 2 = not implemented CR = COP Timer Rate CR2 = COP Timer Rate

35 A/D Conversion with the HC ADPU: 0 = power down = power up CSEL: 0 = A/D and EEPROM use E clock = A/D and EEPROM use internal RC 00 µsec. delay is necessary to stabilize analog bias voltage after ADC is turned on DLY: Oscillator Startup Bit 0 = Coming out of Stop, no delay is used and MCU resumes within approx. 4 cycles. = After Stop Power-saving mode, 4000 E clock cycle delay imposed to allow crystal stabilization

36 A/D Conversion with the HC ADCTL register ($030) CCF SCAN MULT CD CC CB CA Bit: CCF = Conversion Complete flag CD CA = Channel control note: read only! See pg. 40 of Reference Guide Bit 6 = not implemented SCAN = Continuous Scan MULT = Controls number of channels

37 A/D Conversion with the HC ADR# Behavior Single Channel (MULT = 0) Multiple Channel (MULT = ) Single Conversion (SCAN = 0) Continuous Conversion (SCAN = ) One channel converted 4 times consecutively. The results are stored in ADR-ADR4 One channel is continuously converted. ADR-ADR4 overwritten 4 channels converted once. The results are stored in ADR-ADR4 4 channels are continuously converted. ADR-ADR4 overwritten

38 A/D Conversion with the HC A/D Result Registers (ADR ADR4): ADR = $03 ADR2 = $032 ADR3 = $033 ADR4 = $034 Note: All registers are read only accessible

39 Converter Channel Assignments Channel Number Channel Signal Result in ADRx if MULT = AN0 AN AN2 AN3 AN4 AN5 AN6 AN7 Reserved V () RH V () RL (V RH )/2 () Reserved (). Used for factory testing ADR ADR2 ADR3 ADR4 ADR ADR2 ADR3 ADR4 - ADR ADR2 ADR3 ADR4

40 A/D result registers Eight inputs on Port E AN0 (PE0) through AN7 (PE7) Four result registers ADR - ADR4, at $03 - $034 Can be configured to be either Inputs PE0-PE3 Inputs PE4-PE7 A single input, sampled four times in a row

41 Table 0-2. A/D Converter Channel Selection (Page 29 Technical Data) Channel Select Control Bits CD:CC:CB:CA XX Channel Signal AN0 AN AN2 AN3 AN4 AN5 AN6 AN7 Reserved V RH () V RL () (V RH )/2 () Result in ADRx If MULTI= ADR ADR2 ADR3 ADR4 ADR ADR2 ADR3 ADR4 ADR ADR2 ADR3 Reserved ADR4 George George W. W. Woodruff School School of of Mechanical Engineering, Georgia Georgia Tech Tech. Used for Factory Testing ---

42 A/D Control Registers ADCTL ($030) CCF 0 SCAN MULT CD CC CB CA Reset to: 0 0 u u u u u u MULT - Single or multiple channel 0: Samples a single channel four times before CCF is set : Samples four channels once before CCF is set CD,CC,CB,CA - Channel selection If MULT is 0, then CD-CA bits specify the channel If MULT is, then CD-CC bits specify the group: 00: Sample AN0-AN3, 0: Sample AN4-AN7 CB-CA bits have no meaning CCF - Conversion Complete Flag Set when all four conversions are complete Cleared by writing to ADCTL - starts the next conversion SCAN - Continuous scan mode 0: Take one set of four conversions and stop : Continually perform new conversions

43 A/D Options OPTION ($039) ADPU CSEL IREQ DLY CME 0 CR CR2 Reset to: 0 0 u u u u u u ADPU - A/D Charge Pump 0: Turn off the A/D : Turn on the A/D (by enabling the charge pump) Note: Wait at least 00 microseconds before using the A/D Waiting helps charge pump to stabilize between 6 to 7 volts Pump provides switching voltage to gates of analog switches of multiplexer CSEL - A/D Clock select 0: Use the E-clock for the A/D : Use a special internal A/D clock that runs at around 2MHz Note: If the E-clock is 750KHz or higher, CSEL should be 0. Otherwise CSEL should be.

44 Using the HC A/D to Read Chan. AN0 OPTION ($039) ADPU CSEL IREQ DLY CME 0 CR CR2 ADCTL ($030) CCF 0 SCAN MULT CD CC CB CA OPTION EQU $039 ADCTL EQU $030 ADR EQU $03 ADRESULT EQU $0000 ORG $2000 LDAA #$80 ;ADPU=,CSEL=0 STAA OPTION ; LDY #30 ;delay for 05 µs DELAY DEY BNE DELAY LDAA #$00 ;SCAN=0,MULT=0 STAA ADCTL ; start conversion LDX #ADCTL ;check for complete flag BRCLR $00,X #$80 * ;CCF is bit 7 LDAA ADR ;read chan. 0 STAA ADRESULT ;store in result SWI Turn on charge pump and select clock source Delay for charge pump to stabilize Set ADCTL to start conversion Wait until conv. complete Read result

45 Analog Input Translation Table () % of VRH-VRL, (2) VRH=5 VRL=0, (3) VRH=3.3 VRL=0 Bit Bit 0 % () 50% 25% 2.5% 6.25% 3.2%.56% 0.78% 0.39% Volts (2) Volts (3) Page 29 of the programming reference guide

46 A/D Converter Applications Strain Gages Load Cells Thermocouples Pressure Transducers Data Acquisition Devices Process and Store Microphones (voice circuitry) Digital Music Recording Digital Speedometer

47 Questions???