Expedited-Compact Architecture for Average Scan Power Reduction

Transcription

1 Expedited-ompact Architecture for Average Scan ower Reduction Samah ohamed Ahmed Saeed omputer Science Department New York University - olytechnic Institute zgur Sinanoglu omputer Engineering Department New York University - Abu Dhabi Abstract Excessive switching activity during scan operations endangers the reliability of the chip under test. We propose an architectural solution, which we refer to as Expedited-ompact, to mitigate the scan power problem that otherwise creates high heat dissipation and possibly hot spots. Expedited-ompact architecture advances the response compaction operations by utilizing scan chains as buffer. This enables the flushing of the transition-wise costly response data out of the system quickly, providing scan-out power savings. The proposed DfT-based approach is non-intrusive for design flow, requires a very minor investment in area, and in turn delivers significant and predictable savings in test power. The proposed solution reduces average test power without resorting to x-filling, enabling the application of orthogonal x-filling techniques in conjunction. Keywords: Test power, scan power, shift power, test compression, response compaction 1 Introduction Excessive switching activity during scan operations endangers the reliability of the chip under test. Elevated levels of peak power, which is the maximum instantaneous power throughout the entire test process, may result in yield loss, while high levels of average power that is the total power dissipation averaged over the duration of the test application process leads to the overheating of the chip under test []. As the shift operations dominate the test application process, average power mostly depends on scan power, and thus, the impact of capture power on average power is negligible. apture power is more of a concern when the target is reductions in peak power. Researchers have proposed numerous scan power reduction methodologies, ranging from test generation and x-filling to scan chain segmentation via clock gating; various papers [, 3, 4, 5, 6, 7] outline these techniques in detail. A recent trend has been low-power test solutions in the context of compression-based scan architectures where filling of x s for higher compression and for lower power are two conflicting objectives. Test generation and/or x-filling solutions for addressing shift and/or capture power have attained reductions at the expense of an increase in pattern count, and thus in test costs. An ideal solution is one that retains cost-quality metrics (pattern count, compression level, fault/defect coverage) intact without interfering with the design flow via intrusive techniques such as clock gating. Very recently, handra et al proposed a Design-for-Testability (DfT) based approach [8], which we shall refer to as Deferred- Broadcast (DB), for reducing scan-in power in the Illinois scan architecture. In this scheme, only one reference chain receives and subsequently broadcasts the stimulus into the other chains during the final small fragment of the shift process, thus allowing all-but-one chains to receive constant- s for the majority of shift cycles. Lower scan-in power is the end-result, while the scan chains eventually receive the intended stimulus intact prior to capture; and, this technique works without clock gating. The shortcoming of the DB architecture [8] is that it only targets scan-in power reduction and overlooks scan-out power. While each stimulus and response transition equally contributes to switching activity during test, scan-out power typically dominates test power; a DfT engineer can always fill the stimulus don t care bits (x s) that remain post-compression properly (-fill or repeat-fill) to leash the scan-in power, while such a direct control over response transitions, with the exception of probabilistic and inexact simulations, does not exist. Thus, although the DB architecture [8] may attain significant savings in scan-in power, these savings may correspond to only a small fraction of the overall scan power. In this work, we propose a complementary solution, Expedited-ompact (E), that targets scan-out power reduction, reducing average scan power. The expedited-compact feature in the proposed architecture enables the collection of the compacted responses in a few chains by utilizing them as buffer. verwriting of the captured response (upon its expedited compaction) in all the other scan chains with shifted constant- values in turn delivers reductions in scan-out power. For industrial cases that employ -fill so as to eliminate transitions in stimuli, the proposed technique is 5 to 66 times more effective than DB [8] in reducing average test power. The proposed features incur a very minor area cost, yielding significant power savings cost-effectively. Furthermore, as the proposed E and the previous DB approaches are complementary and orthogonal, their joint application delivers both scan-in and scan-out power reduction. We have presented a preliminary version [1] of this work at the VLSI Test Symposium 11 in Dana oint, A, USA, and received the best paper award. opyright (c) 11 IEEE. ersonal use is permitted. For any other purposes, permission must be obtained from the IEEE by ing pubs-permissions@ieee.org.

2 Reference chain Region 1 Region omp. Resp / of shift cycles done shift cycles done Figure 1. Expedited-ompact (E) - regions E architecture does not require design-flow intrusive hardware such as clock gating logic, retaining the clock tree intact, which differentiates the proposed solution from the traditional scan chain segmentation techniques [9]. It retains test development (test generation, x-fill) and application (test data, pattern count, fault/defect quality) intact. E can deliver 7-85% average scan power reduction at a projected area cost of less than.1% for large-sized industrial circuits. roposed Expedited-ompact (E) Architecture Assume that a given scan architecture has four scan chains feeding a 4x1 compactor; Figure 1 provides the proposed E architecture for such an architecture. As the compactor has a single output, only one chain (topmost) is designated as the reference chain (R), while the other (three) chains are the shadow chains (S). The additional compactor (shaded color) introduced in between the regions performs the expedited compaction operation. The new compactor feeds the reference chain of Region with the compressed response of all the chains of Region 1, while simultaneously the original compactor propagates the compressed response of Region to the scan-out channel. Also during the first half of the shift operations, constant- stimulus feeds the shadow chains of Region. By the end of the first half of shift cycles, the chains in Region 1 consist of inserted stimulus, the reference chain in Region consists of the compacted response, and the shadow chains of Region consist of all s. In the second half of the shift cycles, stimulus feed into all the chains in the Region 1 continues, while the compacted response in the reference chain of Region passes on to the scan-out channel. Simultaneously, the stimulus in Region 1 passes on to Region. A simple counter-based controller, similar to the one in [8], can control the select lines of the multiplexer, eliminating the need for any dedicated external pins or additional control data. Note that E does not require physical partitioning of the chip but rather inserts, on the test path, multiplexer and compaction logic, which is typically slow and can be distributed physically to ease routing. As the associated delay can already be afforded in the conventional scan (between the last scan cell and the output channel), it is reasonable to expect that the same delay can be tolerated in between the scan cells; if not, scan pipelining or balancing registers [1] can be utilized at the expense of additional area. While Figure 1 illustrates the proposed E architecture for only two regions, a larger number of regions can increase the scan-out power savings. E with r regions enables the filling of all the shadow chains, except for those in the leftmost region, with s subsequent to one r th of the shift cycles, collecting all the compacted responses in the reference chain at this time. Thus, during the remainder of shift cycles (the last r 1 r portions), the scan-out power dissipation occurs only in the reference chain. We will show in the next section that E attains a reduction factor of in average scan-out power for c chains. It is important to differentiate E from another architectural solution that breaks chains into shorter ones, utilizes multiple compactors and reduces the shift speed. Such a solution delivers average power savings while retaining the test time similar to E; yet key features of the scan architecture, such as the number of scan chains, the number of output channels and thus the tester interface and/or compactor characteristics (if the number of channels is reduced) and shift speed are changed. As the power savings of E stem from the switching activity reduction due to the constant- shift-in enabled by the use of multiple compactors, these key features are retained in a scan architecture with E. As a multiplexer driven by a constant- on one of the data inputs simplifies down to an AND gate, the cost of E per chain, assuming a simple XR tree as the compactor, for instance, is approximately r 1 XR gates and r 1 AND gates. Based on the area constraints and targeted power reduction levels, we can appropriately adjust r, enabling a cost-effective trade-off between area and power; larger values for r deliver larger savings in scan-out power yet at the expense of higher area cost. opyright (c) 11 IEEE. ersonal use is permitted. For any other purposes, permission must be obtained from the IEEE by ing pubs-permissions@ieee.org.

3 Inserted ontent Scan-in ower Scan-out ower ulus Response s r ulus ulus s Response Response r ulus onstant- s onstant- Response r onstant- onstant- Table 1. ower dissipation scenarios. r/ r/ r/ r/ r/ r/ 1/4 of shift cycles done r/ r/ r/ r/ r r/ r r/ r /4 of shift cycles done r r r 3 Expected ower Reductions r/ r/ r/ 3/4 of shift cycles done r r r shift cycles done Figure. ower dissipation savings of 4-region E with respect to traditional scan In our expected power saving analysis, we will refer to the basic scan architecture with a response compactor as the base case. We pursue a simplified power model wherein the number of transitions in scan cells defines the power value, as the two strongly correlate [11]; we validate the accuracy of this model in the Experimental Results Section. s ( r ) denotes the expected number of transitions induced by only stimulus (response) transitions in a fragment of l scan cells over a shift period of l cycles; s = t s l and r = t r l, where t s and t r denote the transition probability between consecutive stimulus bits and consecutive response bits, respectively. In Table 1, we present the expected power dissipation levels for different scenarios for an l-bit scan chain fragment, which vary in the bit vector that the fragment receives serially and the bit vector that the fragment initially contains. We express the scan-in and scan-out power components separately. Replacing a stimulus (response) fragment shift-in with a constant- shift-in, and replacing a stimulus (response) fragment shift-out with a constant- shift-out yields a power saving of s / ( r /) each. Figure provides the power dissipation savings of the E technique with respect to traditional scan in every scan chain fragment during different intervals of shift operations. From this figure, we observe savings in the scan-out power component, while the scan-in power component remains intact. We can express the expected power dissipation level for the traditional (base) and E architecture with c chains, each with r regions (r = 4 in the example), as: r/ r/ r/ We can see that E attains a reduction factor of this reduction factor is 16 7 base = s r c E = s r c + r r c + r r (r + c 1) in scan-out power only; for our example above (r = 4 and c = 4), =.3x. Apparently, the larger values of c and r deliver higher savings in scan-out power. 4 Deferred-Broadcast [8] (DB) and DB+E Architectures We illustrate DB with a single-input fanout-based decompressor, which is how [8] originally defined this scheme, while we later on discuss the extension of DB for other basic combinational decompressors, an aspect missing in [8]. For brevity purposes, we illustrate the two orthogonal techniques DB and E together, which we refer to as DB+E. Figure 3 provides the DB+E architecture for a single scan-in channel fanning out to four scan chains. Also, in this example, the DB technique decomposes every scan chain into four blocks. Simultaneous to the expedited compact operations, in the first (1) () opyright (c) 11 IEEE. ersonal use is permitted. For any other purposes, permission must be obtained from the IEEE by ing pubs-permissions@ieee.org.

4 Reference chain R1 R R3 R4 S11 S1 S13 S1 S S3 S31 S3 S33 S41 S4 S43. Resp. Resp. Resp.... Resp.... Resp /4 of shift cycles done /4 of shift cycles done Resp /4 of shift cycles done shift cycles done Figure 3. DB + E - 4 blocks, regions three quadrants of the shift cycles, only the reference chain receives the broadcast stimulus, filling in the first three blocks of the reference chain, while simultaneously the shadow chains receive constant- s. In the last (fourth) quadrant of the shift cycles, the deferred broadcast operation takes place; the R i and S ij blocks receive the broadcast stimulus in R i 1, while the scan-in channel broadcasts stimulus into R 1 and S 1j blocks. By the end of the last quadrant of shift cycles, all the chains will have received the intended broadcast stimulus. ower reduction in the DB architecture (with no E) stems solely from the constant- stimuli that we pump into the shadow chains, delivering scan-in power reductions. As the DB scheme shifts out the responses intact, however, scan-out power remains the same. A similar analysis to the one in the previous section can show that DB attains a reduction factor of power where b and c denote the number of blocks and chains, respectively, as: b c (b+c 1) in scan-in DB = s b (b + c 1) + r b c The cost of DB per scan chain is approximately 1 AND gate and b 1 multiplexers. (3) DB+E = s b (b + c 1) + r r (r + c 1) b c (b+c 1) DB with b blocks together with E with r regions result in a reduction factor of in scan-in power and a reduction factor of in scan-out power; in this DB+E architecture, b and r can have distinct values. For very large values of b (r) and c, the overall reduction ratio of the DB architecture approaches 1 + s r, while E delivers an overall power reduction ratio of 1 + r s. When s and r are comparable, both reduction ratios asymptotically approach x. The typical expectation, however, is that r is much larger than s, as proper x-fill techniques enable reductions in s while no such direct control exists over r. In such cases, the reduction by the DB architecture barely exceeds 1x, while E can deliver very high reduction ratios with large values of b (r) and c. 5 Application Domain and Extensions The proposed E technique is applied with a given type of compactor chosen by the DfT designer. The conventional response compaction applies the same compaction operation by a single hardware unit sequentially on numerous regions, as the data of these regions pass by; the proposed E technique applies the same operation concurrently on each region by multiple of the same hardware units operating in parallel. In E, the compacted responses that have been collected in the reference chains bypass all the compactors on the way to the output channels, producing the same compacted response with respect to the conventional case; aliasing, masking, fault/defect coverage and diagnostic properties of the given scan architecture are perfectly retained. Furthermore, the patterns are applied in an identical manner; pattern count, test time and data volume are also retained. We also (4) opyright (c) 11 IEEE. ersonal use is permitted. For any other purposes, permission must be obtained from the IEEE by ing pubs-permissions@ieee.org.

5 note that the proposed technique copes with the more challenging problem of reducing power in the compression mode. In the case of multiple compression/compaction modes [1], the same reconfigurable/dual compactor needs to be repeated to enable the E operations; furthermore, the multiplexing logic that enables multiple compression modes can be reused to lower the cost of E. ower dissipation in the serial top-up mode can always be lowered by properly filling the don t cares, which constitute the majority of the bits of uncompressed patterns. 5.1 Uneven Scan hain Lengths The proposed E architecture can accommodate for uneven scan chain lengths. As we utilize the reference chain fragments as buffers for the compacted responses, one constraint is that the reference chain fragments in a region should be longer than or equal to the longest chain fragment in the neighboring region to its left. We can ensure this by inserting the E logic in such a way that all fragments in all regions except for the leftmost one are identical in length, which are longer than or equal to the longest chain fragment in the leftmost region. Similar constraints apply to the DB architecture. 5. E With lock Gating As we mentioned earlier, one important and beneficial aspect of the proposed E architecture is its capability to deliver power savings without resorting to design-intrusive clock-gating. However, we also note that power dissipation in clock trees can be significant. If clock-gating is indeed permissible, E can work with clock-gating also. In such an implementation, we can shut off the clock of the shadow chains in a region from the time of completion of the expedited compaction operation (reference chain has collected the compressed responses and shadow chains have received constant- s) until the chains receive their stimulus. During this period, dynamic power dissipation in the corresponding clock trees disappears. In the DB+E architecture with clock gating, we can extend the shut off of the clock of the shadow chains until the beginning of the deferred broadcast operation, providing a wider window where we can further reduce the power dissipation in the clock trees. 5.3 Response Unknowns Every response compactor bears a particular unknown (x) mitigation characteristic. An x-clean design can benefit from the use of a ISR given that a serial scan mode can be enabled for diagnostics. The proposed E architecture can also accommodate ISRs by inserting multiple copies of the ISR in between the regions in order to expedite the response compression, yet without the need for any reference chains (buffers). The scan-out power reduction ratio is improved to r, the number of regions. The presence of unknown x s in the design necessitates the use of masking in conjunction with the ISR. This is a challenge for the proposed E scheme; as the expedited compaction operations should finish by the end of the first r th of the shift cycles, so should the load of the entire mask data. In an effort to retain the number of mask channels intact, an r-bit buffer can help distribute r bits of mask data in every cycle to r ISRs, necessitating the mask channels be operated r times faster. Another approach to mitigate x s while retaining some diagnostic capabilities is the use of multi-output XR compactors [13], rather than simple single-output XR tree. Implementing E in this case necessitates the use of multiple reference chains: as many reference chains (n) as the number of scan-out channels. For a 4x XR-based compactor, for instance, the example in Figure 1 can be slightly modified by having the top two chains as the reference chains, and having constant- shift operations in the bottom two chains only. Apparently, the power reduction benefit will be reduced compared to the single-output XR tree; (n r+c n) the scan-out power reduction factor becomes for a c by n response compactor (n scan-out channels). This general formula can be used to derive the power reduction factor for any case; for a single-output XR tree (n = 1), the scan-out power reduction ratio is, while for a ISR (n = ), this ratio degenerates to r. (1 r+c 1) = 5.4 Extensions for DB Similar extensions can be foreseen for the DB architecture as well, although [8] presented the original idea for a particular decompressor, namely, a single-input broadcast (fanout) decompressor. A generalized deferred decompress scheme can save scan-in power with other basic types of combinational decompressors, such as multi-input fanout decompressors or combinational XR-based decompressors; such a scheme can use b copies of an n by c decompressor (n scan-in channels) along with n designated reference chains. The end-result would be a scan-in power reduction factor of 6 Experimental Results b c (n b+c n). We have computed the power reduction results of DB by assuming an Illinois architecture, and the results of E by assuming various compactors (XR-based and ISR). We utilize a few ISAS89 benchmark circuits (test data generated with ATLANTA opyright (c) 11 IEEE. ersonal use is permitted. For any other purposes, permission must be obtained from the IEEE by ing pubs-permissions@ieee.org.

6 E (3 regions) DB (1 blocks) X-fill Scan-out gating ircuit Scan cell switching model Timing-based model [8] [14] [15] s % 47.9% 1.% 31.6% -4% s % 5.4% 9.1% 3.8% for other s % 39.7% 15.% 19.3% benchmarks Table. Average scan power reduction comparisons ircuit scan cells chains DB (1 blocks) [8] E ( regions) E (3 regions) E (4 regions) E (6 regions) E (1 regions) A + single-output XR tree 15, B + single-output XR tree, single-output XR tree 61, two-output XR tree 61, five-output XR tree 61, A + ISR 15, B + ISR, ISR 61, Table 3. Average scan power reductions (%) for industrial circuits ATG tool) and the industrial test data that we obtained from adence, which consists of 1 fully specified (x s remaining post-compression -filled) stuck-at patterns and their responses for three industrial designs. Table provides the average power reduction comparisons where the underlying scan architecture is assumed to be a single scan-in channel feeding eight scan chains that drive a single-output XR tree. The proposed scheme also assumes -filling of don t cares that remain post-compression in the stuck-at patterns. All the techniques deliver perfect stuck-at fault coverage levels of 89.9%, 99.5% and 95.9%, respectively. olumns and 3 compare the scan power reductions by the proposed scheme with respect to the scan cell switching model [11] and a more elaborate timing-based model (via running odelsim and creating a VD file that captures all the switching activity in the circuit); the results closely correlate, validating the accuracy of the simple scan cell switching model. The proposed 3-region E approach delivers 4-5% scan power reductions at the expense of 14 XRs, multiplexers and 14 AND gates (.17% area cost). The DB approach [8] delivers 1-15% scan power reduction, while the x-fill approach provides around 3% power savings at no area cost; a potential disadvantage of the x-fill techniques is the degradation in defect coverage and/or pattern count inflation. The scan-out gating approach may possibly incur timing penalties in addition to.1-.3% area cost; the approach in [15] is applied at the RT-level to prevent timing penalties. ost importantly, all the four schemes compared in this table are orthogonal techniques and can be applied in conjunction to minimize scan power. Table 3 provides the average power reduction results of the proposed E technique that we applied on the test data of three industrial designs. For the largest circuit, for instance, DB delivers almost no reduction, while the full-capacity 1-region E delivers a reduction around 9%. n the other extremal point, the proposed E delivers 35-5% reductions in scan power for these designs with only a single replication of the compactor ( regions) cost-effectively. In between these two extremal points, the cost-effective 3-region E delivers 45-65% reductions; for the largest design (), 3-region E delivers an overall scan power reduction of 63% for a single-out compactor, and 54% for a five-output compactor, mimicking the end-result of designer s choices in enhancing x-mitigation capabilities. We can obtain higher levels of reductions in the case of a ISR due to the absence of a reference chain that collects the compacted responses. As only the test data was available to us, we can gauge the area cost of DB and E architectures with respect to the scan overhead (the area cost due to scan multiplexers). er-chain cost of DB with 1 blocks is 11 UXes and 1 AND gate, while per-chain cost of E (with XR tree as the compactor) with, 3, and 1 regions is 1 XR + 1 AND gate, XR + AND gates, and 11 XR + 11 AND gates, respectively. For Design that has 61K registers, for instance, as each scan chain has more than K scan cells, the per-chain scan overhead is more than UXes. The area cost of DB, E and DB+E correspond to a small fraction of scan overhead. We can therefore project the cost of DB, E and DB+E architectures to be less than.1% of the die area for even larger industrial designs. We also provide a switching activity plot for a duration that spans a little more than the shift and capture operations of three test patterns for various E architectures in Figure 4. All six plots (corresponding to E with varying number of regions) present a similar behavior; peak switching activity occurs during the capture operations where roughly half of the 61K flip-flops toggle, and this activity decays as shift operations proceed. The underlying reason for this behavior is that the responses embed more transitions compared to the stimuli; as more stimuli enter the scan chains and as the responses exit the system, switching activity reduces. E architectures with a larger number of regions deliver a quicker silencing of the switching activity. 7 onclusions In this paper, we propose a DfT-based solution that can reduce average test power significantly in a cost-effective manner without resorting to any x-filling techniques. The proposed solution is simple, scalable, and retains test data and quality intact, as observed responses are the same with or without E. Furthermore, E is non-intrusive for design flow, as it does not require clock gating for power savings. The proposed E architecture advances the response compaction operations, ensuring that only opyright (c) 11 IEEE. ersonal use is permitted. For any other purposes, permission must be obtained from the IEEE by ing pubs-permissions@ieee.org.

7 Figure 4. Switching activity (y-axis: number of toggles) vs time (x-axis: the cycle number) plot for E on Design : lots from top to bottom correspond to E with 1,, 3, 4, 6 and 1 regions, respectively. the reference chain holds the compacted response during the majority of shift cycles, thus enabling a constant- feed into all the other chains. The proposed E architecture also offers a power-area co-optimization for designs with a very tight area budget. It can still deliver significant reductions in test power at reduced area costs. For industrial test cases we have experimented with, we observe 7-9% reductions in test power, boding well for even larger-sized circuits. References [1] S.. Saeed and. Sinanoglu, Expedited response compaction for scan power reduction, in VLSI Test Synposium, 11, pp []. Girard, Survey of low-power testing of VLSI circuits, IEEE Design and Test, vol. 19, no. 3, pp. 8 9,. [3] J. Saxena, K.. Butler, V. B. Jayaram, S. Kundu, N. V. Arvind,. Sreeprakash, and. Hachinger, A case study of IR-drop in structured at-speed testing, in International Test onference, 3, pp [4] S. Ravi, ower-aware test: hallenges and solutions, in IEEE International Test onference, 7, pp [5] S. Ravi, R. arekhji, and J. Saxena, Low power test for nanometer system-on-chips (socs), Journal of Low ower Electronics, vol. 4, pp. 81 1, 8. [6].. Ravikumar,. Hirech, and X. Wen, Test strategies for low-power devices, Journal of Low ower Electronics, vol. 4, pp , 8. [7] D. zysz,. Kassab, X. Lin, G. rugalski, J. Rajski, and J. Tyszer, Low-power scan operation in test compression environment, IEEE Transactions on omputer-aided Design of Integrated ircuits, vol. 8, no. 11, pp , 9. [8] A. handra, F. Ng, and R. Kapur, Low power Illinois scan architecture for simultaneous power and test data volume reduction, in Design, Automation and Test in Europe onference, 8, pp [9] L. Whetsel, Adapting scan architectures for low power operation, in International Test onference,, pp [1] Z. Qi, H. Liu, X. Li, D. Wang, Y. Han, H. Li, and W. Hu, A scalable scan architecture for godson-3 multicore microprocessor, in ATS, 9, pp [11] R. Sankaralingam, N. A. Touba, and B. ouya, Reducing power dissipation during test using scan chain disable, in VLSI Test Symposium, 1, pp [1] A. handra, Y. Haihua, and R. Kapur, ultimode illinois scan architecture for test application time and test data volume reduction, in VLSI Test Symposium, 7, pp [13] S. itra and K. S. Kim, X-compact: An efficient response compaction technique for test cost reduction, in IEEE International Test onference,, pp [14] X. Liu and Q. Xu, n simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment, International Test onference, p. 9.3, 9. [15] E. Alpaslan, Y. Huang, X. Lin, W.-T. heng, and J. Dworak, n reducing scan shift activity at RTL, IEEE Transactions on omputer- Aided Design of Integrated ircuits, vol. 9, no. 7, pp , 1. opyright (c) 11 IEEE. ersonal use is permitted. For any other purposes, permission must be obtained from the IEEE by ing pubs-permissions@ieee.org.