Chapter 11 Latches and Flip-Flops

Transcription

1 Chapter 11 Latches and Flip-Flops SKEE1223 igital Electronics Mun im/arif/izam FKE, Universiti Teknologi Malaysia ecember 8, 2015

2 Types of Logic Circuits Combinational logic: Output depends solely on the present input. Has no memory. Sequential logic: Output depends not only on the present input and also on past history of inputs. Has memory. Synchronous sequential logic Use a clock signal to regulate operations. Simpler to design Asynchroous sequential logic oes not use a clock.

3 Types of Memory Elements Ungated Latches Gated Latches Flip-flops

4 Bistable Circuits Bistable circuit Any circuit stable in 0 or 1 Has memory Value does not change by itself Simplest bistable circuit : cascaded inverters

5 SR Latch SR = set/reset Replace inverters in prev page with NOR gates When S = R = 0, operates exactly as cascaded inverters R S R S

6 SR Latch S R Logic symbol. S R (next) (next) Action 0 0 No change Reset Set Forbidden Characteristic table.

7 SR Latch S R Unknown values Set Reset Set Illegal inputs Both outputs LOW and are always opposite S = R = 0 holds previous value S = 1, R = 0 sets to 1 S = 0, R = 1 resets to 0 S = R = 1, both and goes to 0, forbidden state

8 S R Latch Same idea as SR latch S and R are active low R S S R (next) (next) Action Forbidden Set Reset 1 1 No change

9 Gated SR Latch R S EN EN S R EN = 1 enables latch opens gate for SR inputs to cross-coupled gates works like ungated SR latch EN = 0 disables latch holds prev state ignores SR inputs

10 Gated SR Latch S EN R EN S R (next) Action 0 X X No change No change Reset Set X Forbidden EN S R Set Reset

11 Latch EN EN Modify SR latch to avoid SR=11 condition EN = 1 latch become transparent input is passed to output after some delay EN = 0 disables latch ignores inputs holds last input when EN went 1 0

12 Latch EN EN (next) Action 0 X Storage state Transparent mode Transparent mode EN

13 Clock Inputs Synchronous digital systems use a clock Clock signal is distributed to all system components All outputs change simultaneously when a clock pulse arrives Clock. T 1 T 2 T 3 T 4 T 1 = T 2 = T 3 = T 4 Not a clock. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4

14 Parts of a Clock Signal Clock period Falling edge Clock width Rising edge evice Latch Gated latch Flip-flop How it uses the clock oes not use the clock Enabled when clock is high Triggered by rising or falling clock edge

15 Master Slave Flip-Flop EN EN Clock Master Slave Clock high Master enabled, slave disabled Input is transparently passed on to master Clock low Master disabled, slave enabled master is locked, and read by slave slave is updated

16 Flip-Flop Clk (next) Action 0 X No change 1 X No change 0 0 Reset 1 1 Set Set latch CLK S Output latch Reset latch R

17 Flip-Flop a Clock Clock Clk b a b c c

18 T Flip-Flop T Clk T (next) Action 0 X No change 1 X No change 0 Hold 1 Toggle T Clock

19 JK Flip-Flop J K C S R (next) Action 0 X X No change 1 X X No change 0 0 No change Reset Set 1 1 X Toggle Clock J K Set Reset Reset Toggle Toggle Toggle

20 JK Flip-Flop J T J Clock Clock K K K J Clock C

21 Flip-Flop Timing Flip-flop input Clock input t SU t H Flip-flop output t CO t s Setup time The time a control input must be maintained before the clock transition. t h Hold time The time a control input must be maintained after the clock transition. t PC Propagation delay from clock to output change The time a flip-flop changes after a clock edge is given

22 74x74 PET FF PR CLR Preset Clear Clock (next) x x x x x x x x NA

23 74x76 Master Slave JK FF J K PR CLR Preset Clear J K Clock (next) x x 0,1 0 1 x x x x x x x x x NA

24 SKEE