Advanced Digital Logic Design EECS 303
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1 Advanced Digital Logic Design EECS Teacher: Robert Dick Office: L477 Tech Phone:
2 Outline Introduction Reset/set latches Clocking conventions D flip-flop Robert Dick Advanced Digital Logic Design
3 Section outline Introduction Reset/set latches Clocking conventions D flip-flop. Introduction Reset/set latches Clocking conventions D flip-flop 3 Robert Dick Advanced Digital Logic Design
4 Flip-flop introduction Introduction Reset/set latches Clocking conventions D flip-flop Stores, and outputs, a value Puts a special clock signal in charge of timing Allows output to change in response to clock transition More on this later Timing and sequential circuits 4 Robert Dick Advanced Digital Logic Design
5 Introduction Reset/set latches Clocking conventions D flip-flop Introduction to sequential elements Feedback and memory Memory Latches 5 Robert Dick Advanced Digital Logic Design
6 Feedback and memory Introduction Reset/set latches Clocking conventions D flip-flop Feedback is the root of memory Can compose a simple loop from NOT gates 6 Robert Dick Advanced Digital Logic Design
7 Feedback and memory Introduction Reset/set latches Clocking conventions D flip-flop Feedback is the root of memory Can compose a simple loop from NOT gates However, there is no way to switch the value 6 Robert Dick Advanced Digital Logic Design
8 TG and NOT-based memory Introduction Reset/set latches Clocking conventions D flip-flop Can break feedback path to load new value However, potential for timing problems 7 Robert Dick Advanced Digital Logic Design
9 Section outline Introduction Reset/set latches Clocking conventions D flip-flop. Introduction Reset/set latches Clocking conventions D flip-flop 8 Robert Dick Advanced Digital Logic Design
10 Reset/set latch Introduction Reset/set latches Clocking conventions D flip-flop R R S Q Q S Q 9 Robert Dick Advanced Digital Logic Design
11 Reset/set timing Introduction Reset/set latches Clocking conventions D flip-flop 00 Reset Hold Set Reset Set Race R S Q Q Unstable state Unstable state 0 Robert Dick Advanced Digital Logic Design
12 RS latch state diagram Introduction Reset/set latches Clocking conventions D flip-flop 00 0 output=q Q input=r S Robert Dick Advanced Digital Logic Design
13 Clocking terms Introduction Reset/set latches Clocking conventions D flip-flop Input T su T h Clock Clock Rising edge, falling edge, high level, low level, period Setup time: Minimum time before clocking event by which input must be stable (T SU ) Hold time: Minimum time after clocking event for which input must remain stable (T H ) Window: From setup time to hold time 2 Robert Dick Advanced Digital Logic Design
14 Gated RS latch Introduction Reset/set latches Clocking conventions D flip-flop S Q R ENB Q 3 Robert Dick Advanced Digital Logic Design
15 Gated RS latch Introduction Reset/set latches Clocking conventions D flip-flop S R ENB Q Q 4 Robert Dick Advanced Digital Logic Design
16 Memory element properties Introduction Reset/set latches Clocking conventions D flip-flop Type Inputs sampled Outputs valid Unclocked latch Always LFT Level-sensitive latch Clock high LFT (T SU to T H ) around falling clock edge Edge-triggered flip-flop Clock low-to-high transition Delay from rising edge (T SU to T H ) around rising clock edge 5 Robert Dick Advanced Digital Logic Design
17 Section outline Introduction Reset/set latches Clocking conventions D flip-flop. Introduction Reset/set latches Clocking conventions D flip-flop 6 Robert Dick Advanced Digital Logic Design
18 Clocking conventions Introduction Reset/set latches Clocking conventions D flip-flop Active high transparent D Q CLK Active low transparent D Q CLK Positive (rising) edge D Q CLK Negative (falling) edge D Q CLK 7 Robert Dick Advanced Digital Logic Design
19 Introduction Reset/set latches Clocking conventions D flip-flop Timing for edge and level-sensitive latches D Clk Q edge Q level 8 Robert Dick Advanced Digital Logic Design
20 Introduction Reset/set latches Clocking conventions D flip-flop Latch timing specifications Minimum clock width, T W Usually period / 2 Low to high propegation delay, P LH High to low propegation delay, P HL Worst-case and typical 9 Robert Dick Advanced Digital Logic Design
21 Latch timing specifications Introduction Reset/set latches Clocking conventions D flip-flop Example, negative (falling) edge-triggered flip-flop timing diagram D T su 20 ns T h 5 ns T su 20 ns T h 5 ns Clk Q T w 20 ns T plh C» Q 27 ns 5 ns T plh D» Q 27 ns 5 ns T phl D» Q 6 ns 7 ns T phl C» Q 25 ns 4 ns 20 Robert Dick Advanced Digital Logic Design
22 Introduction Reset/set latches Clocking conventions D flip-flop FF timing specifications Minimum clock width, T W Usually period / 2 Low to high propagation delay, P LH High to low propagation delay, P HL 2 Robert Dick Advanced Digital Logic Design
23 FF timing specifications Introduction Reset/set latches Clocking conventions D flip-flop Example, positive (rising) edge-triggered flip-flop timing diagram D T su 20 ns T h 5 ns T su 20 ns T h 5 ns Clk T w 25 ns Q T plh 25 ns 3 ns T phl 40 ns 25 ns 22 Robert Dick Advanced Digital Logic Design
24 RS latch states Introduction Reset/set latches Clocking conventions D flip-flop S R Q + Q + Notes 0 0 Q Q unstable 23 Robert Dick Advanced Digital Logic Design
25 JK latch Introduction Reset/set latches Clocking conventions D flip-flop R S latch Use output feedback to ensure that RS Q + = Q K + Q J 24 Robert Dick Advanced Digital Logic Design
26 JK latch Introduction Reset/set latches Clocking conventions D flip-flop J K Q Q hold reset set toggle 25 Robert Dick Advanced Digital Logic Design
27 JK race Introduction Reset/set latches Clocking conventions D flip-flop Set Reset 00 Toggle Race Condition 26 Robert Dick Advanced Digital Logic Design
28 Section outline Introduction Reset/set latches Clocking conventions D flip-flop. Introduction Reset/set latches Clocking conventions D flip-flop 27 Robert Dick Advanced Digital Logic Design
29 Falling edge-triggered D flip-flop Introduction Reset/set latches Clocking conventions D flip-flop Use two stages of latches When clock is high First stage samples input w.o. changing second stage Second stage holds value When clock goes low First stage holds value and sets or resets second stage Second stage transmits first stage Q + = D One of the most commonly used flip-flops 28 Robert Dick Advanced Digital Logic Design
30 Falling edge-triggered D flip-flop Introduction Reset/set latches Clocking conventions D flip-flop D D Clk= = 0 R Q S Q 0 D D Clock high 29 Robert Dick Advanced Digital Logic Design
31 Falling edge-triggered D flip-flop Introduction Reset/set latches Clocking conventions D flip-flop D D 0 Holds D when clock goes low Clk== R Q S Q 0 D D Holds D when clock goes low Clock switching Inputs sampled on falling edge, outputs change after falling edge 30 Robert Dick Advanced Digital Logic Design
32 Falling edge-triggered D flip-flop Introduction Reset/set latches Clocking conventions D flip-flop D D Clk= = 0 D R Q S Q D? 0 Clock low 3 Robert Dick Advanced Digital Logic Design
33 Edge triggered timing Introduction Reset/set latches Clocking conventions D flip-flop 00 Positive edge t riggered FF Negative edge t riggered FF 32 Robert Dick Advanced Digital Logic Design
34 RS clocked latch Introduction Reset/set latches Clocking conventions D flip-flop Storage element in narrow width clocked systems Dangerous Fundamental building block of many flip-flop types 33 Robert Dick Advanced Digital Logic Design
35 JK flip-flop Introduction Reset/set latches Clocking conventions D flip-flop Versatile building block Building block for D and T flip-flops Has two inputs resulting in increased wiring complexity Don t use master/slave JK flip-flops Ones or zeros catching Edge-triggered varieties exist 34 Robert Dick Advanced Digital Logic Design
36 D flip-flop Introduction Reset/set latches Clocking conventions D flip-flop Minimizes input wiring Simple to use Common choice for basic memory elements in sequential circuits 35 Robert Dick Advanced Digital Logic Design
37 Toggle (T) flip-flops Introduction Reset/set latches Clocking conventions D flip-flop State changes each clock tick Useful for building counters Can be implemented with other flip-flops JK with inputs high D with XOR feedback 36 Robert Dick Advanced Digital Logic Design
38 Asynchronous inputs Introduction Reset/set latches Clocking conventions D flip-flop How can a circuit with numerous distributed edge-triggered flip-flops be put into a known state Could devise some sequence of input events to bring the machine into a known state Complicated Slow Not necessarily possible, given trap states Can also use sequential elements with additional asynchronous reset and/or set inputs 37 Robert Dick Advanced Digital Logic Design
39 Latch and flip-flop equations Introduction Reset/set latches Clocking conventions D flip-flop RS D Q + = S + R Q Q + = D 38 Robert Dick Advanced Digital Logic Design
40 Latch and flip-flop equations Introduction Reset/set latches Clocking conventions D flip-flop JK T Q + = J Q + K Q Q + = T Q 39 Robert Dick Advanced Digital Logic Design
41 Outline Robert Dick Advanced Digital Logic Design
42 Section outline 2. 4 Robert Dick Advanced Digital Logic Design
43 Sequential FSM design example We ll walk through the design of an example finite state machine (FSM) Some of the stages will be covered in more detail in later lectures I want you to have a high-level understanding of our overall goal before covering every detail of FSM synthesis 42 Robert Dick Advanced Digital Logic Design
44 Naturally express control However, no simple direct HW implementation We want to get to sequential logic Need to go though other stages first 43 Robert Dick Advanced Digital Logic Design
45 Can be expressed with regular expressions, examples Accept the empty string, Accept nothing, Accept 0 or, (0 + ) Accept anything starting with and one or more 0 and ending with 0 or 0, 0 + (0 + 0) Accept anything starting with zero or more 000 or and ending with, (000 + ) 44 Robert Dick Advanced Digital Logic Design
46 Section outline Robert Dick Advanced Digital Logic Design
47 (NFA) State graph Multiple states can be active at the same time Some states Accept The automata accepts if any accepting states are active 46 Robert Dick Advanced Digital Logic Design
48 NFA ( )() + 47 Robert Dick Advanced Digital Logic Design
49 NFA ( )() + a 0 b c d e 0 f g h i j k 47 Robert Dick Advanced Digital Logic Design
50 NFA ( )() + a 0 b c d e 0 f g h i j k 47 Robert Dick Advanced Digital Logic Design
51 NFA ( )() + a 0 b c d e 0 f g h i j k 47 Robert Dick Advanced Digital Logic Design
52 NFA ( )() + a 0 b c d e 0 f g h i j k 0 47 Robert Dick Advanced Digital Logic Design
53 NFA ( )() + a 0 b c d e 0 f g h i j k 0 47 Robert Dick Advanced Digital Logic Design
54 NFA ( )() + a 0 b c d e 0 f g h i j k 0 47 Robert Dick Advanced Digital Logic Design
55 NFA ( )() + a 0 b c d e 0 f g h i j k 0 47 Robert Dick Advanced Digital Logic Design
56 NFA ( )() + a 0 b c d e 0 f g h i j k 0 47 Robert Dick Advanced Digital Logic Design
57 NFA ( )() + a 0 b c d e 0 f g h i j k 0 47 Robert Dick Advanced Digital Logic Design
58 Section outline Robert Dick Advanced Digital Logic Design
59 (DFA) NFAs require multiple states to be simultaneously active Can t represent this with conventional logic state variables Need to convert to deterministic representation 49 Robert Dick Advanced Digital Logic Design
60 DFA ( )() + 50 Robert Dick Advanced Digital Logic Design
61 DFA ( )() + a b f i abfi 50 Robert Dick Advanced Digital Logic Design
62 DFA ( )() + a b f c i j abfi cj 50 Robert Dick Advanced Digital Logic Design
63 DFA ( )() + a b f 0 c d i j 0 d abfi cj 50 Robert Dick Advanced Digital Logic Design
64 DFA ( )() + a b f 0 c d e i j 0 d ei abfi cj 50 Robert Dick Advanced Digital Logic Design
65 DFA ( )() + a b f 0 c d e i j abfi cj d ei 0 j 50 Robert Dick Advanced Digital Logic Design
66 DFA ( )() + a b f 0 c d e i j k abfi cj d ei 0 ki j 50 Robert Dick Advanced Digital Logic Design
67 DFA ( )() + a b f c 0 0 g d e i j k abfi 0 cj g d ei 0 ki j 50 Robert Dick Advanced Digital Logic Design
68 DFA ( )() + a b f c 0 0 g d h e i j k abfi 0 cj g d ei 0 ki j hi 50 Robert Dick Advanced Digital Logic Design
69 DFA ( )() + a b f c 0 0 g d h e i j k abfi 0 cj g d ei 0 ki j hi 50 Robert Dick Advanced Digital Logic Design
70 DFA to more explicit FSM ( )() + abfi 0 cj g 0 d ki hi ei j 5 Robert Dick Advanced Digital Logic Design
71 DFA to more explicit FSM ( )() + z abfi 0 cj g 0 d ki hi ei j 5 Robert Dick Advanced Digital Logic Design
72 DFA to more explicit FSM ( )() + 0 z abfi 0 cj g 0 d ki hi ei j 5 Robert Dick Advanced Digital Logic Design
73 DFA to more explicit FSM ( )() + 0 z abfi cj g d ki hi 0 ei j 0 5 Robert Dick Advanced Digital Logic Design
74 Section outline Robert Dick Advanced Digital Logic Design
75 DFA to FSM DFA may only accept or reject Simple to convert Moore FSM Add explicit output values to states 53 Robert Dick Advanced Digital Logic Design
76 Moore block diagram outputs combinational logic sequential elements feedback combinational logic inputs 54 Robert Dick Advanced Digital Logic Design
77 Mealy block diagram sequential elements outputs feedback combinational logic inputs 55 Robert Dick Advanced Digital Logic Design
78 Moore FSMs 0 A/0 B/ D/ C/0 56 Robert Dick Advanced Digital Logic Design
79 Section outline Robert Dick Advanced Digital Logic Design
80 Introduction to state reduction s + s 0 Q A A B 0 B C B 0 C A B 0 D A A 58 Robert Dick Advanced Digital Logic Design
81 Introduction to state reduction s + s 0 Q A A B 0 B C B 0 C A B 0 D A A 58 Robert Dick Advanced Digital Logic Design
82 Introduction to state reduction s + s 0 q AC AC B 0 B AC B 0 D AC AC 59 Robert Dick Advanced Digital Logic Design
83 Introduction to state reduction s + s 0 q AC AC B 0 B AC B 0 D AC AC 59 Robert Dick Advanced Digital Logic Design
84 Introduction to state reduction s + s 0 q AC AC B 0 B AC B 0 D AC AC 59 Robert Dick Advanced Digital Logic Design
85 State assignment s + s 0 q ABC ABC ABC 0 D ABC ABC 60 Robert Dick Advanced Digital Logic Design
86 State assignment s + s 0 q ABC ABC ABC 0 D ABC ABC Only two adjacent states, state assignment is trivial 60 Robert Dick Advanced Digital Logic Design
87 State assignment s + s 0 q ABC ABC ABC 0 D ABC ABC Only two adjacent states, state assignment is trivial However, good to consider output, q 60 Robert Dick Advanced Digital Logic Design
88 State variable functions s + s 0 q Robert Dick Advanced Digital Logic Design
89 State variable functions s + s 0 q s + (s) = 0 6 Robert Dick Advanced Digital Logic Design
90 State variable functions s + s 0 q s + (s) = 0 q(s) = s 6 Robert Dick Advanced Digital Logic Design
91 Mealy FSMs /0 A /X B 0/0 D 0/0 0/ /0 0/ C / 62 Robert Dick Advanced Digital Logic Design
92 Mealy tabular form s + /q s 0 A D/0 B/X B C/ B/0 C A/0 B/ D C/ C/0 63 Robert Dick Advanced Digital Logic Design
93 Mealy to Moore conversion /0 A /X B 0/0 D 0/ 0/0 / 0/ C /0 A/0 B/X B/ D/0 0 C/ 0 B/ 0 C/0 64 Robert Dick Advanced Digital Logic Design
94 State variable combinational synthesis D flip flops q plain old combinational logic 65 Robert Dick Advanced Digital Logic Design
95 State variable combinational synthesis clock D flip flops q plain old combinational logic Separate sequential and combinational portions of circuit 65 Robert Dick Advanced Digital Logic Design
96 State variable combinational synthesis clock D flip flops q plain old combinational logic Separate sequential and combinational portions of circuit Conduct standard logic synthesis 65 Robert Dick Advanced Digital Logic Design
97 FSM design summary Specify requirements in natural form regular expression or NFA Converting from NFA to DFA is straightforward Converting from DFA to FSM is straightforward Minimize the number of states using compatible states, class sets, and binate covering Assign values to states to minimize logic complexity Allow only adjacent or path transitions for asynchronous machines Optimize implementation of state and output functions 66 Robert Dick Advanced Digital Logic Design
98 Outline Robert Dick Advanced Digital Logic Design
99 Recommended reading M. Morris Mano and Charles R. Kime. Logic and Computer Design Fundamentals. Prentice-Hall, NJ, third edition, 2004 Chapter 7 Chapter 6 68 Robert Dick Advanced Digital Logic Design
100 Video controller repair lab Design a finite state machine based on an English problem specification The design problem isn t very difficult Going from a real-world problem to a formal representation may be difficult Be careful not to use too many state variables!!! Could easily turn it from a 6 hour lab to a 2 hour lab 69 Robert Dick Advanced Digital Logic Design
101 Next lecture More detail and examples on FSM design and optimization 70 Robert Dick Advanced Digital Logic Design
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