6.S084 Tutorial Problems L05 Sequential Circuits

Transcription

1 Preamble: Sequential Logic Timing 6.S084 Tutorial Problems L05 Sequential Circuits In Lecture 5 we saw that for D flip-flops to work correctly, the flip-flop s input should be stable around the rising edge of the clock. We will now formalize this requirement and explore its implications on the timing of sequential circuits through several problems. 1. D flip-flop timing constraints: For a D flip-flop to work correctly, the D input must be a valid and stable digital value for at least t!"#$% (setup time) before the rising edge of the clock, and for at least t!"#$ (hold time) after the rising edge of the clock, as shown in the diagram below. The setup time guarantees that the value of D has propagated through the relevant internal feedback path of the D flip-flop before the rising edge of the clock (specifically, the feedback path of the first D latch, which switches from pass to hold when the clock goes from 0 to 1). Similarly, the hold time guarantees that the relevant feedback paths have stabilized before D is allowed to change. Violating the setup or hold times may cause metastability: the flip-flop may register an incorrect value, and may have an undefined output for an unbounded period of time. As shown in the timing diagram, a flip-flop s output Q is guaranteed to be a valid and stable digital value t!" (propagation delay) after the rising edge of the clock. Like the propagation delay of combinational circuits, the propagation delay is an upper bound. Unlike for combinational circuits, the propagation delay for flip-flops is defined from the rising clock edge to the output, not from any input to the output. 2. Minimum clock cycle time and meeting the setup-time constraint: Consider the circuit below, where FF1 and FF2 are D flip-flops that use the same clock and are connected through some combinational logic CL. This models a generic path between two flip-flops. 6.S084 Tutorial Problems - 1 of 7 - L05 Sequential Circuits

2 Assume we define the following parameters, shown in the timing diagram above: t!",!!! is FF1 s propagation delay. t!",!" is CL s propagation delay. t!"#$%,!!! is FF2 s setup time. t!"# is the clock period, i.e., the time between two consecutive rising edges. Then, to meet FF2 s setup time, t!"! t!",!!! + t!",!" + t!"#$%,!!! The timing diagram shows why. The value at FF2 s input will be stable t!",!!! + t!",!" after the rising edge of the clock. This time must be at least t!"#$%,!!! before the next rising edge of the clock. The time between rising edges is t!"#, so t!",!!! + t!",!" t!"# t!"#$%,!!!. This is equivalent to the above inequality. For our sequential system to work correctly, this inequality must hold across all register-toregister paths. Therefore, the longest combinational logic path between any two registers imposes a lower bound on the clock period, or equivalently, an upper bound on the clock frequency, f!"# = 1/t!"#, determining how many operations we can perform per second. The key takeaway is that, to design fast digital systems, it is important to avoid long logic paths between registers. For example, modern processors have between 8 to 16 levels of gates between any pair of registers. Synthesis tools can determine the maximum clock frequency automatically, and will try to improve it by optimizing the longest paths, but there is a limit to what tools can achieve. Later in the course we will study design strategies to achieve a high clock frequency. 3. Contamination delays and meeting the hold-time constraint: Analyzing how to meet the hold-time constraint requires that we specify a lower bound on the delay of our combinational logic and registers. Specifically, the contamination delay of a combinational circuit is the minimum time that may elapse between one of its inputs becoming invalid (i.e., not a digital 0 or 1) and one of its outputs becoming invalid. In other words, the contamination delay is a lower bound on how long the circuit s outputs will remain stable after the inputs start changing. A flip-flop s contamination delay is defined similarly, as the minimum time between the rising edge of the clock and the output becoming invalid. Similarly to our previous derivation, assume we define the following parameters: t!",!!! is FF1 s contamination delay. t!",!" is CL s contamination delay. t!"#$,!!! is FF2 s hold time. Then, to meet FF2 s hold time, t!",!!! + t!",!" t!"#$,!!! Contamination delays are often smaller than hold times, so if there is little or no logic between two registers, we may need to add some logic (e.g., a buffer or chain or buffers) to meet the holdtime constraint. In practice tools take care of this, so you will not have to worry about it when designing sequential circuits. Note how the clock period does not show up in this inequality. Therefore, if the hold-time constraint is violated, the circuit will not work correctly at any frequency. 6.S084 Tutorial Problems - 2 of 7 - L05 Sequential Circuits

3 Problem 1. Consider the following sequential logic circuit. It consists of one input IN, a 2-bit register that stores the current state, and some combinational logic that determines the state (next value to load into the register) based on the current state and the input IN. (A) Using the timing specifications shown below for the XOR and DREG components, determine the shortest clock period, t CLK, that will allow the circuit to operate correctly or write NONE if no choice for t CLK will allow the circuit to operate correctly and briefly explain why. Component t CD t PD t SETUP t HOLD XOR2 0.15ns 2.1ns DREG 0.1ns 1.6ns 0.4ns 0.2ns Minimum value for t CLK (ns): or explain why none exists (B) Using the same timing specifications as in (A), determine the setup and hold times for IN with respect to the rising edge of CLK. t SETUP for IN with respect to CLK (ns): t HOLD for IN with respect to CLK (ns): (C) One of the engineers on the team suggests using a new, faster XOR2 gate with t CD = 0.05ns and t PD = 0.7ns. Determine a new minimum value for t CLK or write NONE and explain why no such value exists. Minimum value for t CLK (ns): or explain why none exists 6.S084 Tutorial Problems - 3 of 7 - L05 Sequential Circuits

4 Problem 2. Consider the following sequential logic circuit. It consists of three D registers, three different pieces of combinational logic (CL1, CL2, and CL3), one input IN, and one output OUT. The propagation delay, contamination delay, and setup time of the registers are all the same and are specified below each register. The hold time for the registers is NOT the same and is specified in bold below each register. The timing specification for each combinational logic block is shown below that logic. (A) (1 point) What is the smallest value for the t CD of CL2 that will allow all the registers in the circuit to operate correctly? Smallest value for t CD of CL2 (ns): (B) (2 points) What is the smallest value for the period of CLK (i.e., t CLK ) that will allow all the registers in the circuit to operate correctly? Smallest value for t CLK (ns): (C) (2 points) What are the smallest values for the setup and hold times for IN relative to the rising edge of CLK that will allow all the registers in the circuit to operate correctly? Setup time for IN (ns): Hold time for IN (ns): (D) (2 points) What are the propagation delay and contamination delay of the output, OUT, of this circuit relative to the rising edge of the clock? t PD for OUT (ns): t CD for OUT (ns): 6.S084 Tutorial Problems - 4 of 7 - L05 Sequential Circuits

5 Problem 3. Consider the following sequential logic circuit. The timing specifications are shown below each component. Note that the two registers do NOT have the same specifications. (A) What are the smallest values for the setup and hold times for IN relative to the rising edge of CLK that will allow both registers in the circuit to operate correctly? Setup time for IN (ns): Hold time for IN (ns): (B) What is the smallest value for the period of CLK (i.e., tclk) that will allow both registers in the circuit to operate correctly? Smallest value for tclk (ns): (C) What is the smallest value for the tcd of R1 that will allow both registers in the circuit to operate correctly? Smallest value for tcd of R1 (ns): (D) Suppose two of these sequential circuits were connected in series, with the OUT signal of the first circuit connected to the IN signal of the second circuit. The same CLK signal is used for both circuits. Now what is the smallest value for the period of CLK (i.e., tclk) that will allow both registers in the circuit to operate correctly? Smallest value for tclk (ns): 6.S084 Tutorial Problems - 5 of 7 - L05 Sequential Circuits

6 Problem 4. Modify the following BSV module, which we saw in Lecture 5, so that it automatically increments its value each cycle. interface Counter; method Action inc; method Bit#(2) read; endinterface module modulocounter(counter); Reg#(Bit#(2)) cnt <- mkreg(0); method Action inc; cnt <= {cnt[1]^cnt[0], ~cnt[0]}; endmethod method Bit#(2) read; return cnt; endmethod endmodule 6.S084 Tutorial Problems - 6 of 7 - L05 Sequential Circuits

7 Problem 5. Implement a BSV module that computes the n th Fibonacci number in n cycles: interface Fibonacci; // start is an Action since it will set the registers // to start the computation method Action start(bit#(5) n); // getresult is an ActionValue since it will both // return the results and change a register method ActionValue#(Bit#(32)) getresult; // busy and ready are just methods that we can call // to check the status method Bool busy; method Bool ready; endinterface module mkfibonacci(fibonacci); 6.S084 Tutorial Problems - 7 of 7 - L05 Sequential Circuits