PLD Synthesis Algorithms

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1 What to Synthesize PLD Synthesis Algorithms Professor Jason Cong Computer Science Department University of California, Los Angeles Los Angeles, CA Structured logic: Examples: datapath, register files, Best to be provided by FPGA vendors as libraries and functional generators Random logic: Examples: control circuits, finite state machines Good candidates to be synthesized by automatic tools 6/22/2001 DAC 2001 Tutorial: Jason Cong 1 6/22/2001 DAC 2001 Tutorial: Jason Cong 2

2 Programmable Logic Blocks (PLBs) in FPGAs Focus of This Talk Lookup-table based Altera APEX and FLEX devices Lucent Technologies ORCA devices Xilinx Virtex and XC4K devices MUX-based Actel ACT1 and ACT2 Quicklogic Eclips PLA-based (CPLD) Altera MAX7000 Cypress CY37000 and CY /22/2001 DAC 2001 Tutorial: Jason Cong 3 Synthesis for random logic Need high-degree of automation Much room for optimization Extensive research Synthesis for SRAM-based (LUT-based) FPGAs Has the largest share in the FPGA market Synthesis-friendly Reconfigurability provides many potential applications 6/22/2001 DAC 2001 Tutorial: Jason Cong 4

3 Formulation of LUT-Based Synthesis Problems Logic optimization (Network transformation) Transform the input network into another network that is more suitable for mapping into LUT networks Technology mapping (LUT covering) Cover the optimized network with LUTs for one or more objectives Logic Optimization Operations Example: decomposition structural : abcd = ((ab)c)d functional: f(a,b,c,d) = g (y1(a,b,c), y2(a,b,c), d) f y1 y2 g 6/22/2001 DAC 2001 Tutorial: Jason Cong 5 6/22/2001 DAC 2001 Tutorial: Jason Cong 6

4 Logic Optimization Operations (Cont d) Extraction f = ac + bc, g = ad + bd then f = ec, g = ed, e = (a+b) Substitution f = a+bc, h = bc then f = a + h Elimination f = a+bc, b = d+e, then f = a+cd+ce Critical path re-synthesis... Technology Mapping for K-LUT Cover the network using K-LUTs Duplication-free v.s. duplicated mapping (k = 3) original circuit duplication-free duplication 6/22/2001 DAC 2001 Tutorial: Jason Cong 7 6/22/2001 DAC 2001 Tutorial: Jason Cong 8

5 Outline Outline Architecture Early results ( ) Simple, homogeneous LUTS E.g. XC2K, Flex8K Heterogeneous FPGAs Embedded memory blocks Complex PLBs Million-gate FPGAs Field-programmable system-on-a-chip Recent advances ( ) New challenges ( ) 6/22/2001 DAC 2001 Tutorial: Jason Cong Homogeneous K-LUT mapping for depth, area min. Focus on combinational circuits Synthesis Heterogeneous FPGA mapping Mapping for EMBs Boolean matching Simultaneous mapping + retiming Layout-driven synthesis Use of IP blocks Synthesis for FPSOC 6/22/2001 DAC 2001 Tutorial: Jason Cong 10

6 Outline Architecture Heterogeneous FPGAs Million-gate FPGAs Heterogeneous FPGAs Million-gate FPGAs Simple, Simple, homogeneous homogeneous LUTS LUTS Embedded memory blocks Embedded memory blocks Field-programmable Field-programmable E.g. XC2K, Flex8K Complex PLBs PLBs system-on-a-chip Outline Architecture Simple, homogeneous LUTS E.g. XC2K, Flex8K Heterogeneous FPGAs Embedded memory blocks Complex PLBs Million-gate FPGAs Field-programmable system-on-a-chip Homogeneous K-LUT K-LUT mapping for depth, area area min. min. Focus on combinational circuits Focus on combinational circuits Synthesis Heterogeneous FPGA Heterogeneous FPGA Layout-driven synthesis mapping Use of Use IP of blocks IP Mapping for for EMBs EMBs Synthesis for Synthesis for FPSOC Boolean matching Simultaneous mapping + Simultaneous mapping retiming + retiming 6/22/2001 DAC 2001 Tutorial: Jason Cong Homogeneous K-LUT mapping for depth, area min. Focus on combinational circuits Synthesis Heterogeneous FPGA mapping Mapping for EMBs Boolean matching Simultaneous mapping + retiming Layout-driven synthesis Use of IP blocks Synthesis for FPSOC 6/22/2001 DAC 2001 Tutorial: Jason Cong 12

7 Outline Early Results: Depth Minimization Early results ( ) Developed for homogeneous LUTs Focus on combinational circuits Recent advances ( ) Optimal mapping for trees Chortle-d [Francis, Rose, Vranesic, ICCAD 91] Optimal mapping for general networks FlowMap [Cong&Ding, ICCAD 92] New challenges ( ) 6/22/2001 DAC 2001 Tutorial: Jason Cong 13 6/22/2001 DAC 2001 Tutorial: Jason Cong 14

8 Early Result: FlowMap Depth-optimal technology mapping [Cong&Ding, TCAD 94] BASIC APPROACH Compute a label for each node Label of a node represents the minimum possible depth of the node in any mapping solution Dynamic Programming Starting from PI nodes, compute node labels in topological order: compute the label of a node based on labels of its predecessors Labels of PO nodes give the depth of the optimal mapping solution. 6/22/2001 DAC 2001 Tutorial: Jason Cong 15 Cuts in a Network Given a cut (X, X) and a label l(v) on each node v Node-Cut size: n(x,x) = {v:(v,u) is cut} X K-feasible cut: n(x,x) < K X Height of a cut: h(x,x) = max{l(v) v X} t 6/22/2001 DAC 2001 Tutorial: Jason Cong 16 s

9 Label Computation in FlowMap Dynamic programming - compute each node label (optimal mapping depth) by computing a min-height K-feasible cut. Min-height K-feasible cut can be computed in O(Km) time using flow computation Primary inputs u w 1 2 v 2 infeasible cut, h = 0 K-feasible cut, h = 1 LUT input size K = 3 FlowMap Algorithm: Summary Phase1 : Label computation Process each node t in topological order starting from PIs: Compute minimum height K-feasible cut (Xt, Xt) in Nt; l(t) = h(xt, Xt) + 1; Phase 2: Generate necessary K-LUTs L = list of POs; WHILE L 0 DO remove a node t from L; LUT(t) = Xt; L = L {non-pi inputs to LUT(t)} END. Produce depth-optimal mapping for any K-bounded network in O(Kmn) time where m: # number of edges; n: # nodes in the network 6/22/2001 DAC 2001 Tutorial: Jason Cong 17 6/22/2001 DAC 2001 Tutorial: Jason Cong 18

10 Early Results: Area Minimization Optimal mapping for trees with bounded or unbounded fanins Chortle-crf [Francis, Rose, Vranesic, DAC 91] : Optimal mapping without logic duplication for general networks DF-Map [Cong&Ding, DAC 93] : NP-hard for general networks with possible logic duplication [Farrahi&Sarrafzadeh, TCAD 94] : 6/22/2001 DAC 2001 Tutorial: Jason Cong 19 Early Results Combined Synthesis with Mapping Extension of traditional logic optimization techniques + covering & functional decomposition MIS-pga and MIS-pga-delay [Murgai et. al., DAC 90, ICCAD91] Use of functional decomposition to generate a LUT network directly FGSyn [Lai, Pedram, Vrudula, DAC 93], IMODEC [Wurth, et al, DAC 95], BoolMap-D [Legl, et al, DAC 96] Mapping with Re-synthesis FlowSYN [Cong&Ding, ICCAD 93], ALTO [Huang, Jou, Shen,ICCAD 96] 6/22/2001 DAC 2001 Tutorial: Jason Cong 20

11 Outline Outline Architecture Simple, homogeneous LUTS E.g. XC2K, Flex8K Homogeneous K-LUT mapping for depth, area min. Focus on combinational circuits Synthesis Heterogeneous FPGAs Embedded memory blocks Complex PLBs Heterogeneous FPGA mapping Mapping for EMBs Boolean matching Simultaneous mapping + retiming Million-gate FPGAs Field-programmable system-on-a-chip Layout-driven synthesis Use of IP blocks Synthesis for FPSOC 6/22/2001 DAC 2001 Tutorial: Jason Cong 21 Early results Recent advances Optimization and mapping for sequential circuits Synthesis for heterogeneous FPGAs Synthesis for FPGAs with embedded memory blocks Use of Boolean matching instead of pattern matching Combined decomposition and mapping UCLA RASP FPGA synthesis system New challenges 6/22/2001 DAC 2001 Tutorial: Jason Cong 22

12 Direct Optimization and Mapping for Sequential Circuits Traditional approaches Assuming the positions of FFs are fixed Mapping each combinational subcircuit separately The optimal solutions for all subcircuits may not lead to the optimal solution of the entire circuit Difficulties and Solutions Difficulties: When to retime? Before mapping? -- delay is un-known for retiming After mapping? -- FF positions are fixed during mapping How to compute an equivalent initial state? Solutions: 3-LUT 3-LUT Simultaneous mapping with retiming [Pan&Liu, DAC 96] [Cong&Wu, ICCD 96] Optimal mapping + forward retiming [Cong&Wu, DAC 98] original circuit F = 2 without retiming Φ = 1 with retiming 6/22/2001 DAC 2001 Tutorial: Jason Cong 23 6/22/2001 DAC 2001 Tutorial: Jason Cong 24

13 Simultaneous Mapping with Retiming Key idea -- expanded circuit a DAG rooted at a node and, every path from a node to the root has the same #FFs Usage: to form all possible LUTs under retiming b a c original circuit a b c 3-LUT 6/22/2001 DAC 2001 Tutorial: Jason Cong 25 a0 1 b c 2 a1 0 b c1 0 a Simultaneous Mapping + Retiming (Cont d) Polynomial-time optimal algorithm for mapping + retiming First proposed in SeqMapII [Pan&Liu, DAC 96] Significant speed-up (over 2000x) achieved by TurboMap [Cong&Wu, ICCD 96 ] Automatic pipelining with use of re-synthesis to reduce max. loop s delay-to-register ratio TurboSYN [Cong&Wu, DAC 97] 6/22/2001 DAC 2001 Tutorial: Jason Cong 26

14 Experimental Results: Mapping + Retiming + Pipelining Experimental Results: Mapping + Retiming + Pipelining (Cont d) 16 MCNC FSMs and ISCAS Sequential Benchmarks with 30~10,000 simple gates 16 MCNC FSMs and ISCAS Sequential Benchmarks with 30~10,000 simple gates TurboSYN: resynthesis+retiming+pip elining TurboMap: mapping+retiming FlowMap+retiming:separa te mapping with retiming TurboSYN: resynthesis+retiming+pip elining TurboMap: mapping+retiming FlowMap+retiming: separate mapping with retiming avg. Clock Period avg. #LUT avg. #Flipflop 6/22/2001 DAC 2001 Tutorial: Jason Cong 27 6/22/2001 DAC 2001 Tutorial: Jason Cong 28

15 Retiming with Initial States Many sequential circuit have initial states Retiming will change the initial state! Equivalent initial state computation for (backward) retiming is NP-hard i j k f(x) guarantee init-state move forward (FRT) y = f(x) f(x) y move backward (BRT) exists X, f(x)=y? NP-complete??? f(x) Conventional Approaches no original circuit compute a retiming can find an equivalent init-state? yes finish Initial-state computation for a given retiming is NP-hard Iteration may not find a feasible retiming solution 6/22/2001 DAC 2001 Tutorial: Jason Cong 29 6/22/2001 DAC 2001 Tutorial: Jason Cong 30

16 Optimal Mapping with Forward Retiming Optimal mapping with forward retiming (FRT) in polynomial time => guarantee initial state computation TurboMap-frt [Cong&Wu, DAC 98] Experimental Results of Optimal Mapping with Forward Retiming 18 Benchmarks with 30~10,000 simple gates 10 out 18 TurboMap solutions cannot compute initstates 7.0 New flow for retiming: Step 1: move FFs backward as much as possible create large freedom for mapping+frt Step 2: optimal mapping+frt clock period min. with guaranteed equivalent initial states TurboMap-frt: mapping+forward retiming TurboMap: mapping+retiming FlowMap-frt: separate mapping with forward retiming 6/22/2001 DAC 2001 Tutorial: Jason Cong 31 avg. Clock Period 6/22/2001 DAC 2001 Tutorial: Jason Cong 32

17 Experimental Results of Optimal Mapping with Forward Retiming 18 Benchmarks with 30~10,000 simple gates 10 out 18 TurboMap solutions cannot compute init-states TurboMap-frt: mapping+forward retiming TurboMap: mapping+retiming FlowMap-frt: separate mapping with forward retiming Technology Mapping for FPGAs with Heterogeneous LUTS Almost all recent FPGA architectures support heterogeneous LUTs One-size fits all is not good enough Examples Xilinx XC CLB = 2 x 4-LUTs = 1 x 5-LUT Lucent ORCA2C 1 PFU = 4 x 4-LUTs = 2 x 5-LUTs = 1 x 6-LUT avg. #5-LUTs avg. #Flipflops 6/22/2001 DAC 2001 Tutorial: Jason Cong 33 6/22/2001 DAC 2001 Tutorial: Jason Cong 34

18 XC4000 Block Diagram ORCA2C Block Diagram 1 PFU = 42 1 x 4-LUTs 5-LUTs 6-LUT 1 CLB = 2 x 4-LUTs = 1 x 5-LUT 6/22/2001 DAC 2001 Tutorial: Jason Cong 35 6/22/2001 DAC 2001 Tutorial: Jason Cong 36

19 Problem Formulation Mapping for Heterogeneous FPGAs Problem Heterogeneous LUTs have different delays and areas Two types of heterogeneous LUT-based FPGAs Fully configurable, no fixed ratio between different types of LUTs Fixed combination of several different LUTs in a PLB (discussed later using Boolean matching) Objective: Delay or area minimization 6/22/2001 DAC 2001 Tutorial: Jason Cong 37 Solutions Compute multiple cuts at each node in the network network-flow computation cut enumeration Select the most appropriate LUT implementation Depth minimization HeteroMap [Cong&Xu, DAC 98]: Polynomial-time delayoptimal for general networks Area minimization Optimal for trees [Korupolu, Lee, Wong, DAC 98] Heuristic for general networks [He&Rose, FPGA 94] 6/22/2001 DAC 2001 Tutorial: Jason Cong 38

20 Heterogeneous v.s. Homogeneous Mapping XC4000 Comparison Comparison Ratio Ratio Delay(4-LUT) : Delay(5-LUT) = 1 : 1.5 Comparison Comparison between between FlowMap FlowMap and and HeteroMap HeteroMap on on XC4000 XC4000 Series Series FPGAs FPGAs -19% Mapping- Mapping- Delay Delay PostLayout- PostLayout- Delay Delay -7% +2% [Cong&Xu, DAC 98] #PLB #PLB FlowMap(5) FlowMap(5) HeteroMap(5,4) HeteroMap(5,4) 6/22/2001 DAC 2001 Tutorial: Jason Cong 39 Comparison between Homogeneous and Heterogeneous FPGAs Delay(3-LUT) : Delay(4-LUT) : Delay(5-LUT) : Delay(6-LUT) = 1 : 1.3 : 1.7 : 2 Comparison Comparison Ratio Ratio Performance Comparison between Homogeneous and Heterogeneous FPGAs Mapping-Delay Mapping-Delay MemoryCell-Area 3-LUT-FPGA 3-LUT-FPGA 4-LUT-FPGA 4-LUT-FPGA 5-LUT-FPGA 5-LUT-FPGA 6-LUT-FPGA 6-LUT-FPGA LUT LUT- HeteroFPGA HeteroFPGA 6/22/2001 DAC 2001 Tutorial: Jason Cong 40

21 Mapping for FPGAs with Embedded Memory Blocks Embedded memory blocks (EMBs) On-chip memories Logic functions FLEX10K Device Block Diagram 6/22/2001 DAC 2001 Tutorial: Jason Cong 41 Problem Formulation Limited number of EMBs in one chip Configuration flexibility of EMBs E.g. Each EMB in FLEX10K has 2K cells and can be configured to 2Kx1, 1Kx2, 512x4, 256x8 memory Unmapped Circuit Minimize delay and/or area LUT EMB LUT LUT LUT EMB Mapped Circuit 6/22/2001 DAC 2001 Tutorial: Jason Cong 42

22 Solutions EMB_Pack [Cong&Xu, FPGA 98] Use EMBs to minimize the circuit area Maintain the circuit delay Post-mapping processing and pre-mapping processing Smap [Wilton, FPGA 98] Use EMBs to minimize the circuit area Post-mapping processing Results of EMB_Pack Comparison Comparison Ratio Ratio Comparison between CutMap [Cong&Hwang, FPGA'95] and and CutMap Followed by by EMB_Pack on on MCNC Benchmarks on on FLEX10K Device Family % CutMap CutMap Followed by by EMB_Pack #LUT #LUT Layout Layout Delay Delay 6/22/2001 DAC 2001 Tutorial: Jason Cong 43 6/22/2001 DAC 2001 Tutorial: Jason Cong 44

23 Boolean Matching for Complex PLBs Direct Mapping to Programmable Logic Blocks (PLBs) PLB: Programmable Logic Block Example: given a 9-input function f of f = x 1 x 2 + x 2 x 3 + x 2 x 3 x 8 + x 5 x 6 a + x 5 x 7 a + x 4 x 5 x 6 x 7 + x 5 x 6 x 7 a + x 5 x 6 x 7 a a = x 0 x 4 + x 0 x 4 Target: Xilinx XC4K FPGAs LUT covering + packing: 4 CLBs Boolean matching: 1 CLB Advantage: significant area & delay reduction F x G XC4K H f(x) Benefits May have significant area and delay reduction Difficulties : Need to perform Boolean matching Given an arbitrary function f and a PLB, determine if PLB can implement f. 6/22/2001 DAC 2001 Tutorial: Jason Cong 45 6/22/2001 DAC 2001 Tutorial: Jason Cong 46

24 Example: Boolean Matching for XC4K CLB Boolean Matching Results -- for MCNC benchmarks Experiment: enumerate all K-input functions Functional decomposition f (X) = H ( F (X1), G (X2) ), f(x) = H ( F (X1), G (X2), x ), f(x) = H (F(X1,x), G(X2), x ), f(x) = H (F(X1,x), G(X2,x), x ). x F G XC4K H f(x) Circuits 5-input 6-input 7-input 9sym C alu alu des XC4K CLB can implement Conditions 98% of 6-input functions F and G input sizes 4 88% of 7-input functions 6/22/2001 DAC 2001 Tutorial: Jason Cong 47 6/22/2001 DAC 2001 Tutorial: Jason Cong 48

25 Application to Technology Mapping (for XC4000 and XC5200 FPGAs) Application to Architecture Evaluation (logic capability v.s. silicon area) Comparing to LUT mapping results, the PLB mapping obtains for XC5200 FPGAs 7% depth reduction F H1 XC4K CLB 40 Memory cells ( > 5 inputs) G H 3,4,5 F G S XC5K Memory cells ( > 4 or 5 inputs) 13% area reduction for XC4000 FPGAs 17% depth reduction 3% area increase XC4K(0,4,3) 24 Memory cells ( > 4 inputs) G H 3,4 F G H XC4K(3/4,4,2) 28,36 Memory cells ( > 4 inputs) 6/22/2001 DAC 2001 Tutorial: Jason Cong 49 6/22/2001 DAC 2001 Tutorial: Jason Cong 50

26 Architecture Evaluation (for wide function implementation) # implementable functions / # memory cells for each type of PLB Combined Decomposition with Mapping a b c d e f g a b c d e f g input funcs 6-input funcs B.2 (4,4,MUX) (0,4,3) XC4K XC5K XC4K (3,4,2) (4,4,2) XC4K (a) Initial 5-bounded network (b) Best mapping after dmig: depth 3, area 5 6/22/2001 DAC 2001 Tutorial: Jason Cong 51 6/22/2001 DAC 2001 Tutorial: Jason Cong 52

27 Impact of Decomposition Problem Formulation a b c d e f g a b c d e f g Structural Gate Decomposition in a W- bounded network for K-LUT mapping (W- SGD/K) Goal: find a decomposition with minimum depth after mapping The W-SGD/K problem is NP-hard for W K 5 [Cong&Hwang, DAC96] (a) Initial 5-bounded network (c) Optimal decomposition: depth 2, area 3 6/22/2001 DAC 2001 Tutorial: Jason Cong 53 6/22/2001 DAC 2001 Tutorial: Jason Cong 54

28 Available Solutions Mapping Graph Definition Simultaneous decomposition and mapping for trees (Chortle-crf or Chortle-d algorithms) Combines bin-packing with flow computation (for computing the min height cuts): DOGMA [Cong&Hwang, DAC 96] Use a mapping graph to encode all possible (or a large class of) decompositions, and compute a mapping solution on it: SLDmap [Chen&Cong, FPGA 01] A modified AND2/INV network to encode a set of circuit structures in a single graph [Lehman et al. ICCAD95] choice nodes (logical equivalence) ugates (two choice nodes and fanins) cycles Reduction unique choice node unique INV and AND2 nodes 6/22/2001 DAC 2001 Tutorial: Jason Cong 55 6/22/2001 DAC 2001 Tutorial: Jason Cong 56

29 Mapping Graph Example Mapping Graph Example A B A B C C D 3 Z D 3 Z A B C a b d e f g h a b d e f g h D c c 6/22/2001 DAC 2001 Tutorial: Jason Cong 57 6/22/2001 DAC 2001 Tutorial: Jason Cong 58

30 Mapping Graph Example Mapping Graph Example A B C D 1 2 3i 3 a b 4 d e f g h Z A B C D 1 2 3i a b 4 d e f g h Z 6/22/2001 DAC 2001 Tutorial: Jason Cong 59 6/22/2001 DAC 2001 Tutorial: Jason Cong 60

31 Mapping Graph Example Overview of SLDMap [Chen&Cong, FPGA 01] A B Initial W-bounded network generation Mapping graph construction C Depth optimal labeling D 3i Label relaxation and area minimization a d f 7 8g 9h Z Decomposition selection Fixed decomposition mapping b e 6/22/2001 DAC 2001 Tutorial: Jason Cong 61 6/22/2001 DAC 2001 Tutorial: Jason Cong 62

32 Experimental Flow Depth/Area Comparison MCNC Circuit Set, UCLA RASP package, CUDD dmig [chen et. al, IEEE Design & Test 92] dogma [cong, DAC96] Initial W-bounded network dmig dogma sldmap cutmap greedy_pack Xilinx Foundation 3.1 P&R depth area dmig dogma sldmap 6/22/2001 DAC 2001 Tutorial: Jason Cong 63 6/22/2001 DAC 2001 Tutorial: Jason Cong 64

33 Post-layout Delay Outline 100 ns k2(v) 9sym(S) i3(v) x1(s) C499(3K) dogma sldmap V:Vertex S:Spartan 3K:XC3K 6/22/2001 DAC 2001 Tutorial: Jason Cong 65 Early results Recent advances Synthesis and optimization for sequential circuits Synthesis for heterogeneous FPGAs Synthesis for FPGAs with embedded memory blocks Use of Boolean matching instead of pattern matching Combined decomposition with mapping UCLA RASP FPGA synthesis system New challenges 6/22/2001 DAC 2001 Tutorial: Jason Cong 66

34 UCLA RASP Synthesis System Objective 1: A Flexible and Efficient FPGA Synthesis Engine EDIF netlist HDL design Internal netlist LUT Mapping Engine LUT netlist Placement Routing Vendor Specific netlist Xilinx, Altera, ORCA PLB Mapping Engine Chip Programming Information Delay Optimal Mapping FlowMap/HeteroMap FlowSYN TurboMap TurboSYN PLB Mapping PDDmap PDDSYN Match-4K/3K EAB-pack Delay/Area Trade-off FlowMap-r CutMap CutSyn Area Optimal Mapping DF-map CutMap-E MarkMap Gate Decomposition for Mapping DMIG DOGMA SLDmap 6/22/2001 DAC 2001 Tutorial: Jason Cong 67 6/22/2001 DAC 2001 Tutorial: Jason Cong 68

35 Objective 2: FPGA Architecture Evaluation Outline Architecture Simple, homogeneous LUTS E.g. XC2K, Flex8K Heterogeneous FPGAs Embedded memory blocks Complex PLBs Million-gate FPGAs Field-programmable system-on-a-chip Homogeneous K-LUT mapping for depth, area min. Focus on combinational circuits Heterogeneous FPGA mapping Mapping for EMBs Boolean matching Simultaneous mapping + retiming Layout-driven synthesis Use of IP blocks Synthesis for FPSOC 6/22/2001 DAC 2001 Tutorial: Jason Cong 69 Synthesis 6/22/2001 DAC 2001 Tutorial: Jason Cong 70

36 Outline Early results Recent advances New challenges Integration of synthesis and layout Field-programmable system-on-a-chip Logic vs. Interconnect Delays Example: Altera FPGA: (EPF8282A A-2 speed, Altera Data Book 98) LE delay: 2.4 ns connection between LE in same LAB: 0.5 ns connection between LE in same row, different LAB:4.7 ns connection between LE in different row: 7.2 ns 6/22/2001 DAC 2001 Tutorial: Jason Cong 71 6/22/2001 DAC 2001 Tutorial: Jason Cong 72

37 Layout-Driven Synthesis Iterative design flow construct-by-correction need to guarantee convergence Concurrent design flow correct-by-construction need to handle design abstraction, constraint propagation, design refinement Best candidate: combination of iterative and concurrent design approaches concurrent synthesis, layout planning, and solution refinement limited number of iterations within the same or adjacent levels to correct unacceptable estimation errors Layout-Driven Synthesis Flow of ADT HDL DESIGN OR NETLIST FROM THIRD PARTY SYNTHESIS TOOL GLOBAL LOGIC OPTIMIZATION AND INTERCONNECT PLANNING PLACEMENT-DRIVEN SYNTHESIS AND ARCHITECTURE EMBEDDING FPGA VENDOR P&R TOOL Source: Courtesy of Aplus Design Technologies, Inc. (ADT) 6/22/2001 DAC 2001 Tutorial: Jason Cong 73 6/22/2001 DAC 2001 Tutorial: Jason Cong 74

38 Use of IP Blocks Field-Programmable System-on-a-Chip (FPSOC) Classification of IP Blocks Soft Hard Firm Challenges IP representation and characterization Interface with synthesis tools IP protection General-Purpose FPSOC processor memory Programmable Logic Application-specific FPSOC processor memory ASIC Programmable Logic 6/22/2001 DAC 2001 Tutorial: Jason Cong 75 6/22/2001 DAC 2001 Tutorial: Jason Cong 76

39 Design Challenges Integration of Embedded operating systems Compilers Synthesis tools Layout tools Need for architecture evaluation Explore and choose the best embedded FPGA architecture (for the given application domain) 6/22/2001 DAC 2001 Tutorial: Jason Cong 77 ArchEvaluator: ADT s PLD Architecture Evaluation Tool Evaluation of programmable logic blocks Sizes Configurations Evaluation of on-chip hierarchy Number of levels Sizes, configuration, and delays at each level Evaluation of heterogeneous architectures Multiple sizes and/or configurations of the same type of logic blocks Multiple types of logic blocks Different kinds of resources on the same chip Embedded Array Configuration Array aspect-ratio Single vs. multiple arrays Source: Courtesy of Aplus Design Technologies, Inc. (ADT) 6/22/2001 DAC 2001 Tutorial: Jason Cong 78

40 Conclusions Synthesis and technology mapping for homogeneous LUTs is a wellunderstood problem (some room for area min.) Recent advances in FPGA synthesis enable many new architecture innovations Embedded memory blocks Heterogeneous LUT based FPGAs Architectures for efficient retiming and pipelining New FPGA synthesis tools and algorithms have to consider layout design support efficient IP re-use Field-programmable logic will be an important component of system-on-a-chip designs Acknowledgments Contributions from Current and former graduate students from my group: Michael Chen (UCLA), Eugene Ding (Agere), Yean-Yow Hwang (Altera), John Peck (AMD), Chang Wu (ADT), and Songjie Xu (ADT) Other colleagues: Peichen Pan (ADT) Supports from National Science Foundation Support from Actel, Altera, Lucent Technologies, Quickturn, Vantis/Lattic, and Xilinx under the California MICRO Program 6/22/2001 DAC 2001 Tutorial: Jason Cong 79 6/22/2001 DAC 2001 Tutorial: Jason Cong 80

41 Further Information Speaker Bio Visit Updated copy of the slides of this talk Survey/tutorial paper on FPGA synthesis Cong and Ding, ACM TODAES, 1996 Recent research publications and software on FPGA synthesis from UCLA JASON CONG received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in Computer Science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Professor and Co-Director of the VLSI CAD Laboratory in the Computer Science Department of University of California, Los Angeles. His research interests include layout synthesis and logic synthesis for high-performance low-power VLSI circuits, design and optimization of high-speed VLSI interconnects, synthesis and architecture design for FPGAs. Dr. Cong is a fellow of IEEE and serves as a consultant or advisory board member for several semiconductor or EDA companies. In 1998, Dr. Cong founded Aplus Design Technologies, Inc. ( which provides innovative layout-driven synthesis solutions and architecture evaluation solutions for both stand-alone FPGAs/CPLDs and embedded FPGAs for SOC designs. 6/22/2001 DAC 2001 Tutorial: Jason Cong 81 6/22/2001 DAC 2001 Tutorial: Jason Cong 82

Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures

Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures Jörn Gause Abstract This paper presents an investigation of Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs)