UG0682 User Guide. Pattern Generator. February 2018
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1 UG0682 User Guide Pattern Generator February 2018
2 Contents 1 Revision History Revision Revision Introduction Hardware Implementation Inputs and Outputs Configuration Parameters Testbench Resource Utilization... 4 UG0682 User Guide Revision 2.0
3 1 Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. 1.1 Revision 2.0 In revision 2.0 of this document, the Resource Utilization section and the Resource Utilization Report table were updated. For more information, see Resource Utilization (see page 4). 1.2 Revision 1.0 Revision 1.0 is the first publication of this document. UG0682 User Guide Revision 2.0 1
4 2 Introduction The pattern generator IP generates the test patterns in RGB Video Format for troubleshooting and analyzing the complete video solutions. The test pattern IP generates following four different types of video test patterns. Color Bar pattern Solid Red Solid Green Solid Blue Figure 1 Top-Level Block Diagram of Pattern Generator The pattern generator IP is configurable and can generate test patterns for any video resolution (1024x768, 1280x720, 1280x800 etc.) for which it is configured. For example if the video resolution is 1024x768 then the value of the parameter g_video_resolution is configured as 32 h400, similarly if the video resolution is 1280x720 then the parameter g_video_resolution is configured as 32 h500. The input signal pattern_type_i defines the type of the video pattern to be generated. If the value of input signal pattern type is 3 b000 Colour Bar pattern is generated 3 b001 solid RED is generated 3 b010 sold GREEN is generated 3 b011 solid Blue is generated The pattern generator IP will generate the patterns based on the input data_enable_i signal, If the data_enable_i signal is high the desired pattern is generated else the output pattern is not generated. This pattern generator IP operates at the system clock CLKIN_i. The output of the pattern generator IP is 24-bit data which comprises of R, G, B data of 8-bit each. The input signals h_sync_i, v_sync_i and data_enable_i, hactive_i,vactive_i are 2-stage flopped inside the pattern generator block to compensate for the latency of R, G and B data and transmitted out as h_sync_o, v_sync_o, data_enable_o, hactive_o and vactive_o respectively. UG0682 User Guide Revision 2.0 2
5 3 Hardware Implementation The following figure shows the color bar pattern generated from the pattern generator. To generate the color bar pattern, a pattern generator counter is implemented. The counter is enabled when the data_enable_i signal is high while it is disabled when the data_enable_i input signal is low. It is a configurable free running counter, when the counter value reached the value configured in parameter video_resolution it resets to zero. Figure 2 Color Bar Pattern Generated from Pattern Generator 3.1 Inputs and Outputs The following table shows the input and output ports of Pattern Generator. Table 1 Inputs and Outputs of Pattern Conversion Signal Name Direction Width Description RSTn_i Input - Active low asynchronous reset signal to design CLKIN_i Input - System clock data_enable_i Input - Data_enable signal, if high Test pattern is generated h_sync_i Input - Horizontal Sync Input v_sync_i Output - Vertical Sync Input hactive_i Output - Horizontal active input signal vactive_i Output - Vertical active input signal Pattern_type_i Output [2:0] Input signal which defines the type of test pattern to be generated R_DATA_o [g_dwidth-1:0] Output R-DATA G_DATA_o [g_dwidth-1:0] Output G-DATA B_DATA_o [g_dwidth-1:0] Output B-DATA Data_enable_o - Output data enable signal H_sync_o - Output sorizontal sync signal V_sync_o - Output vertical sync signal hactive_o - Output horizontal active signal UG0682 User Guide Revision 2.0 3
6 Signal Name Direction Width Description vactive_o - Output vertical active signal 3.2 Configuration Parameters The following table shows the configuration parameters used in the hardware implementation of Pattern Generator. These are generic parameters and can be varied based on the application requirements. Table 2 Configuration Parameters Signal Name g_video_resolution g_count_width g_dwidth Description Width of the data I/O Horizontal resolution bit width Horizontal resolution 3.3 Testbench A test bench has been provided to check the functionality of the pattern generator core. Table 3 Testbench Configuration Parameters Name CLKPERIOD Description Clock Period 3.4 Resource Utilization The following table lists the resource utilization of the Pattern Generator block implemented in the SmartFusion 2 and PolarFire system-on-chip (SoC) FPGA device M2S150T-FBGA1152 package and PolarFire FPGA (MPF300TS_ES - 1FCG1152E package). Table 4 Resource Utilization Report Resource Usage DFFs 25 4-Input LUTs 63 MACC 0 RAM1Kx18 0 RAM64x18 0 UG0682 User Guide Revision 2.0 4
7 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA USA Within the USA: +1 (800) Outside the USA: +1 (949) Fax: +1 (949) Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions; security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees globally. Learn more at UG0682 User Guide Revision 2.0 5
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