CHAPTER 6 DESIGN OF HIGH SPEED COUNTER USING PIPELINING

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1 149 CHAPTER 6 DESIGN OF HIGH SPEED COUNTER USING PIPELINING 6.1 INTRODUCTION Counters act as important building blocks of fast arithmetic circuits used for frequency division, shifting operation, digital alarm clock, computer memory pointers, digital multimeter, Analog to Digital Converters etc., Speed, power consumption and area requirements of counter are specific demands of present day portable VLSI systems. Better operating frequency is realized in Hafeez and Ann Gordon- Ross (2011) and Kakarountas et al (2003) designs using pipelining and carry generation circuit respectively. However the circuits suffer from more hardware complexity for large values of n. To further increase the operating frequency and reduce power dissipation, a parallel counter architecture was proposed in the thesis, with entire architecture divided into modules and least two significant bits of basic module used to excite the higher significant modules. The proposed design methodology is implemented in 16 bit counter with 4 bit up counter as basic and subsequent modules.

2 BASICS OF PARALLEL COUNTING Parallel Counters are series of n flip-flops with 2 n states. The notion of the word parallel is that, a clock pulse is given at-a-time to all the flipflops. It may be fed directly or alternatively it may be ANDed with some other variable (for example output of previous stage, some other stage etc.,). In another design methodology for a n - bit count sequence, n/m blocks are used where m is the count bits of a single block (Figure 6.1). Out of n/m blocks, one is the fundamental block which is m bit up counter and whose count value is used to trigger the subsequent higher count blocks with the aid of a control logic. The control logic generates trigger pulse for the higher count block one count earlier or at all high state of fundamental block depending upon the number of pipelined elements used in the path. The trigger pulse for the second higher count block is generated using the outputs of the fundamental block and first higher count block by the control logic. The trigger pulse is generated one clock pulse earlier or at the high state of fundamental block and higher count block-1 combined. The process of triggering of all the subsequent higher count blocks is done similarly with the aid of pulse generated by control logic using the outputs of fundamental and previous counter blocks. Figure 6.1 Block diagram of n bit parallel counter

3 PROPOSED PARALLEL COUNTER ARCHITECTURE The architecture of the proposed parallel counter consists of basic and subsequent modules, where each subsequent module is triggered from the state transitions of basic and previous modules Synchronous Mode of Operation The circuit connection based on the proposed methodology for a 16 bit counter is shown in Figure 6.2. The circuit consist of basic module (M b ), three subsequent modules (M s1 M s3 ) and State Exciting Logic (SEL). The basic module and subsequent modules are exclusive to the counter design and is a 4 bit up counter for the circuit shown in Figure 6.2. The basic module gives the count values for least significant four bits. Stimulus for triggering subsequent counting modules of higher significance are generated on the clock cycles(positive edge of CLKIN) preceding the final state transition of basic module and all high state of prior subsequent modules and are fed through DFFs in SEL. In synchronous mode of operation the counter s basic module and subsequent modules are triggered by common clock. Figure 6.2 Block diagram of the 16 bit parallel counter(synchronous operation)

4 152 i) Basic Module The basic module is a parallel synchronous 4-bit up counter, with outputs Q 3 Q 2 Q 1 Q 0 and its schematic is shown in Figure 6.3. Here JK flip flops are connected in cascade with AND of previous flip-flop outputs as the J and K input of current flip-flop. The logic that defines Q 3, Q 2, Q 1 and Q 0 are given by Equation (6.1) to Equation (6.4). Q 0 (t+1) = J 0 Q 0 '(t) + K 0 'Q 0 (t) (6.1) Q 1 (t+1) = Q 0 Q 1 ' (t) + Q 0 'Q 1 (t) (6.2) Q 2 (t+1) = Q 1 Q 0 Q 2 '(t) +(Q 1 Q 0 ) 'Q 2 (t) (6.3) Q 3 (t+1) = Q 2 Q 1 Q 0 Q 3 ' (t) +(Q 2 Q 1 Q 0 )'Q 3 (t) (6.4) Figure 6.3 Schematic diagram of basic module -M b Initially all the flip-flops of basic module will be reset to 0. On giving J=1 and K=1 to the first flip-flop, its output gets alternating between 1 & 0 & 1 for each clock pulse. Since the first flip-flop output is given to J and K input of second flip flop, each 1 output of first flip-flop toggles the second flip-flop output between 1 and 0. Since AND of first and second flip-flop

5 153 outputs are used for third flip-flop J,K input each 11 state corresponding to first and second flip-flop toggles the third flip-flop and so on. Once this block reaches the state preceding final transition i.e., (Q 3 =1,Q 2 =1,Q 1 =1, Q 0 =0), the state outputs are encoded through an AND-logic to produce a valid high-state output for enable signal TRG 1. The TRG 1 = Q 3 Q 2 Q1notQ 0 is fed through DFF in SEL to trigger subsequent module M s1 through its STR control input.the advantage of using JK flip-flop in the basic module is that it gets toggled (i.e., alternate 0 and 1) when both J and K are 1. This avoids the use of extra combinational logic as in case of D flip-flops and thus reduces the area overhead. ii) Subsequent Modules The subsequent modules (M si s) used in the proposed counter are 4 bit up counters triggered by positive edge of the clock. Figure 6.4 depicts the schematic and the Equation(6.5) to Equation(6.8) defines the output (Q si3 Q si2 Q si1 Q si0 ) of subsequent module Q si0 (t+1)=strxorq si0 (t) (6.5) Q si1 (t+1)=[str'q si1 (t)orstr(q si1 (t)xorq si0 (t))] (6.6) Q si2 (t+1) = [STR Q si2 (t)] or [STR [[Q si2 (t) (Q' si1 (t))] or [Q si2 (t)(q' si0 (t))]or [(Q' si2 (t))(q si1 (t)q si0 (t))] (6.7) Q si3 (t+1)=[str'&q si3 (t)]or[str&q si3 (t)&q' si2 (t)]or [Q si3 (t)&(q' si1 (t))]or[q si3 (t)&q' si0 (t)]or [Q' si3 (t)&q si2 (t)&q si1 (t)&q si0 (t)] (6.8) The counting operations of subsequent modules are enabled by a high at its STR input. Each high at the STR input increments the subsequent module output by 1. The subsequent module M s1 gets triggered by a high at

6 154 TRG 1 which is generated by SEL from the outputs of basic module. The enable signal for subsequent module M s2 is TRG 2 which is an AND of subsequent module M s1 and basic module [Q s13 Q s12 Q s11 Q s10 & Q 3 Q 2 Q 1 not (Q 0 )] outputs fed through DFF. Since one flip-flop is used in the path of trigger pulse, it is generated one state prior to all high state of basic module. Figure 6.4 Schematic diagram of subsequent module-m si The enable signal for subsequent module M s3 is TRG 3 which is an AND operation of basic and prior subsequent module represented as Q s23 Q s22 Q s21 Q s20 &Q s13 Q s12 Q s11 Q s10 & Q 3 Q 2 Q 1 not (Q 0 ) fed through DFF. It is seen that trigger pulse is generated one state prior to all high state of basic module since one DFF is used in the path. Enabling of a M si module one state prior to all high state of previous subsequent modules and basic module combined (one clock cycle ahead) maintains proper setup time to DFFs in the enable path.

7 155 iii) State Exciting Logic SEL operates similar to encoder circuit in that it encodes the counter outputs of modules of lower significance modules and carries this output to trigger modules of higher significance. Figure 6.5 depicts the schematic of SEL. The SEL generates the enable signals (STR input) for the three subsequent modules (M s1 -M s3 ) viz., TRG 1 TRG 2 and TRG 3 represented in Equation (6.9) to Equation (6.11). TRG 1 =DFF[Q 3 Q 2 Q 1 not(q 0 )] (6.9) TRG 2 =DFF[Q 3 Q 2 Q 1 not(q 0 )& Q s13 Q s12 Q s11 Q s10 ] (6.10) TRG 3 = DFF[Q 3 Q 2 Q 1 not(q 0 )& Q s13 Q s12 Q s11 Q s10 & Q s23 Q s22 Q s21 Q s20 ] (6.11) Figure 6.5 Schematic diagram of SEL

8 156 TRG 1 is set to high one state prior to all high state of basic module as one DFF is used in the path of TRG 1 in SEL. Similarly from the Equation(6.10) it can be seen that TRG 2 and TRG 3 are generated one state prior to all high state of basic module as both these signals have one DFF in their path as seen from schematic of SEL Asynchronous Mode of Operation The circuit connections of the proposed parallel counter in asynchronous mode of operation for a sample 16 bit counter is shown in Figure 6.6. Figure 6.6 Block diagram of proposed 16 bit parallel counter (asynchronous operation) In asynchronous mode clock pulses are not used to trigger the basic and subsequent modules, instead the state transition preceding the final state of previous module is used to excite next module. In this mode the same counter modules (i.e. basic and subsequent) used for synchronous counter design are used. Here Q 3 ' (Q 3 bar) of basic module is connected to CLK and STR of subsequent module M S1, Q S13 ' (Q S13 bar) of subsequent module M S1 is connected to CLK and STR of subsequent module M S2, Q S23 ' (Q S23 bar) of subsequent module M S2 is connected to CLK and STR of subsequent module M S3. At the start Q 3 of basic module is 0, CLK and STR input of subsequent module M S1 will be high. Since the flip flops of subsequent module are

9 157 positive edge triggered, all flip flops of subsequent module M S1 will be in idle state. When the basic module output reaches all high state, its output Q 3 changes from 1 to 0 in next cycle, Q 3 ' changes from 0 to 1. This change in Q 3, triggers the subsequent module M S1 as it is positive edge triggered. Each change of Q 3 ' of basic module from 1 to 0 triggers the subsequent module and its count increases by 1. Similarly when the output of subsequent module M S1 reaches all high state (i.e. Q S13 Q S12 Q S11 Q S10 = 1111), Q S13 changes from 1 to 0 in next clock pulse. This change in Q S13 triggers subsequent module M S2 as Q S13 ' is connected to CLK and STR input of subsequent module M S2. In the same way when the subsequent module M S2 reaches all high state, Q S23 changes from 1 to 0 in next pulse. This triggers the subsequent module M S3 as its CLK and STR input are connected to Q S23 '. Each triggering by Q S23 increments the count of subsequent module M S3 by 1. The process continues till the output of M S3 reaches all high state during which the counter attains its maximum count value after which it is reset to initial position Enhanced counter design using JK flip-flop As a modification to the proposed counter design, an implementation of subsequent module using JK flip-flop is done and its schematic is shown in Figure 6.7. Here JK input of first flip-flop is connected to STR which is always maintained at 1, toggles the flip-flop for each clock pulse. A high at the output of first flip-flop triggers the second flip-flop as JK inputs of second flip-flop are connected to Q output of first flip-flop. The JK inputs of third flip-flop are derived from AND of first and second flip-flop outputs. So a high at the output of first and second flip-flop triggers the third flip-flop. Similarly high at the output of first, second and third flip-flop triggers the fourth flip-flop as its JK inputs are derived from AND of Q outputs of first, second and third flip-flops.

10 158 Figure 6.7 Schematic of subsequent module implemented with JK flipflop Equation (6.12) to Equation(6.15) define the outputs (Q jk si3q jk si2q jk si1q jk si0) of this module and are given by Q jk si0(t+1)=strxorq jk si0(t) (6.12) Q jk si1(t+1)=[str&q jk si0(t)]xorq jk si1(t) (6.13) Q jk si2(t+1)=[ STR&Q jk si0(t)&q jk si1(t)] xorq jk si2(t) (6.14) Q si3 (t+1)=[ STR&Q jk si0(t) & Q jk si1(t) &Q jk si2(t)]xorq jk si3(t) (6.15) where i denotes the position of subsequent module. The JK flip-flop implementation of subsequent module is simple and offers versatility in extension to higher bit counters with ease. In addition the use of extra combinational logic to derive the flip-flop inputs is significantly reduced when compared with the subsequent module implemented with DFF.

11 RESULTS AND PERFORMANCE ANALYSIS The proposed counter and its counterparts are designed using VHDL code and synthesized using Altera Quartus II tool. Kakarountas et al(2003) and Hafeez and Ann Gordon-Ross (2011) counters are used for comparison. a) Functional Evaluation The simulation outputs of the proposed 16 bit parallel counters are synthesized at 250 GHz operating frequency using HDL description and shown in Figure 6.8, Figure 6.9 and Figure Figure 6.8 Timing waveform of the proposed 16 bit counter- synchronous operation, at 250 GHz clock frequency

12 160 Figure 6.9 Timing waveform of the proposed 16 bit counter- asynchronous operation( using D Flip-flop), at 250 GHz clock frequency Figure 6.10 Timing waveform of the proposed 16 bit counter asynchronous operation (using JK flip-flop), at 250 GHz clock frequency

13 161 The vertical axis shows magnitude while the horizontal axis represents time scale in nanoseconds. The input clock is fed through a CMOS buffer for a near practical simulation environment. The sufficient setup times at DFFs input to generate each output of subsequent module gives regular and uniform output and suggests the suitability of the proposed architecture for high counter operating frequencies. b) Performance Evaluation The performance parameters like power dissipation and delay of the proposed counters and prior arts were extracted at 250 MHz operating frequency and shown in Table 6.1. From the reports of Altera Quartus II power analysis tool it is found that the power dissipation of the proposed counters (synchronous and asynchronous) is better compared to Kakarountas et al (2003) and Hafeez and Ann Gordon-Ross (2011) counters. However the proposed counter and parallel counter designs (Hafeez and Ann Gordon-Ross 2011), (Kakarountas et al 2003) demonstrate high power dissipation compared to conventional designs. The delay of the proposed counter (Synchronous) is better compared to Kakarountas et al (2003), Hafeez and Ann Gordon-Ross (2011) and conventional counters (synchronous design). The proposed counter (asynchronous connected) demonstrates better delay performance compared to conventional design(asynchronous connected). Plots of delay of proposed counters and previous approaches are shown in Figure 6.11 and Figure The better delay performance of the proposed parallel counter (synchronous) exhibits the best PDP performance compared to all other architectures. The PDP performance of the proposed parallel counter (asynchronous) is better compared to conventional design (asynchronous connected). This is due to the triggering of high end subsequent modules from the outputs of basic and

14 162 previous modules which decreases delay. Plots of PDP of proposed counters and previous approaches are shown in Figure 6.12 and Figure The proposed asynchronous counter implemented with JK flip-flop demonstrates better area reduction compared to Kakarountas et al (2003) and Hafeez and Ann Gordon-Ross (2011) and conventional designs (synchronous connected). This is due to the elimination of SEL in the proposed counter (asynchronous) and simpler combinational logic to feed J and K inputs. In addition, the transistor count for each individual module of the proposed counters is calculated and is shown in Table 6.2. Table 6.1 Comparison of proposed 16 bit counter designs with conventional, Kakarountas et al(2003) and Hafeez and Ann Gordon-Ross (2011) counters Hafeez Parameter Kakarountas et al (2003) Kakarountas et al (2003) Improved Conventional- Conventional- Sync. Async. and Ann Gordon- Ross Proposed Proposed Proposed- (Async.- (Async. - Sync. DFF) JKFF) (2011) Total power(mw) Delay(ns) PDP(E-12 Joules) Area in transistor count

15 163 Figure 6.11 Delay of proposed synchronous counter and previous designs Figure 6.12 PDP of proposed synchronous counter and previous designs Figure 6.13 Delay of proposed asynchronous counters and conventional design

16 164 Figure 6.14 PDP of proposed asynchronous counters and conventional design Table 6.2 Transistor count of components used in proposed 16 bit parallel counter designs Counter Basic M b M3 (Module-3S) Module- State- Exciting logic Combinational logic Total Proposed (Sync) Proposed (async- JK FF) Proposed (async- D FF) It is seen that the use of JK flip-flops in subsequent module reduces the transistor count by 51% and 59% respectively compared to its DFF counterpart, thanks to the toggling nature of JK FF which eliminates the need for complex combinational logic design at flip-flop input.

functionality of the proposed counter, an implementation in a frequency divider cum squarer circuit is

The input to the circuit is a 16 bit number (I 15 I 14 I 1 I 0 ) which sets the end of count operation

$.Q 1 Q 0 is a fraction of total count value of the parallel counter it is called as frequency division.$

17 IMPLEMENTATION OF THE PROPOSED COUNTER IN FREQUENCY DIVIDER CUM SQUARE FINDER CIRCUIT To verify the functionality of the proposed counter, an implementation in a frequency divider cum squarer circuit is done, whose block diagram is shown in Figure The input to the circuit is a 16 bit number (I 15 I 14 I 1 I 0 ) which sets the end of count operation after a RES pulse. Since the output represented by Q 15 Q 14..Q 1 Q 0 is a fraction of total count value of the parallel counter it is called as frequency division. Figure 6.15 Block diagram of Frequency divider cum squarer circuit The square finder circuit which has an accumulator unit shown in Figure 6.16, on the other hand accumulates Q 15 Q 14..Q 1 Q 0 after each RES pulse till the end of final count value of parallel counter thus achieving square output of I 15 I 14 I 1 I 0.

18 166 Figure 6.16 Block diagram of accumulator unit Figure 6.17 Output waveform of Frequency divider cum squarer circuit using synchronous counter

19 167 Figure 6.18 Output waveform of Frequency divider cum squarer circuit using asynchronous counter The output waveform corresponding to the frequency divider cum squarer circuit is shown in Figure 6.17 and Figure A plot of delay of the frequency divider cum square finder circuit implemented with the proposed, Hafeez and Ann Gordon-Ross (2011) and conventional designs is shown in Figure It is found that the proposed counter implemented system demonstrates better delay performance both in synchronous and asynchronous operation.

168 Figure 6.19 Normalized delay of Frequency divider cum squarer circuit implemented with proposed, conventional and Hafeez and Ann Gordon-Ross (2011) counters 6.

The proposed counter design is comprised of modules which are up counters and a state exciting logic for controlling the operation of the modules.

20 168 Figure 6.19 Normalized delay of Frequency divider cum squarer circuit implemented with proposed, conventional and Hafeez and Ann Gordon-Ross (2011) counters 6.6 CONCLUSION A methodology for design of parallel counter which can operate at high frequencies is presented. The proposed counter design is comprised of modules which are up counters and a state exciting logic for controlling the operation of the modules. The features of the proposed counter are triggering of individual modules from pulse generated from basic and prior subsequent modules, avoiding usage of a long chain of AND rippling as in conventional designs for large counter widths. This consequently improves the counter operating frequency significantly. Since the counter architecture is designed from basic module and copies of subsequent module, design of large counter architectures is attractive and easy. Synthesis reports demonstrates better performance of the proposed design methodology implemented in a 16 bit counter in terms of delay reduction compared to previous works at high operating frequencies. An implementation of the proposed counter in a frequency divider cum squarer circuit is done to verify its functionality.

Low Power Area Efficient Parallel Counter Architecture

Low Power Area Efficient Parallel Counter Architecture Lekshmi Aravind M-Tech Student, Dept. of ECE, Mangalam College of Engineering, Kottayam, India Abstract: Counters are specialized registers and is