A High-Speed CMOS Image Sensor with Column-Parallel Single Capacitor CDSs and Single-slope ADCs

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1 A High-Speed CMOS Image Sensor with Column-Parallel Single Capacitor CDSs and Single-slope ADCs LI Quanliang, SHI Cong, and WU Nanjian (The State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing , P.R. China) ABSTRACT This paper presents a high speed CMOS image sensor (CIS) with column-parallel single capacitor correlated double samplings (CDSs), programmable gain amplifiers (PGAs) and single-slope analog-to-digital converters (ADCs). The single capacitor CDS circuit has only one capacitor so that the area CDS circuit is small. In order to attain appropriate image contrast under different light conditions, the signal range can be adjusted by PGA. Single-slope ADC has smaller chip area than others ADCs and is suitable for column-parallel CIS architectures. A prototype sensor of pixels was realized in a 0.13μm 1P3M CIS process. Its pixel circuit is 4T active pixel sensor (APS) and pixel size is 10 10μm 2. Total chip area is 4 4mm 2. The prototype achieves the full frame rate in excess of 250 frames per second, the sensitivity of 10.7V/lx s, the conversion gain of 55.6μV/e and the column-to- column fixed-pattern noise (FPN) 0.41%. CMOS image sensor, Correlated double sampling, Programmable gain amplifier, Single-slope ADC, 4T, FPN 1 INTRODUCTION Due to benefit of lower power consumption, lower voltage operation, on-chip functionality and compatibility with standard CMOS technology, random access of image data, and lower cost [1],recent advances in CMOS image sensors have made them viable alternatives to charge-coupled devices (CCD), particularly in high-speed camera. A high-speed camera is a useful tool for the observation of high-speed phenomena, analysis of high-speed machinery and sports and so on. There are three general approaches to implementing ADC with active pixel sensors: chip level ADC, column level ADC, and pixel level ADC [2]. The chip level ADC uses only single ADC for an entire pixel array. Hence, extremely high-speed ADC should be required to achieve a high frame rate. The pixel-level ADC implements an ADC in every pixel, providing extremely high frame rate at the price of silicon area and power consumption. The column- parallel ADC which has an ADC in one or more columns of pixel array can achieve a good trade-off among frame-rate, the number of ADC, the data conversion rate of single ADC, noise performance, and power consumption. To achieve very high data conversion rate, many CISs employ column-parallel ADC architecture [4-6].There are many kinds of ADCs for column-parallel CISs. Successive approximation ADC (SAR) [4], cyclic ADC [5] and single slope ADC [6] have been utilized for column-parallel CISs. A single slope ADC is much simpler than other ADCs,which mainly consists of a International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Imaging Detectors and Applications, edited by Makoto Ikeda, Nanjian Wu, Guangjun Zhang, Kecong Ai, Proc. of SPIE Vol. 8194, SPIE CCC code: X/11/$18 doi: / Proc. of SPIE Vol

2 single comparator and requires much less chip area and power consumption than a SAR or cyclic ADC. Moreover, this simple circuit also makes it relatively easy to ensure uniformity between columns and thus minimizes the column-to-column fixed-pattern noise. As a result, single-slope is very suitable for the column parallel architecture. In this paper, single-slope ADC acts as column parallel ADC. Correlated double sampling (CDS) circuit is also a key building block in a CMOS imager. The CDS circuit can reduce pixel reset noise, pixel fixed pattern noise (FPN), and flicker noise [3]. FPN is the primary noises of the CMOS imager, which is caused by random variations in the threshold voltage of the reset and source-follow transistors, variations in the photodetector geometry and variations in the dark current. In conventional designs, CDS circuit consists of two sets of sampling and hold (S/H) circuits and a differential amplifier [2]. The basic S/H circuit consists of a switch and a capacitor. This paper presents a high speed CMOS image sensor (CIS) with column-parallel single capacitor correlated double samplings (CDSs), programmable gain amplifiers (PGAs) and single-slope analog-to-digital converters (ADCs). The CDS circuit uses only one capacitor. Compared to conventional CDS circuit, single capacitor CDS requires less chip area. In order to attain appropriate image contrast under different light conditions, the signal range can be adjusted by PGA. Single-slope ADC has smaller chip area than others ADCs and is suitable for column-parallel CIS architectures. The rest of the paper is organized as follows. In section 2, the architecture of high speed CIS, the single capacitor CDS, the programmable gain amplifier and the single slope ADC are presented. In section 3, the experimental results will be presented. Finally, conclusions are drawn in section 4. 2 ARCHITECTURE OF HIGH SPEED CIS 2.1 Overall Block Diagram Figure1. The Overall Block Diagram of this CIS The overall block diagram of this high speed CIS is shown in Figure 1. In addition to the pixel array, the sensor consists of CDS array, PGA array, single-slope ADC array, data storage and output, and controlling modules. The Proc. of SPIE Vol

3 controlling module controls pixel array to operate and to output the image data row by row. First CDS array samples pixel signals after pixel reset operation and signal charge and outputs a difference signal between the reset and signal values. Then the signal is amplified by the PGA, and next the signal is quantified by single-slope ADC. The output data of ADC is stored in data storage unit and outputted by I/O interface T Pixel and CDS The pixel consists of a pinned photodiode (PPD), four transistors M1~M4 for pixel reset and readout. The CDS schematic consists of a capacitor C1, one reset transistor M6 and buffer M7. M5 and M8 are bias transistors. The schematic of 4T APS and single capacitor CDS, the timing diagram of the CDS circuit are shown in figure 2.CDS works as following: V CDS V pix RST CDS Vb Vb AbTX MT (a) (b) Figure2. The Schematic of 4T APS and the Single Capacitor CDS (a), and the Timing Diagram of the CDS Circuit (b) First, RST and SEL are high, RST CDS is low, and M2, M4, and M6 are on. The nodes A and B are charged to V RST +Vpix_offset and V CDS, respectively. As a result, the sampling capacitor C1 stores the charge of C1*(V CDS -V RST -Vpix_offset). Second, RST becomes low, TX and RST CDS become high, and M1 is on, while M2 and M6 are off. The node A is charged to Vsig+Vpix_offset and node B is floating, the voltage of node B is V B. So, C1 stores the charge of C1*(V B -Vsig-Vpix_offset). Considering the charge on the capacitor yields: C1 V CDS V RST V _ C1 V B V V _ (1) Then, V B V CDS V RST V (2) As shown in equation (2), the pixel offset voltage V pix_offset is eliminated. Where V RST is the pixel reset voltage, Vsig is the pixel signal voltage, and Vpix_offset is the pixel offset voltage including reset noise and fixed pattern noise. 2.3 PGA Proc. of SPIE Vol

4 The operation of PGA is divided into two models: (a) initialization and sampling and (b) amplifying, as illustrates in figure 3.In initialization and sampling model, switch S1, S3 are on, S2 is off, and the charge of C3 is discharged to zero, Vin is sampled on C2. Then PGA enters into amplifying model, switch S1, S3 become off, S2 turns on, the charge of C2 transfers into C3.Considering the charge on the node C yields: So C2 V C3 V (3) C C V (4) Where V in is the output of CDS, and V out is the output of PGA. The gain of PGA is determined by ratio of C2 and C3. C3 is a programmable capacitance, and its value can be changed by adjusting the control word. Thereby, the gain of PGA can be programmed by adjusting the value of C3. AOfTI (a) (b) Figure3. The Operation of PGA: (a) Initialization and Sampling and (b) Amplifying 2.4 Single Slope ADC ALJ1JJb jçrnjb ç ALWb COflUL ACOUJb COflUL (a) (b) Figure4. The architecture (a) and the timing diagram (b) of single slope ADC The single-slope ADC consists of ramp generator, comparator, counter and latch. Figure 4 shows the architecture of 8-bit single-slope ADC and the timing diagram to operate single-slope ADC. V in is compared with ramp voltage V ramp, which is generated by the ramp generator. V ramp value is determined by the counter. When Vin and Vramp crisscross, the Proc. of SPIE Vol

output of comparator becomes from high to low, and the output data of counter are latched. The latched data are the outputs of single-slope ADC.

So, most of the ADC s area is occupied by comparator and the single-slope requires smalll chip area. 3 EXPERIMENTAL RREULTS The chip is fabricated in 0.13μm CMOS process.

There is 256 column-parallel readout paths (a unit with a CDS, a PGA, and a single-slope ADC) at the bottom of the pixel array.

5 output of comparator becomes from high to low, and the output data of counter are latched. The latched data are the outputs of single-slope ADC. For column-parallel CIS, the ramp generator and counter of the single-slopee ADC can be shared by every column, and data-latch s area is small. So, most of the ADC s area is occupied by comparator and the single-slope requires smalll chip area. 3 EXPERIMENTAL RREULTS The chip is fabricated in 0.13μm CMOS process. The microphotograph of the chip is shown in Figure 5. Pixel array is , and pixel pitch is 10μm.There is 256 column-parallel readout paths (a unit with a CDS, a PGA, and a single-slope ADC) at the bottom of the pixel array. There is a controlling module at the left of chip, which controls pixel array, CDS, PGA, ADC, and data storage and outputt to operate according to the timing diagram of chip. Under FPGA controlling, image data transfer from CIS chip to computer. Figure 6 shows a sample image taken by the prototype chip at 250fps. The summary of this chip is shown in table 1. Figure5. Microphotograph of the fabricated CIS Figure6. A sample image taken by the prototype chip Table1. Information of CIS Process 0.13μm CIS process Power Supply 3.3 V (Analog)/1.5 V (Digital) Pixel Array Pixel Size μm 2 Pixel Type 4T FF 77% ADC Single-slope ADC ADC resolution 8 bit Sensitivity 10.7V/lx s Conversion Gain 55.6μV/ /e Col.-to-Col. FPN(dark) 0.41% Proc. of SPIE Vol

6 4 CONCLUSION A CMOS image sensor was fabricated and tested. It has 3.3 V analog power supply, and 1.5 V digital power supply. The column readout circuit consists of single capacitor CDS, PGA and single-slope ADC. Its pixel size is μm 2. Total chip area is 4 4 mm 2 which includes bond pads. The prototype chip achieves the full frame rate in excess of 250 frames per second, the sensitivity of 10.7V/lx s, the conversion gain of 55.6μV/e and the column-to-column FPN 0.41%. REFERENCES [1] Bigas, M., Cabruja, E., Forest, J. and Salvi, J., Review of CMOS image sensors, Microelectronics Journal,Papers 37, (2006). [2] Ohta, J.,[Smart CMOS Image Sensors and Applications], CRC Publishers, Boca Raton, London & New York, 46-47(2007). [3] Kawai, N. and Kawahito, S., Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensor, IEEE Trans. Electron Devices, Papers 51, (2004). [4] Matsuo, S.; Bales, T.J.; Shoda, M.; Osawa, S.; Kawamura, K.; Andersson, A.; Munirul Haque; Honda, H.; Almond, B.; Yaowu Mo; Gleason, J.; Chow, T.; Takayanagi, I., 8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC, IEEE Trans. Electron Devices, Papers56( 11), , (2009). [5]. Jong, H. P., Aoyama, S., Watanabe, T., Isobe, K.; Kawahito, S., A high-speed low-noise CMOS image sensor with 13-b column-parallel single-ended cyclic ADCs, IEEE Trans. Electron Devices, Papers56( 11), (2009). [6] Lee, D., Cho, K., Kim, D., and Han, G., Low-noise in-pixel comparing active pixel sensor using column-level single-slope ADC, IEEE Trans. Electron Devices, Papers 55(12), ,(2008). Proc. of SPIE Vol

PERFORMANCE ANALYSIS OF AN EFFICIENT TIME-TO-THRESHOLD PWM ARCHIECTURE USING CMOS TECHNOLOGY

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